Patent application number | Description | Published |
20080251860 | Semiconductor Memory Device - The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line. | 10-16-2008 |
20080252388 | Oscillator and charge pump circuit using the same - The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor. | 10-16-2008 |
20080298156 | SEMICONDUCTOR DEVICE UNDERGOING DEFECT DETECTION TEST - A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode. | 12-04-2008 |
20090003091 | Semiconductor Device - There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path. | 01-01-2009 |
20090022001 | SEMICONDUCTOR MEMORY DEVICE - By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON. | 01-22-2009 |
20090058543 | Temperature detecting semiconductor device - There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals. | 03-05-2009 |
20090079407 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention provides a regulator circuit that can fast-respond to a variation in load current and supply a sufficient drive current so as to be capable of generating a stable internal source voltage. The regulator circuit includes a preamplifier circuit that detects and amplifies a different between a reference voltage and an internal source voltage, a clamp circuit that limits the amplitude of an output of the preamplifier circuit, a main amplifier circuit that amplifies the amplitude-limited output of the preamplifier circuit, and a driver circuit that outputs the internal source voltage according to the output of the main amplifier. Even though the internal source voltage varies abruptly, the regulator circuit does not oscillate owing to the effect of the clamp circuit. | 03-26-2009 |
20090102544 | SEMICONDUCTOR DEVICE INCLUDING DETECTOR CIRCUIT CAPABLE OF PERFORMING HIGH-SPEED OPERATION - A detector circuit and a negative voltage generating circuit capable of performing a high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors make the voltage division between the negative voltage and the power supply to obtain the detect potential. | 04-23-2009 |
20100033609 | SOLID STATE IMAGING DEVICE - To obtain a solid state imaging device having a data transfer function capable of outputting digital data after A/D conversion to the outside in a high speed. | 02-11-2010 |
20100109761 | SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT - A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented. | 05-06-2010 |
20100165691 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. | 07-01-2010 |
20100188120 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit. | 07-29-2010 |
20100231768 | SOLID-STATE IMAGE PICKUP DEVICE - There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space. | 09-16-2010 |
20110127609 | SEMICONDUCTOR MEMORY DEVICE - The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line. | 06-02-2011 |
20110182131 | SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT - A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented. | 07-28-2011 |
20110221419 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors. | 09-15-2011 |
20120170344 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 07-05-2012 |
20130010513 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 01-10-2013 |
20140126264 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 05-08-2014 |