Patent application number | Description | Published |
20080251849 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device comprising a first semiconductor region and a second semiconductor region,
| 10-16-2008 |
20090014795 | Substrate for field effect transistor, field effect transistor and method for production thereof - A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition. | 01-15-2009 |
20090027947 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced. | 01-29-2009 |
20090144618 | Method and apparatus for displaying text information and numerical information in association with each other - A method and apparatus for associating text information with numerical information. A first phrase corresponding to a time period is generated. The first phase represents a change in first numerical information over the time period. The first numerical information includes time-series data pertaining to a financial index. The text information is retrieved through use of a retrieval condition that includes the first phrase. The first numerical information is retrieved through use of the retrieval condition and the first phrase. The extracted text information and the retrieved first numerical information are outputted in association with each other. | 06-04-2009 |
20090172415 | PROCESSOR APPARATUS - The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption. | 07-02-2009 |
20090201063 | DYNAMIC SEMICONDUCTOR DEVICE - A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased. | 08-13-2009 |
20100130103 | POLISHING APPARATUS AND PROGRAM THEREOF - A polishing apparatus includes a loading section ( | 05-27-2010 |
20100141301 | LOGIC CIRCUIT, ADDRESS DECODER CIRCUIT AND SEMICONDUCTOR MEMORY - Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential. | 06-10-2010 |
20100149887 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING POWER SOURCE - A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained. | 06-17-2010 |
20110032741 | SEMICONDUCTOR MEMORY DEVICE - The SRAM cell is formed by an inverter circuit (P | 02-10-2011 |
20120257442 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line. | 10-11-2012 |