Patent application number | Description | Published |
20080251849 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device comprising a first semiconductor region and a second semiconductor region,
| 10-16-2008 |
20090014795 | Substrate for field effect transistor, field effect transistor and method for production thereof - A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition. | 01-15-2009 |
20090033403 | LEVEL CONVERTING CIRCUIT - A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. | 02-05-2009 |
20090201063 | DYNAMIC SEMICONDUCTOR DEVICE - A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased. | 08-13-2009 |
20090274575 | PRECISION ALLOY - A precision alloy for die-casting contains aluminum, silicon and zinc, wherein on the basis of the overall mass, the content of aluminum is 40% by mass or more and 45% by mass or less, and the content of silicon is 2% by mass or more and 8% by mass or less. Also other solving means will be described. | 11-05-2009 |
20100033235 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor. | 02-11-2010 |
20100327961 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY VOLTAGE CONTROL SYSTEM - A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit. | 12-30-2010 |
20110285478 | PRECISION ALLOY - A precision alloy for die-casting contains aluminum, silicon and zinc, wherein on the basis of the overall mass, the content of aluminum is 40% by mass or more and 45% by mass or less, and the content of silicon is 2% by mass or more and 8% by mass or less. Also other solving means will be described. | 11-24-2011 |
20130070402 | COMMUNICATION DEVICE AND PRODUCING METHOD FOR ENCLOSURE OF THE SAME - An enclosure that contains a transmission section and a reception section of an ODU is protected against hard environments without it being necessary to apply a coating of paint to the enclosure. The present invention is communication device (ODU) ( | 03-21-2013 |
20130181872 | COMMUNICATION APPARATUS - The purpose of the present invention is to reduce the cost of a product while ensuring reliability of the product as a wireless transmission/reception apparatus. Provided is communication apparatus (ODU) (1) installed outside, which includes a case that houses a transmission unit for transmitting a signal and a reception unit for receiving the signal, and a waveguide connected to an external antenna and configured to receive/transmit a signal. In the apparatus, the waveguide is formed integrally with the case, and taper (16) is formed in a part of the tube hole of the waveguide. | 07-18-2013 |
Patent application number | Description | Published |
20100117705 | Semiconductor integrated circuit device having plural delay paths and controller capable of Blocking signal transmission in delay path - A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path. | 05-13-2010 |
20100295530 | Power supply voltage control circuit - A power supply voltage control circuit controls power supply voltage supplied to a target circuit that performs certain signal processing. The power supply voltage control circuit includes a control signal generation circuit that selectively generates first and second control signals when the power supply voltage supplied to the target circuit is increased from a first power supply voltage to a second power supply voltage, the second power supply voltage being higher than the first power supply voltage, and a power supply circuit that increases the power supply voltage toward a voltage level of the second power supply voltage based on the first control signal, or increases the power supply voltage to a voltage level higher than the second power supply voltage first and subsequently decreases the power supply voltage to the second power supply voltage based on the second control signal. | 11-25-2010 |
20110175658 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING VOLTAGE CONTROL METHOD - A semiconductor integrated circuit includes a first circuit part that is designed under a first corner condition with respect to a process variation, a second circuit part that is designed under a second corner condition narrower than the first condition, and a control part that changes an operating voltage supplied to the first circuit part and the second circuit part according to a delay amount of the first circuit part, and starts the second circuit part when a delay characteristic caused by a change in the operating voltage conforms to a delay characteristic under the second corner condition. | 07-21-2011 |
20110187419 | SEMICONDUCTOR INTEGRATED CIRCUIT AND VOLTAGE CONTROLLER THEREWITH - A semiconductor integrated circuit is capable of accurately detecting the characteristics of a chip. The semiconductor integrated circuit includes a monitor circuit and a control circuit. The control circuit generates a clock pulse signal having M successive pulses (M is 2 or a greater integer), and outputs the clock pulse signal to the monitor circuit. The monitor circuit includes a frequency divider and a ring oscillator. The frequency divider frequency divides the clock pulse signal by M and generates the resulting signal as an enable signal. The ring oscillator generates an oscillation signal as a monitor output value during a period defined in accordance with the enable signal. | 08-04-2011 |
20110241725 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value. | 10-06-2011 |
20120182047 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM - A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops. | 07-19-2012 |
20120218016 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING PLURAL DELAY PATHS AND CONTROLLER CAPABLE OF BLOCKING SIGNAL TRANSMISSION IN DELAY PATH - A semiconductor integrated circuit device, includes a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal, a delay detection unit that detects respective delay times in the plurality of delay paths, and a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path. The control unit selects, as one delay path, a delay path whose delay time is a middle value among the plurality of delay paths. | 08-30-2012 |
Patent application number | Description | Published |
20090014095 | HIGH-STRENGTH COLD ROLLED STEEL SHEET EXCELLING IN CHEMICAL TREATABILITY - The invention provides a high strength cold rolled steel sheet having excellent chemical conversion treatment property stably even Mo is added aiming high strengthening. The surface property of the cold rolled steel sheet satisfies that the characteristic of 10 μm or more of the maximum depth (Ry) of the unevenness and 30 μm or less of the average spacing (Sm) of the unevenness, and that either one or more preferably both of, the characteristic of the load length ratio (tp40) of the unevenness of the surface is 20% or less, and the characteristic of the difference of the load length ratios (tp60) and (tp40) is 60% or more, is satisfied, and the crack of 3 μm or less width and 5 μm or more depth does not exist on the surface. | 01-15-2009 |
20090032148 | HIGH-STRENGTH HOT-ROLLED STEEL SHEET EXCELLENT IN CHEMICAL TREATABILITY - There is provided a high-strength hot rolled steel sheet excellent in phosphatability, wherein a maximum depth (Ry) of pits and bumps, existing on a surface thereof, is not less than 10 μm, and an average interval (Sm) of the pits and the bumps is not more than 30 μm, meeting either a requirement for a load length ratio (tp40) of the pits and the bumps on the surface at not more than 20%, or a requirement for a difference between a load length ratio (tp60) and the load length ratio (tp40), at not less than 60%, or both thereof. The high-strength hot rolled steel sheet is capable of exhibiting stable and excellent phosphatability even if Mo highly effective for reinforcement in strength is added thereto in expectation of a higher strength. | 02-05-2009 |