Patent application number | Description | Published |
20080237684 | Method of manufacturing a nanowire transistor, a nanowire transistor structure, a nanowire transistor field - A method of manufacturing a nanowire transistor includes oxidizing at least a portion of a semiconductor carrier. The semiconductor carrier includes a first carrier portion and a second carrier portion above the first carrier portion. A portion of the oxidized portion is removed, thereby forming an oxide spacer between a portion of the second carrier portion and the first carrier portion. A gate region is formed above at least a portion of the second carrier portion, and a first source/drain region and a second source/drain region are formed. | 10-02-2008 |
20080237694 | Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module - The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer. | 10-02-2008 |
20080259687 | Integrated Circuits and Methods of Manufacturing Thereof - Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure. | 10-23-2008 |
20080308856 | Integrated Circuit Having a Fin Structure - Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure. | 12-18-2008 |
20090072274 | INTEGRATED CIRCUIT INCLUDING A FIRST GATE STACK AND A SECOND GATE STACK AND A METHOD OF MANUFACTURING - An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack. | 03-19-2009 |
20090309152 | Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate. | 12-17-2009 |
Patent application number | Description | Published |
20120091730 | Energy Supply System and Operating Method - An energy supply system is provided with an electricity generating device for regeneratively generating electrical energy that can be fed into an electricity supply grid. The energy supply system includes an electricity generating device for regeneratively generating electrical energy which can be fed into an electricity supply grid, a hydrogen generating device for generating hydrogen using electrical energy from the regenerative electricity generating device, a methanation device for converting hydrogen generated by the hydrogen generating device and a supplied carbon oxide gas into a gas containing methane, and a gas providing device for providing a supplementary gas or a replacement gas in a variably specifiable supplementary/replacement gas quality suitable for feeding into a gas supply grid with the use of the gas containing methane from the methanation device and/or the hydrogen from the hydrogen generating device. A method of operating the system is also provided. | 04-19-2012 |
20130041051 | METHOD FOR PRODUCING A METHANE-RICH PRODUCT GAS AND REACTOR SYSTEM USABLE FOR THAT PURPOSE - The invention relates to a method for producing a methane-rich product gas, in which a starting gas containing hydrogen and carbon dioxide is catalytically methanated under the influence of at least one adjustatable parameter in at least two stages and at least one criterion relating to the composition of the product gas is monitored. The criterion is fulfilled under a condition influencing the method and when the condition changes, a change in the parameter setting that preserves fulfilment of the criterion is affected. | 02-14-2013 |
20130287652 | SHELL-AND-TUBE REACTOR FOR CARRYING OUT CATALYTIC GAS PHASE REACTIONS - A tube bundle reactor for carrying out catalytic gas phase reactions, particularly methanation reactions, has a bundle of catalyst-filled reaction tubes through which reaction gas flows and around which heat carrier flows during operation. In the region of the catalyst filling, the reaction tubes run through at least two heat carrier zones which are separated from one another, the first of which heat carrier zones extends over the starting region of the catalyst filling. The reaction tubes each have a first reaction tube portion with a first hydraulic diameter of the catalyst filling and, downstream thereof in flow direction of the reaction gas, at least a second reaction tube portion with a second hydraulic diameter of the catalyst filling that is greater than the first hydraulic diameter of the catalyst filling. | 10-31-2013 |