Patent application number | Description | Published |
20110197168 | DECOMPOSING INTEGRATED CIRCUIT LAYOUT - Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed. | 08-11-2011 |
20110245949 | METHOD AND APPARATUS OF PATTERNING SEMICONDUCTOR DEVICE - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 10-06-2011 |
20120072874 | DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION AND MASK RULE CHECK ENFORCEMENT - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC. | 03-22-2012 |
20120227018 | Method and Apparatus of Patterning Semiconductor Device - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 09-06-2012 |
20130246981 | DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION TO REDUCE CORNER ROUNDING - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout. | 09-19-2013 |
20130275925 | Pattern Correction With Location Effect - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a plurality of IC regions each including an IC pattern; performing a dissection process to the IC design layout; and performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect. The correction process includes performing a first correction step to a first IC region of the IC regions, resulting in a first corrected IC pattern in the first IC region; and performing a second correction step to a second IC region of the IC regions, starting with the first corrected IC pattern, resulting in a second corrected IC pattern. | 10-17-2013 |
20130275926 | NOVEL METHODOLOGY OF OPTICAL PROXIMITY CORRECTION OPTIMIZATION - A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database. | 10-17-2013 |
20140101623 | METHOD OF MERGING COLOR SETS OF LAYOUT - A method includes determining one or more potential merges corresponding to a color set A | 04-10-2014 |
20140248768 | Mask Assignment Optimization - A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines. | 09-04-2014 |
20150106773 | METHODOLOGY FOR PATTERN CORRECTION - The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time. | 04-16-2015 |
20150106779 | METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION - The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced. | 04-16-2015 |
20150143304 | Target Point Generation for Optical Proximity Correction - A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour. | 05-21-2015 |
Patent application number | Description | Published |
20090034882 | WEARABLE BAG WITH SECURITY DEFENSE - The present invention pertains to a wearable bag comprising a body divided by two panels, two shoulder straps respectively disposed on two panels, and a zipper with two zipper tracks and two zipper tabs. Particularly, the body has a plurality of pockets disposed therein, which are sewed to the front side thereof; further the panels are interlocked to form a bag with the shoulder straps by the zipper tabs sliding toward the same direction along the zipper tracks; relatively, the panels are detached to form a wearable vest while the zipper tabs slide toward a reverse direction. As a result, the present invention provides with multiple uses, used for a bag or a vest, and also facilitates to decrease the possibility of robbery for increasing the security defense. | 02-05-2009 |
20090034884 | CONVENIENT PORTABLE BAG - The present invention pertains to a portable bag comprising a bag body, a zipper, and a strap. Particularly, the strap includes a strap loop with a blocking portion engaging thereto. Further, the blocking portion is inserted into the bag body and fixed therein by a larger outer diameter of the blocking portion than a dimension of a detaching portion while interlocking the zipper, which results in the strap to be a held in the hand or in the shoulder. As a result, the present invention provides with multiple ways for the portability and the convenience in use while carrying out the blocking portion and the articles in the bag. | 02-05-2009 |
20090055989 | Garment with various utilities - The present invention pertains to a garment with various utilities comprising a body cover, a head cover, and a pair of sleeves; wherein, two body gown portions are respectively extended from two sides of the body cover, which separately have a gown seam disposed thereon; the head cover connects to the body cover, and the sleeves are respectively joined to two sides of the body cover. While dressing, two arms are respectively penetrating through the sleeves, and the body is enclosed by the cohesion of two gown seams resulting in the overlapping of two body gown portions. Consequently, people can exert the garment instead of towels in different purposes, such as for the household use, for SPA, etc., thus enhancing the personal sanitary concern, keeping warm, and decreasing large expense for cleaning towels and the destruction to the environment by the cleansers. | 03-05-2009 |
Patent application number | Description | Published |
20110095394 | ANTIFUSE AND METHOD OF MAKING THE ANTIFUSE - A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse. | 04-28-2011 |
20120106259 | Adaptive Control of Programming Currents for Memory Cells - A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation. | 05-03-2012 |
20120163086 | CONCURRENT OPERATION OF PLURAL FLASH MEMORIES - A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. | 06-28-2012 |
20130242676 | FAST-SWITCHING WORD LINE DRIVER - A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level. | 09-19-2013 |
20130286729 | Methods and Apparatus for Non-Volatile Memory Cells - Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed. | 10-31-2013 |
20140062580 | Diode Formed of PMOSFET and Schottky Diodes - A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET. | 03-06-2014 |
20140211549 | ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY - A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances. | 07-31-2014 |
20140253190 | Multiple Power Domain Electronic Device and Related Method - An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit. | 09-11-2014 |
20140269030 | METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING - A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. | 09-18-2014 |
20150054485 | Bandgap Reference and Related Method - A device includes a proportional-to-absolute-temperature (PTAT) current source having a bandgap reference voltage node, and a negative temperature dynamic load having an input terminal electrically connected to the bandgap reference voltage node. | 02-26-2015 |
20150070057 | Multiple Power Domain Electronic Device and Related Method - An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit. | 03-12-2015 |
20150187721 | PACKAGE WITH MULTIPLE PLANE I/O STRUCTURE - A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit. | 07-02-2015 |
Patent application number | Description | Published |
20080251832 | Logic compatible arrays and operations - An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array. | 10-16-2008 |
20110233654 | NANO-CRYSTAL GATE STRUCTURE FOR NON-VOLATILE MEMORY - A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is provided between the control gate and the substrate. The nano-crystals in the charge storage layer have a size of about 1 nm to about 10 nm, and may be formed of Silicon or Germanium. Writing operations are accomplished via hot electron injection, FN tunneling, or source-side injection. Erase operations are accomplished using FN tunneling. The control gate is formed of a single layer of polysilicon, which reduces the total number of processing steps required to form the device, thus reducing cost. | 09-29-2011 |
20120087188 | STRUCTURE AND INHIBITED OPERATION OF FLASH MEMORY WITH SPLIT GATE - A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities. | 04-12-2012 |
20130064017 | CONCURRENT OPERATION OF PLURAL FLASH MEMORIES - A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. | 03-14-2013 |
20130070519 | READ ARCHITECTURE FOR MRAM - A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison. | 03-21-2013 |
20130201754 | MRAM WITH CURRENT-BASED SELF-REFERENCED READ OPERATIONS - A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element. | 08-08-2013 |
20130265820 | ADJUSTING REFERENCE RESISTANCES IN DETERMINING MRAM RESISTANCE STATES - Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position. | 10-10-2013 |
20130271207 | REFERENCE GENERATION IN AN INTEGRATED CIRCUIT DEVICE - A method for generating a reference voltage in an integrated circuit device that is powered by a low voltage power includes generating a coarse first reference voltage using a coarse reference generator, routing the coarse first reference voltage to a boost regulator as an input reference voltage by a hand-off switch circuit, the boost regulator generating an initial-state stepped-up supply based on the first reference voltage, and generating at least two outputs of a second, more accurate, reference voltage from the stepped-up supply voltage using a fine-resolution reference generator. The second reference can be then looped back to the boost regulator, thus, generating a more accurate steady-state stepped-up supply voltage. | 10-17-2013 |
20130272059 | DIFFERENTIAL MRAM STRUCTURE WITH RELATIVELY REVERSED MAGNETIC TUNNEL JUNCTION ELEMENTS ENABLING WRITING USING SAME POLARITY CURRENT - A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array. | 10-17-2013 |
20130307080 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 11-21-2013 |
20130308367 | STRUCTURE AND METHOD FOR FORMING CONDUCTIVE PATH IN RESISTIVE RANDOM-ACCESS MEMORY DEVICE - An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array. | 11-21-2013 |
20140003141 | CONCURRENT OPERATION OF PLURAL FLASH MEMORIES | 01-02-2014 |
20140094009 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 04-03-2014 |
20140157088 | MRAM Smart Bit Write Algorithm with Error Correction Parity Bits - Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location. | 06-05-2014 |
20150063048 | Sample-and-Hold Current Sense Amplifier and Related Method - A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier. | 03-05-2015 |
20150221383 | MULTIPLE-TIME PROGRAMMABLE MEMORY - A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage. | 08-06-2015 |
20150234403 | LOW-DROPOUT REGULATOR - A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes. | 08-20-2015 |
20150294696 | STABILIZING CIRCUIT - A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V. | 10-15-2015 |
20150355963 | MRAM SMART BIT WRITE ALGORITHM WITH ERROR CORRECTION PARITY BITS - Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location. | 12-10-2015 |
Patent application number | Description | Published |
20100041194 | SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF - A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell. | 02-18-2010 |
20110199845 | REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF - A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays. | 08-18-2011 |
20120127806 | MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR - A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor. | 05-24-2012 |
20120134218 | CHARGE PUMP CONTROL SCHEME USING FREQUENCY MODULATION FOR MEMORY WORD LINE - A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage. | 05-31-2012 |
20120275249 | REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF - A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays. | 11-01-2012 |
20130093499 | POWER SWITCH AND OPERATION METHOD THEREOF - A power switch includes a control circuit, a cross-coupled amplifier, a first switching circuit coupled between a first output terminal and the first controlled ground terminal, and a second switching circuit coupled between a second output terminal and the second controlled ground terminal. The control circuit is configured to connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to a first voltage level and to set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level. | 04-18-2013 |
20130121088 | MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR - A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness. | 05-16-2013 |
20130127515 | VOLTAGE DIVIDING CIRCUIT - A voltage divider is disclosed that includes a plurality of components connected in series having respective input terminals, respective output terminals, and a reference voltage node at the connection between one of the input terminals and one of the output terminals. The voltage divider also includes a level shifter having a input terminal coupled to the reference voltage node and having a output terminal supplying an output reference voltage. | 05-23-2013 |
20140146613 | OPERATING METHOD OF MEMORY HAVING REDUNDANCY CIRCUITRY - In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page. | 05-29-2014 |
20140185401 | SENSING CIRCUIT, MEMORY DEVICE AND DATA DETECTING METHOD - A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage. | 07-03-2014 |
20140211537 | RESISTANCE-BASED RANDOM ACCESS MEMORY - A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node. | 07-31-2014 |
20140256099 | METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD - A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference. | 09-11-2014 |
20140340970 | MEMORY WITH DYNAMIC FEEDBACK CONTROL CIRCUIT - A memory comprising a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is configured to boost the word line voltage to a predetermined voltage value greater than a target threshold voltage, change a clock frequency of a clock signal supplied to the charge pump from a non-zero frequency to a zero frequency if the word line voltage is above the predetermined voltage value, and change the clock frequency from the zero frequency to the non-zero frequency if the word line voltage is below the target threshold voltage. | 11-20-2014 |
20150015223 | Low Dropout Regulator and Related Method - A device includes an error amplifier, a standby current source, a charging current source, a voltage divider, and a first switch. The error amplifier has a negative input terminal and a positive input terminal. The standby current source has a control terminal electrically connected to an output terminal of the error amplifier. The voltage divider has an input terminal electrically connected to an output terminal of the standby current source, and an output terminal electrically connected to the positive input terminal of the error amplifier. The charging current source has a control terminal electrically connected to the output terminal of the error amplifier. The first switch has a first terminal electrically connected to an input terminal of the charging current source, and a second terminal electrically connected to a first power supply node. | 01-15-2015 |
20150095868 | METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD - A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference. | 04-02-2015 |
20150109850 | MEMORY DEVICES - A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells. | 04-23-2015 |
20150117131 | MEMORY DEVICES - A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed. | 04-30-2015 |
20150131361 | MEMORY DEVICE - A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells. | 05-14-2015 |
20150131372 | MEMORY CONTROLLER, MEMORY DEVICE AND METHOD OF OPERATING - A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell. | 05-14-2015 |
20150144860 | RESISTIVE MEMORY ARRAY AND FABRICATING METHOD THEREOF - The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure. | 05-28-2015 |
20150180210 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques. | 06-25-2015 |
20150206583 | Operating Resistive Memory Cell - A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source. | 07-23-2015 |
20150269997 | Resistive Memory Array - A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line. | 09-24-2015 |
Patent application number | Description | Published |
20100206070 | SPEED METER HAVING PEDOMETRIC FUNCTION - A speed meter having pedometric function comprises a casing provided with a liquid crystal screen, a gravity sensor provided in electric connection in the casing, a circuit board, and a microprocessor. A changeover switch is respectively connected with the gravity sensor and the microprocessor. Thereby, the forward speed of a vehicle can be obtained by the detection of the gravity sensor and the calculation of the microprocessor when the vehicle is driven. After the changeover switch is switched into a status of walking or running, the step count of a user can be obtained by the detection of the gravity sensor and the calculation of the microprocessor and shown on the liquid crystal screen. | 08-19-2010 |
20100207802 | G-SENSOR REMOTE CONTROLLER - A G-sensor (gravity sensor) remote controller is characterized in that at least a G-sensor and a microprocessor are provided within the main body of the remote controller. Each G-sensor provided in the main body of the remote controller is used for sensing the tapping action of a user to produce sensing signals and different sensing signals can be produced according to the area on the main body the user taps or the tapping frequency within a period of time. The microprocessor provided in the main body of the remote controller is electrically connected with the G-sensor and for processing the sensing signals from the G-sensor to control the function setting of the remote controller itself or other electric apparatuses. | 08-19-2010 |
20100208421 | BIKE COMPUTER HAVING DUAL POWER SOURCE - A bike computer having dual power source comprises a housing, a first power module, a switch module and a second power module. The housing has a control module, a liquid display module and a light source module. The control module is electrically connected to the liquid display module, and the light source module provides lights to the liquid display module. A first power module is electrically connected to the control module to supply power to the control module; the switch module is electrically connected to the control module, the first power module, and the light source module. A second power module is electrically connected to the switch module, where is controllable by the control module to switch power outputting for the light source module from the first power module to the second power module. | 08-19-2010 |
20100211350 | SPEED METER - A speed meter connected to a vehicle comprises a casing provided with a liquid crystal screen, and a gravity sensor, a power source, a circuit board, and a microprocessor are provided in the casing. The microprocessor is located on the circuit board. The power source, the circuit board, the liquid crystal screen, and the gravity sensor are respectively electrically connected with each other and the gravity sensor is connected with the microprocessor. Thereby, when the vehicle is driven forward, the forward speed of the vehicle can be obtained via the calculation of the microprocessor after the gravity sensor detects the forward acceleration. The obtained forward speed can be shown on the liquid crystal screen to inform users immediately. | 08-19-2010 |