Yang, Kaohsiung County
Chih-Wei Yang, Kaohsiung County TW
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20090250754 | PARTIALLY DEPLETED SILICON-ON-INSULATOR METAL OXIDE SEMICONDUCTOR DEVICE - A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and the silicon-on-insulator substrate. | 10-08-2009 |
Chin-Cheng Yang, Kaohsiung County TW
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20090176069 | Mask for Controlling Line End Shortening and Corner Rounding Arising from Proximity Effects - A mask for producing an image feature on an image surface during a semiconductor fabrication process is provided, the mask comprising a main feature having opaque areas and transmissive areas arranged in the form of the image feature, wherein each end of the main feature includes at least one of an opaque edge and a transmissive edge, wherein the opaque edge includes a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge includes a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature. | 07-09-2009 |
20130138238 | WAFER CENTERING HARDWARE DESIGN AND PROCESS - An apparatus, system, or method for positioning a wafer on a support of a rotatable chuck may improve the accuracy and precision of various wafer edge cuts and wafer profiling at a variety of stages of wafer manufacturing. The apparatus, system, or and/or method may employ one or more of a wafer position calculator to calculate a desired wafer position and to provide desired wafer position information to a wafer arm controller; and a wafer arm controller in communication with the wafer position calculator to provide instructions to adjust a wafer arm to position the wafer on the support according to the desired wafer position. Various sensor detectors and sensor lights or other mechanisms for sensing the position of a wafer may also be used. | 05-30-2013 |
Chin-Tien Yang, Kaohsiung County TW
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20080251827 | Checkerboard deep trench dynamic random access memory cell array layout - A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas. | 10-16-2008 |
20080299734 | Method of manufacturing a self-aligned fin field effect transistor (FinFET) device - A method of manufacturing a self-aligned fin FET (FinFET) device is disclosed, in which, an insulating layer of a shallow trench isolation is etched back to partially expose sidewalls of the semiconductor substrate surrounded by the shallow trench isolation, and the sidewalls of the semiconductor substrate are then isotropically etched, allowing the semiconductor substrate to form into a relatively thin fin structure for forming a three-dimensional gate structure having three faces. | 12-04-2008 |
Fu-Chih Yang, Kaohsiung County TW
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20130112986 | Gallium Nitride Semiconductor Devices and Method Making Thereof - The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device. | 05-09-2013 |
20140110782 | Source Tip Optimization For High Voltage Transistor Devices - The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region. | 04-24-2014 |
Ming-Liau Yang, Kaohsiung County TW
Ping-Feng Yang, Kaohsiung County TW
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20120119342 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound. | 05-17-2012 |
Sheng-An Yang, Kaohsiung County TW
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20120124272 | FLASH MEMORY APPARATUS - A flash memory apparatus including a command analysis unit, a first flash memory and a second flash memory is provided. The command analysis unit with a plurality of command buffers receives a plurality of command elements and queues the command elements in the command buffers in sequence. The command analysis unit transmits the command elements simultaneously to the first flash memory and the second flash memory through a command bus, and the flash memory device writes/reads the first flash memory and the second flash memory simultaneously through a first data bus and a second data bus different from the first data bus respectively to execute an operation. The flash memory device queues the command elements so as to enhance the command throughput, and the flash memories share the same command bus for dual channel operation. | 05-17-2012 |
Shun Kuei Yang, Kaohsiung County TW
Syuan-Ling Yang, Kaohsiung County TW
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20110141548 | ELECTRO-WETTING DISPLAY PANEL - An electro-wetting display panel including an active device array substrate, a dielectric layer, a wall structure, a first liquid containing dyes, a second liquid, and an opposite substrate is provided. The active device array substrate includes a substrate, scan lines, data lines, and pixels. The pixels are electrically connected with the scan lines and the data lines accordingly. Each pixel includes an active device, a transparent pixel electrode, and a reflective layer. The transparent pixel electrode located above the reflective layer is electrically connected with the active device. The reflective layer has a bumpy surface. The dielectric layer is disposed on the active device array substrate. The wall structure is disposed on the dielectric layer. The first liquid is disposed on the dielectric layer. The opposite substrate is disposed above the active device array substrate. The second liquid is disposed between the active device array substrate and the opposite substrate. | 06-16-2011 |
20120161171 | PIXEL STRUCTURE - A pixel structure including a pair of first sub-pixels, a pair of second sub-pixels and an electrical tunable photonic crystal layer is provided. The pair of first sub-pixels are substantially identical in area, and the pair of second sub-pixels are substantially identical in area. The area of each second sub-pixel is twice the area of each first sub-pixel. In addition, the electrical tunable photonic crystal layer is disposed over the pair of first sub-pixels and the pair of second sub-pixels. | 06-28-2012 |
20120281269 | ELECTRO-WETTING DISPLAY DEVICE AND DRIVING METHOD THEREOF - An electro-wetting display device includes a light guide plate having a light incident surface and a light output surface, a light source, a transparent electrode, a dielectric layer, a transparent non-polar solution layer, a counter substrate, a light emitting material layer, a counter electrode layer and a transparent polar solution layer. The light source is disposed near the light incident surface. The transparent electrode layer is disposed on the light output surface. The dielectric layer covers the transparent electrode layer and has refractive index n1. The transparent non-polar solution layer is disposed on the dielectric layer and has refractive index n2, and n2≧n1. The counter substrate is disposed above the transparent non-polar solution layer. The light emitting material layer and the counter electrode are disposed on the counter substrate. The transparent polar solution layer is disposed between the counter substrate and the light guide plate. | 11-08-2012 |
Tai-Chang Yang, Kaohsiung County TW
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20100074479 | HIERARCHICAL FACE RECOGNITION TRAINING METHOD AND HIERARCHICAL FACE RECOGNITION METHOD THEREOF - A hierarchical face recognition training method and a hierarchical face recognition method thereof for performing a face feature recognition on an image under detection. The method includes a training process and a recognition process. The recognition method includes the steps. A plurality of training samples is obtained. The training samples are subdivided into a plurality of sub-image categories according to a plurality of angle intervals, and the training of a plurality of face features performs on a corresponding sub-image detector of each of the sub-image categories. The training measures performed repeatedly to generate sub-image categories at a sub-level of the sub-image categories. The training method includes the steps. An image under detection is loaded. A similarity of each of sub-image detectors compares according to the image under detection, and the sub-image detector having the highest similarity is selected. The face recognition measures performed repeatedly on the selected sub-image detector. | 03-25-2010 |
20110129127 | OBJECT IMAGE CORRECTION APPARATUS AND METHOD FOR OBJECT IDENTIFICATION - An object image correction apparatus and method for object identification are disclosed. The object image correction method is firstly used for correcting a face or an object under a right position. For example, in order to reduce time consumption for facial identification, the method corrects the deviations such as a rotation, direction, and scaling before an identification process. Preferably, an image is retrieved in a first step. One or more object positions are then detected. Next, some positions of the features are found, and the positions of plural feature points thereon are computed. The method then goes to determine the degree of deviations for the object based on the positions of feature points. Moreover, one or in combination of a rotation correction, a scaling correction, a direction correction, and a shift correction is introduced to process the correction on each deviation. The positions of the feature points are consequently obtained. | 06-02-2011 |
Yi-Chih Yang, Kaohsiung County TW
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20100178782 | CONNECTION BASE ASSEMBLY FOR AN IC TESTING APPARATUS - A connection base assembly for an IC testing apparatus has a base, a top cap and a conductive assembly. The base has a bottom board and an outer frame provided with multiple grooves. The grooves are defined in the top of and extend to the bottom of the outer frame to form multiple through holes in the bottom of the outer frame. The conductive assembly is mounted between the base and the top cap and has multiple conductive elements, multiple top resilient elements and multiple bottom resilient elements. The conductive elements are mounted respectively in the grooves in the outer frame of the base, and each conductive element has a contacting segment and a connecting segment. The top resilient elements and the bottom resilient elements are respectively mounted on and abut with the tops and the bottoms of the resilient elements. | 07-15-2010 |
Ying-Hui Yang, Kaohsiung County TW
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20110128979 | LASER SCANNING DEVICE AND METHOD USING THE SAME - A laser scanning device and a method using the same are provided. The laser scanning device includes a laser output unit, a shape rotation unit, a scanning unit and a control unit. The laser output unit is used to output a laser beam. The shape rotation unit is disposed on a propagation path of the laser beam for rotating a spot of the laser beam by a predetermined angle. The scanning unit receives the laser beam whose spot has been rotated by the predetermined angle to scan a work piece set on a carrier unit. The control unit is set between the shape rotation unit and the scanning unit for generating the predetermined angle based on a scanning position of the scanning unit. | 06-02-2011 |
20120125901 | APPARATUS AND SYSTEM FOR IMPROVING DEPTH OF FOCUS - The present invention provides an apparatus and a system for improving depth of focus (DOF), wherein an optical lens for optical processing is actuated to vibrate whereby the DOF of the optical processing is increased due to the variation of focal point. In the embodiment of the present invention, an actuator is coupled to the optical lens for providing vibration energy wherein the optical lens is actuated by the vibration energy so as to vibrate on an optical axis thereof so as to increase the DOF during the optical processing, thereby improving the quality and efficiency of optical processing. | 05-24-2012 |