Patent application number | Description | Published |
20110084391 | Reducing Device Mismatch by Adjusting Titanium Formation - An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 Å; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer. | 04-14-2011 |
20130068023 | Motion Sensor Device and Methods for Forming the Same - A Micro-Electro-Mechanical System (MEMS) device includes a sensing element, and a proof mass over and overlapping at least a portion of the sensing element. The proof mass is configured to be movable toward the sensing element. A protection region is formed between the sensing element and the proof mass. The protection region overlaps a first portion of the sensing element, and does not overlap a second portion of the sensing element, wherein the first and the second portions overlap the proof mass. | 03-21-2013 |
20140252499 | Metal-Oxide-Semiconductor Field-Effect Transistor with Extended Gate Dielectric Layer - A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain. | 09-11-2014 |
20150177273 | Motion Sensor Device and Methods for Forming the Same - A Micro-Electro-Mechanical System (MEMS) device includes a sensing element, and a proof mass over and overlapping at least a portion of the sensing element. The proof mass is configured to be movable toward the sensing element. A protection region is formed between the sensing element and the proof mass. The protection region overlaps a first portion of the sensing element, and does not overlap a second portion of the sensing element, wherein the first and the second portions overlap the proof mass. | 06-25-2015 |
20160079368 | Metal-Oxide-Semiconductor Field-Effect Transistor with Extended Gate Dielectric Layer - A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain. | 03-17-2016 |
Patent application number | Description | Published |
20100140687 | High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates - An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region. | 06-10-2010 |
20110163375 | High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates - An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region. | 07-07-2011 |
20140021539 | Power Transistor with High Voltage Counter Implant - Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain. | 01-23-2014 |
20140145261 | High Voltage Drain-Extended MOSFET Having Extra Drain-OD Addition - An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions. | 05-29-2014 |
20140273376 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks. | 09-18-2014 |
20150249144 | High Voltage Drain-Extended MOSFET Having Extra Drain-OD Addition - An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate. | 09-03-2015 |
Patent application number | Description | Published |
20130134512 | Power MOSFETs and Methods for Forming the Same - A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate | 05-30-2013 |
20140197489 | Power MOSFETs and Methods for Forming the Same - Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. | 07-17-2014 |
20150162442 | Power MOSFETs and Methods for Forming the Same - Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. | 06-11-2015 |
Patent application number | Description | Published |
20100065944 | SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR DESIGN - An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors. | 03-18-2010 |
20140042590 | Metal-Insulator-Metal Capacitor and Method of Fabricating - Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors. | 02-13-2014 |
20150294936 | MIM CAPACITOR STRUCTURE - The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication. | 10-15-2015 |
20150295019 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor. | 10-15-2015 |
20150295020 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer. | 10-15-2015 |
20160071920 | Metal-Insulator-Metal Capacitor with Current Leakage Protection - A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges. | 03-10-2016 |
Patent application number | Description | Published |
20100237348 | Thin Film Transistor Array Substrate - A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode. | 09-23-2010 |
20100245222 | ACTIVE ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR DRIVING THE SAME - An active array substrate, a liquid crystal display panel and method for driving the same are provided. The active array substrate includes a plurality of first strip electrodes and second strip electrodes. The sum of one width of the first stripe electrode and one pitch between two adjacent first stripe electrodes is greater than that of one width of the second strip electrode and one pitch between two adjacent second strip electrodes. | 09-30-2010 |
20120181541 | Thin Film Transistor Array Substrate - A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode. | 07-19-2012 |
20120181542 | Thin Film Transistor Array Substrate - A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode. | 07-19-2012 |
Patent application number | Description | Published |
20130300973 | DISPLAY MODULE - A display module, which includes a display panel, a backlight unit and a bezel. The backlight unit is disposed opposite to the display panel. The bezel includes a bottom, a plurality of sidewalls and a plurality of extension structures. The bottom is configured to support the backlight unit. These sidewalls are configured to corporately enclose the display panel and the backlight unit, and each sidewall has a first end and a second end opposite to each other; wherein the first end is connected to the bottom. The extension structures each extend from the second end of the respective sidewall and include a supporting portion, disposed between the backlight unit and the display panel and opposite to the bottom, configured to support the display panel. | 11-14-2013 |
20140098514 | Display, Backlight Module, and Frame Structure Thereof - A backlight module includes a light-guiding plate, a back-light source disposed at a side of the light-guiding plate, and a frame structure disposed surrounding the light-guiding plate. The frame structure includes a border component, at least one first convex, and at least one second convex. The border component includes at least one first border and at least one second border. The first border and the second border are adjacent to each other and distributed along a first direction and a second direction respectively. The first convex protrudes from the inner surface of the first border and extends inward along the second direction. The second convex protrudes from the inner surface of the second border and extends inward along the first direction. The first direction is vertical to the second direction, and the top of the vertical height of the first convex is lower than that of the second convex. | 04-10-2014 |
Patent application number | Description | Published |
20130140533 | PIXEL STRUCTURE OF ELECTROLUMINESCENT DISPLAY PANEL - A pixel structure of electroluminescent display panel has a first sub-pixel region, a second sub-pixel region and a third sub-pixel region. The pixel structure of electroluminescent display panel includes a first organic light-emitting layer and a second organic light-emitting layer. The first organic light-emitting layer, which includes a first organic light-emitting material, is disposed at least in the first sub-pixel region and the second sub-pixel region. The second organic light-emitting layer, which includes a second organic light-emitting material and a third organic light-emitting material, is disposed at least in the second sub-pixel region and the third sub-pixel region. The first organic light-emitting layer and the second organic light-emitting layer overlap in the second sub-pixel region. The first sub-pixel region and the third sub-pixel region have different cavity lengths. | 06-06-2013 |
20130140535 | PIXEL STRUCTURE OF AN ELECTROLUMINESCENT DISPLAY PANEL - A pixel structure of an electroluminescent display panel includes a first sub-pixel region, a second sub-pixel region, a third sub-pixel region and a fourth sub-pixel region having different cavity lengths. The first sub-pixel region and the second sub-pixel region share a first organic light-emitting layer, which can generate a first primary color light in the first sub-pixel region, and a second primary color light in the second sub-pixel region. The third sub-pixel region and the fourth sub-pixel region share a second organic light-emitting layer, which can generate a third primary color light in the third sub-pixel region, and a fourth primary color light in the fourth sub-pixel region. The first primary color light, the second primary color light, the third primary color light and the fourth primary color light have different spectra of wavelength. | 06-06-2013 |
Patent application number | Description | Published |
20140035082 | Elevated Photodiodes with Crosstalk Isolation - A device includes a plurality of isolation spacers, and a plurality of bottom electrodes, wherein adjacent ones of the plurality of bottom electrodes are insulated from each other by respective ones of the plurality of isolation spacers. A plurality of photoelectrical conversion regions overlaps the plurality of bottom electrodes, wherein adjacent ones of the plurality of photoelectrical conversion regions are insulated from each other by respective ones of the plurality of isolation spacers. A top electrode overlies the plurality of photoelectrical conversion regions and the plurality of isolation spacers. | 02-06-2014 |
20140035083 | Elevated Photodiode with a Stacked Scheme - A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode. | 02-06-2014 |
20150064832 | Elevated Photodiode with a Stacked Scheme - A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode. | 03-05-2015 |
20150118787 | Elevated Photodiodes with Crosstalk Isolation - A device includes a plurality of isolation spacers, and a plurality of bottom electrodes, wherein adjacent ones of the plurality of bottom electrodes are insulated from each other by respective ones of the plurality of isolation spacers. A plurality of photoelectrical conversion regions overlaps the plurality of bottom electrodes, wherein adjacent ones of the plurality of photoelectrical conversion regions are insulated from each other by respective ones of the plurality of isolation spacers. A top electrode overlies the plurality of photoelectrical conversion regions and the plurality of isolation spacers. | 04-30-2015 |
20150372042 | Elevated Photodiode with a Stacked Scheme - A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode. | 12-24-2015 |
Patent application number | Description | Published |
20150185576 | Active Device Substrate and Display Panel Using The Same - An active device substrate includes scan lines, data lines, a first pixel electrode, a second pixel electrode, a first transistor, and a second transistor. The (M−1)th scan line, the (M)th scan line, the (N−1)th data line, and the (N)th data line define a first sub-pixel area. The (L)th scan line, the (L+1)th scan line, the (N)th data line, and the (N+1)th data line define a second sub-pixel area. The first pixel electrode, the first transistor, and the second transistor are disposed in the first sub-pixel area, and at least one portion of the second pixel electrode is disposed in the second sub-pixel area. The first transistor is electrically connected to one of the scan lines, one of the data lines, and the first pixel electrode. The second transistor is electrically connected to one of the scan lines, one of the data lines, and the second pixel electrode. | 07-02-2015 |