Patent application number | Description | Published |
20100293401 | Power Managed Lock Optimization - In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free. | 11-18-2010 |
20110252251 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 10-13-2011 |
20120144172 | Interrupt Distribution Scheme - In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor. | 06-07-2012 |
20120167107 | Power Managed Lock Optimization - In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free. | 06-28-2012 |
20120185703 | Coordinating Performance Parameters in Multiple Circuits - Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles. | 07-19-2012 |
20120260081 | Adjusting Device Performance Based on Processing Profiles - Adjusting processor performance based on processing profiles. The method may determine that a process has entered a processing state after an idle state. In response to entering the processing state the processing time of the processor may be monitored. In response to the processing time exceeding a first threshold of time, the performance of the processor may be increased from a first level to a second level. In response to the processing time exceeding a second threshold time, the performance of the processor may be decreased from the second level to a third level. | 10-11-2012 |
20120317427 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 12-13-2012 |
20130043917 | HARDWARE CONTROLLED PLL SWITCHING - A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL. | 02-21-2013 |
20130055004 | HARDWARE-BASED AUTOMATIC CLOCK GATING - A system and method for automatically updating with hardware clock tree settings on a system-on-a-chip (SOC). A SOC includes a hardware clock control unit (HCCU) coupled to a software interface and a clock tree. The SOC also includes multiple integrated circuit (IC) devices, wherein each IC device receives one or more associated core clocks provided by one or more phase lock loops (PLLs) via the clock tree. The HCCU receives a software-initiated request specifying a given IC device is to be enabled. The HCCU identifies one or more core clocks used by the given IC device. For each one of the identified core clocks, the HCCU configures associated circuitry within the clock tree to generate an identified core clock. The HCCU may also traverse the clock tree and disable clock generating gates found not to drive any other enabled gates or IC devices. | 02-28-2013 |
20130067257 | Power Managed Lock Optimization - In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free. | 03-14-2013 |
20130232364 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 09-05-2013 |
20140089546 | INTERRUPT TIMESTAMPING - A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor. | 03-27-2014 |
20140089712 | Security Enclave Processor Power Control - An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory. | 03-27-2014 |
20140122908 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 05-01-2014 |
20140208135 | POWER-UP RESTRICTION - Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit. | 07-24-2014 |
20140215182 | Persistent Relocatable Reset Vector for Processor - In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time. | 07-31-2014 |
Patent application number | Description | Published |
20080307245 | Methods and systems to dynamically manage performance states in a data processing system - Methods and apparatuses to dynamically manage a performance state of a data processing system are described. The data processing system includes a plurality of components; one or more buses coupled to the plurality of components, and a dynamic performance state manager unit coupled to the components. The dynamic performance state manager unit is configured to receive information about a first plurality of current states of components of the system. The dynamic performance state manager unit is configured to determine a second plurality of required system performance states for the components; and to determine a current system performance state based on the first plurality and the second plurality. | 12-11-2008 |
20090063108 | Compatible trust in a computing device - A method and apparatus for executing a first executable code image having a first version number into a memory of a device in an attempt to establish an operating environment of the device are described. The first executable code image retrieves a second version number from the second executable code image after successfully authenticating the second executable code image. If the first version number and the second version number do not satisfy a predetermined relationship, the second executable code image is prevented from being loaded by the first executable code image. | 03-05-2009 |
20090063715 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 03-05-2009 |
20090257595 | Single Security Model In Booting A Computing Device - A method and apparatus for securely booting software components in an electronic device to establish an operating environment are described herein. According to an aspect of the invention, software components are to be executed in sequence in order to establish an operating environment of a device. For each software component, a security code is executed to authenticate and verify an executable code image associated with each software component using one or more keys embedded within a secure ROM (read-only memory) of the device and one or more hardware configuration settings of the device. The security code for each software component includes a common functionality to authenticate and verify the executable code image associated with each software component. In response to successfully authenticating and verifying the executable code image, the executable code image is then executed in a main memory of the device to launch the associated software component. | 10-15-2009 |
20090259855 | Code Image Personalization For A Computing Device - A method and apparatus for personalizing a software component to be executed in particular environment are described herein. According to an aspect of the invention, in response to an executable code image representing a software component to be installed in an electronic device, the executable code image is encrypted using an encryption key. The encryption key is then wrapped with a UID that uniquely identifies the electronic device, where the UID is embedded within a secure ROM of the electronic device. The wrapped encryption key and the encrypted executable code image are then encapsulated into a data object to be stored in a storage of the electronic device, such that when the electronic device is subsequently initialized for operation, the executable code image can only be recovered using the UID of the electronic device to retrieve a decryption key in order to decrypt the executable code image. | 10-15-2009 |
20090295461 | DEVICE CONFIGURATION - A process and apparatus for configuring one or more integrated circuits within a device in a manufacturing process is described. In an exemplary process, a device is manufactured by assembling a chip onto a board such as a printed circuit substrate and the chip is fused from power routed across the board to the chip. The power source for the fusing can be generated from the internal power supply on the board or received on a test point on the board itself or a connection interface (e.g. a USB interface) coupled to the board. In an exemplary apparatus, a device comprises a chip with a plurality of fuses that are used to configure the device and a board coupled to the chip, with the board capable of routing power from the board to the chip and the power is used to blow one or more of the plurality of fuses. | 12-03-2009 |
20100211700 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 08-19-2010 |
20110219252 | Methods and Systems for Power Management in a Data Processing System - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 09-08-2011 |
20110258640 | METHOD AND APPARATUS FOR INTERCOMMUNICATIONS AMONGST DEVICE DRIVERS - Techniques for intercommunication amongst device drivers are described herein. In one embodiment, an application programming interface (API) is provided by a kernel of an operating system (OS) running within a data processing system. The API is accessible by device drivers associated with multiple devices installed in the system. In response to a request from a first instance of a driver the API, information indicating whether another instance of the same driver is currently started is returned via the API. Other methods and apparatuses are also described. | 10-20-2011 |
20110283023 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 11-17-2011 |
20110314305 | Dynamic Voltage Dithering - A request for a high voltage mode is received and a high voltage timer is started in response to determining that a remaining amount of high voltage credits exceeds a voltage switch threshold value. A switch to the high voltage mode is made in response to the request. A low voltage mode is switched to in response to an indication. The request may be received from an application running on a data processing system. If the indication is that the high voltage timer has expired, a low voltage timer is started in response to switching to low voltage mode. If the high voltage request is still active when the low voltage timer expires, a switch back to high voltage mode occurs and a new high voltage timer is started. | 12-22-2011 |
20120166781 | SINGLE SECURITY MODEL IN BOOTING A COMPUTING DEVICE - A method and apparatus for securely booting software components in an electronic device to establish an operating environment are described herein. According to an aspect of the invention, software components are to be executed in sequence in order to establish an operating environment of a device. For each software component, a security code is executed to authenticate and verify an executable code image associated with each software component using one or more keys embedded within a secure ROM (read-only memory) of the device and one or more hardware configuration settings of the device. The security code for each software component includes a common functionality to authenticate and verify the executable code image associated with each software component. In response to successfully authenticating and verifying the executable code image, the executable code image is then executed in a main memory of the device to launch the associated software component. | 06-28-2012 |
20120185712 | METHODS AND SYSTEMS FOR POWER MANAGEMENT IN A DATA PROCESSING SYSTEM - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 07-19-2012 |
20120278597 | COMPATIBLE TRUST IN A COMPUTING DEVICE - A method and apparatus for executing a first executable code image having a first version number into a memory of a device in an attempt to establish an operating environment of the device are described. The first executable code image retrieves a second version number from the second executable code image after successfully authenticating the second executable code image. If the first version number and the second version number do not satisfy a predetermined relationship, the second executable code image is prevented from being loaded by the first executable code image. | 11-01-2012 |
20130024677 | SECURE BOOTING A COMPUTING DEVICE - A method and an apparatus for executing codes embedded inside a device to verify a code image loaded in a memory of the device are described. A code image may be executed after being verified as a trusted code image. The embedded codes may be stored in a secure ROM (read only memory) chip of the device. In one embodiment, the verification of the code image is based on a key stored within the secure ROM chip. The key may be unique to each device. Access to the key may be controlled by the associated secure ROM chip. The device may complete establishing an operating environment subsequent to executing the verified code image. | 01-24-2013 |
20130036298 | SECURELY RECOVERING A COMPUTING DEVICE - A method and an apparatus for establishing an operating environment by certifying a code image received from a host over a communication link are described. The code image may be digitally signed through a central authority server. Certification of the code image may be determined by a fingerprint embedded within a secure storage area such as a ROM (read only memory) of the portable device based on a public key certification process. A certified code image may be assigned a hash signature to be stored in a storage of the portable device. An operating environment of the portable device may be established after executing the certified code. | 02-07-2013 |
20130081124 | TRUSTING AN UNVERIFIED CODE IMAGE IN A COMPUTING DEVICE - A method and an apparatus for configuring a key stored within a secure storage area (e.g., ROM) of a device including one of enabling and disabling the key according to a predetermined condition to execute a code image are described. The key may uniquely identify the device. The code image may be loaded from a provider satisfying a predetermined condition to set up at least one component of an operating environment of the device. Verification of the code image may be optional according to the configuration of the key. Secure execution of an unverified code image may be based on a configuration that disables the key. | 03-28-2013 |
20130283076 | METHODS AND SYSTEMS FOR POWER MANAGEMENT IN A DATA PROCESSING SYSTEM - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 10-24-2013 |
20130326239 | POWER MANAGEMENT WITH THERMAL CREDITS - A power management system, in one embodiment, determines a thermal status (e.g. a temperature or a calculation of power consumption) of at least a portion of a data processing system, and based on that status, thermal credits are calculated and then used to determine a voltage dithering pattern and a voltage boost pattern. | 12-05-2013 |
20140129852 | Dynamic Voltage Dithering - A request for a high voltage mode is received and a high voltage timer is started in response to determining that a remaining amount of high voltage credits exceeds a voltage switch threshold value. A switch to the high voltage mode is made in response to the request. A low voltage mode is switched to in response to an indication. The request may be received from an application running on a data processing system. If the indication is that the high voltage timer has expired, a low voltage timer is started in response to switching to low voltage mode. If the high voltage request is still active when the low voltage timer expires, a switch back to high voltage mode occurs and a new high voltage timer is started. | 05-08-2014 |
20150033030 | SECURELY RECOVERING A COMPUTING DEVICE - A method and an apparatus for establishing an operating environment by certifying a code image received from a host over a communication link are described. The code image may be digitally signed through a central authority server. Certification of the code image may be determined by a fingerprint embedded within a secure storage area such as a read only memory (ROM) of the portable device based on a public key certification process. A certified code image may be assigned a hash signature to be stored in a storage of the portable device. An operating environment of the portable device may be established after executing the certified code. | 01-29-2015 |
Patent application number | Description | Published |
20090248910 | CENTRAL DMA WITH ARBITRARY PROCESSING FUNCTIONS - A method and system is disclosed for transforming of data by a DMA controller without first saving the transmitted data on an intermediate medium. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is transformed into a modified state. This transformation may include encryption or decryption of the data. The transformation may also include adding error correction bits to the data through an encoding process or decoding previously encoded data. Upon completion of the transformation, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device. Also disclosed is a DMA controller capable of performing the data transformation. | 10-01-2009 |
20140082242 | REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK - A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period. | 03-20-2014 |
20140082383 | PREDICTING USER INTENT AND FUTURE INTERACTION FROM APPLICATION ACTIVITIES - Techniques for power management of a portable device are described herein. According to one embodiment, a user agent of an operating system executed within a portable device is configured to monitor activities of programs running within the portable device and to predict user intent at a given point in time and possible subsequent user interaction with the portable device based on the activities of the program. Power management logic is configured to adjust power consumption of the portable device based on the predicted user intent and subsequent user interaction of the portable device, such that remaining power capacity of a battery of the portable device satisfies intended usage of the portable device. | 03-20-2014 |
20140082384 | INFERRING USER INTENT FROM BATTERY USAGE LEVEL AND CHARGING TRENDS - Techniques for power management of a portable device are described herein. According to one embodiment, a user agent of an operating system executed within a portable device is configured to monitor daily battery usage of a battery of the portable device, to capturing, by the user agent, daily battery charging pattern of the battery of the portable device, and to inferring, by the user agent, user intent of utilizing the portable device at a given point in time based on a battery operating condition at the point in time in view of the daily battery usage and the daily battery charging pattern. Power management logic is configured to perform power management actions based on the user intent. | 03-20-2014 |
20140164661 | Methods and Systems for Time Keeping in a Data Processing System - Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period. | 06-12-2014 |