Huang, Hsin-Chu
Alex Huang, Hsin Chu TW
Patent application number | Description | Published |
---|---|---|
20130319738 | MULTILAYER ELECTRONIC STRUCTURE WITH THROUGH THICKNESS COAXIAL STRUCTURES - A multilayer electronic structure comprising a plurality of dielectric layers extending in an X-Y plane and comprising at least one coaxial pair of stacked posts extending through at least one dielectric layer in a Z direction that is substantially perpendicular to the X-Y plane, wherein the coaxial pair of stacked via posts comprises a central post surrounded by a torroidal via post separated from the central post by a separating tube of dielectric material. | 12-05-2013 |
20130333924 | MULTILAYER ELECTRONIC SUPPORT STRUCTURE WITH INTEGRAL METAL CORE - A laminated multilayer electronic support structure comprising a dielectric with integral vias and feature layers and further comprising a planar metal core characterized by a thickness of less than 100 microns. | 12-19-2013 |
20130333934 | MULTILAYER ELECTRONIC STRUCTURE WITH STEPPED HOLES - A multilayer electronic structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein at least one multilayered hole crosses at least two layers of the plurality of layers and comprises at least two hole layers in adjacent layers of the multilayer composite electronic structure, wherein the at least two holes in adjacent layers have different dimensions in the X-Y plane, such that a perimeter of the multilayered hole is stepped and where at least one hole is an aperture to a surface of the multilayer electronic structure. | 12-19-2013 |
Bob Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100006398 | SEGREGATING APPARATUS - An apparatus for segregating electronic components that engages and stops each of a plurality of electronic packages passing down a singulation tube is disclosed. In addition, the segregating apparatus is cable of segregating the electronic packages even though some of them had been linked together during the sealing process. The segregating apparatus includes a first swing arm to clip a electronic component, a second swing arm to clip another electronic component, and a third swing arm to depart the two electronic components, where all of components of the segregating apparatus are driven by a single driving force, reducing the size of the apparatus and the time needed for the segregating process. | 01-14-2010 |
Chang-Yu Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110141086 | ELECTROPHORETIC DISPLAY AND METHOD OF DRIVING THE SAME - An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage. | 06-16-2011 |
Chao Chien Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110032230 | CONTROL DEVICE AND CONTROL METHOD FOR IMAGE DISPLAY - A control device for an image display includes at least two reference points, a modulation unit and a remote controller. The modulation unit modulates the light of a predetermined spectrum generated by the reference points with a brightness variation cycle. The modulation unit controls the reference points to emit the light with a first brightness within a first period of the brightness variation cycle and to emit the light with a second brightness within a second period of the brightness variation cycle, wherein the first brightness and the second brightness are not zero gray level. The remote controller captures the light of the predetermined spectrum with a sampling cycle and demodulates an image variation of the reference points with respect to the remote controller. The present invention further provides a control method for an image display. | 02-10-2011 |
20120113000 | CURSOR CONTROL METHOD AND APPARATUS - A cursor control method for controlling a cursor on an image display includes: providing at least two reference points for generating light of a predetermined spectrum and defining a predetermined area; providing an image sensor pointing inside the predetermined area; receiving the light of the predetermined spectrum by the image sensor to form a digital image; identifying positions and shapes of the images of the reference points on the digital image to form a first parameter; performing distance and angle compensations on the first parameter; moving the aiming point of the image sensor inside the predetermined area to form a second parameter; and calculating an displacement of the images of the reference points on the digital image according to the compensated first and second parameters so as to accordingly control the cursor. The present invention further provides a cursor control apparatus. | 05-10-2012 |
20130335323 | CURSOR CONTROL DEVICE AND SYSTEM - A cursor control device includes an image sensor, at least one button, a processing unit, a selection unit and a transmitter. The image sensor captures a plurality of image frames. The at least one button outputs a trigger signal while being pressed. The processing unit calculates a displacement according to the image frames and outputs a control signal according to the trigger signal. The selection unit selects one of at least two different cursor lock periods. The transmitter outputs the control signal and the displacement, wherein the processing unit controls the transmitter to output zero displacement within the cursor lock period selected after receiving the trigger signal. The present disclosure further provides a cursor control system. | 12-19-2013 |
20140015990 | INTERACTIVE IMAGING SYSTEM AND REMOTE CONTROLLER APPLIED THERETO - An interactive imaging system includes an image system and a remote controller. The image system includes at least one reference beacon, a receiving unit and a host. The at least one reference beacon emits light in an emission pattern. The receiving unit is configured to receive a packet data. The host controls an enable time of the at least one reference beacon according to the packet data. The remote controller includes an image sensor and a transmission unit. The image sensor captures the light emitted from the at least one reference beacon at a sampling period. The transmission unit sends the packet data corresponding to the sampling period of the image sensor. | 01-16-2014 |
20140043233 | INTERACTIVE SYSTEM AND REMOTE DEVICE - An interactive system includes a display, a processor and a remote controller. The display includes at least one reference beacon for providing light with a predetermined feature. The remote controller includes an image sensor configured to capture an image containing the reference beacon and calculates an aiming coordinate according to an imaging position of the reference beacon in the captured image. The processor calculates a scale ratio of a pixel size of the display with respect to that of the image captured by the image sensor and moves a cursor position according to the scale ratio and the aiming coordinate. | 02-13-2014 |
20140247214 | HANDHELD POINTER DEVICE AND TILT ANGLE ADJUSTMENT METHOD THEREOF - An exemplary embodiment of the present disclosure provides a handheld pointer device and a tilt angle adjustment method thereof. The tilt angle adjustment method includes the following steps. Images corresponding to the position of a reference point are captured as the handheld pointer device pointing toward the reference point to generate a plurality of frames. Whether the reference point has substantially moved is subsequently determined based on the plurality of frames. When determines that the reference point has not substantially moved, causes an accelerometer unit of the handheld pointer device to detect the accelerations thereof over various axes so as to update a first tilt angle being used currently to a second tilt angle, accordingly. The handheld pointer device may thus accurately and efficiently calculate the relative position of the reference point with the appropriate tilt angle of the handheld pointer device used. | 09-04-2014 |
20150054745 | HANDHELD POINTER DEVICE AND POINTER POSITIONING METHOD THEREOF - A pointer positioning method for a handheld pointer device includes: capturing a first frame containing a reference point when the handheld pointer device updates a first tilt angle presently used to a second tilt angle; computing a first pointing coordinate according to the image position of the reference point in the first frame and the first tilt angle; computing a second pointing coordinate according to the image position of the reference point in the first frame and the second tilt angle; capturing a second frame containing the reference point to compute a third pointing coordinate according to the image position of the reference point in the second frame and the second tilt angle; generating a cursor parameter for controlling a display position of a cursor on a display apparatus according to the first pointing coordinate, the second pointing coordinate, and the third pointing coordinate. | 02-26-2015 |
Chau-Shiang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100136868 | METHOD OF FORMING A COLOR FILTER TOUCH SENSING SUBSTRATE - A method of forming a color filter touch sensing substrate integrates touch-sensing structures/elements of a touch panel into the inner side of the color filter substrate, which faces a thin film transistor substrate, and forms patterned assistant electrodes on the surfaces of the transparent sensing pads for decreasing the equivalent resistance of the touch-sensing structures/elements. Moreover, since an adjacent transparent conductive layer and an assistant electrode layer are patterned to form the transparent sensing pads and the patterned assistant electrodes, a simplified pattern-transferring process can be applied to the transparent sensing pads and the patterned assistant electrodes, or bridge structures can be formed from the assistant electrode layer for electrically connecting between some transparent sensing pads. Therefore, the forming process is simplified. | 06-03-2010 |
20110157084 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of diode ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each diode ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
20120015464 | METHOD OF FORMING A COLOR FILTER TOUCH SENSING SUBSTRATE - A method of forming a color filter touch sensing substrate integrates touch-sensing structures/elements of a touch panel into the inner side of the color filter substrate, which faces a thin film transistor substrate, and forms patterned assistant electrodes on the surfaces of the transparent sensing pads for decreasing the equivalent resistance of the touch-sensing structures/elements. Moreover, since an adjacent transparent conductive layer and an assistant electrode layer are patterned to form the transparent sensing pads and the patterned assistant electrodes, a simplified pattern-transferring process can be applied to the transparent sensing pads and the patterned assistant electrodes, or bridge structures can be formed from the assistant electrode layer for electrically connecting between some transparent sensing pads. Therefore, the forming process is simplified. | 01-19-2012 |
Cheng-Lin Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090209098 | Multi-Step Cu Seed Layer Formation for Improving Sidewall Coverage - A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber. | 08-20-2009 |
20090209106 | In Situ Cu Seed Layer Formation for Improving Sidewall Coverage - A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer. | 08-20-2009 |
20090258487 | Method for Improving the Reliability of Low-k Dielectric Materials - A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer. | 10-15-2009 |
20100171220 | Reducing Resistivity in Interconnect Structures of Integrated Circuits - An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening. | 07-08-2010 |
20110171826 | Reducing Resistivity in Interconnect Structures of Integrated Circuits - An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening. | 07-14-2011 |
20110304042 | Copper Bump Structures Having Sidewall Protection Layers - A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer. | 12-15-2011 |
20120306073 | Connector Design for Packaging Integrated Circuits - A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar. | 12-06-2012 |
20120306080 | Packaging Structures and Methods - A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier. | 12-06-2012 |
20120322261 | Methods for Via Structure with Improved Reliability - Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line. | 12-20-2012 |
20130020698 | Pillar Design for Conductive Bump - A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material. | 01-24-2013 |
20130056865 | Method of Three Dimensional Integrated Circuit Assembly - A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. | 03-07-2013 |
20130119382 | Plating Process and Structure - A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed. | 05-16-2013 |
20130119552 | Method for Forming Chip-on-Wafer Assembly - A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip. | 05-16-2013 |
20130140563 | Plating Process and Structure - A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. | 06-06-2013 |
20130330921 | Plating Process and Structure - A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. | 12-12-2013 |
20140035135 | SOLDER BUMP FOR BALL GRID ARRAY - A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1. | 02-06-2014 |
20140038405 | Packaging Structures and Methods with a Metal Pillar - A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier. | 02-06-2014 |
20140167254 | BUMP STRUCTURES FOR SEMICONDUCTOR PACKAGE - A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The lateral dimension of the first metal pillar is greater than the lateral dimension of the second metal pillar. | 06-19-2014 |
20140264828 | Method and Apparatus for a Conductive Pillar Structure - A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width. | 09-18-2014 |
20140264838 | Method and Apparatus for a Conductive Bump Structure - A method and apparatus for a conductive bump structure is provided. The conductive bump structure may include a conductive layer and a conductive bump formed over a through via (“TV”). The TV may be formed through a substrate and a passivation layer. The TV may have a top surface extending above a top surface of the passivation layer. The conductive layer may be formed directly over the TV using one or more electroless plating processes. The conductive layer may have sides that may taper from a top surface of the conductive layer to the top surface of the passivation layer. The conductive layer may include a plurality of layers, wherein each layer may be formed using one or more electroless plating processes. The conductive bump may be formed on the conductive layer and may be reflowed to couple the conductive bump to the conductive layer. | 09-18-2014 |
20140264843 | Integrated Circuit Structure Having Dies with Connectors - An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer. | 09-18-2014 |
20140287553 | Method for Forming Chip-on-Wafer Assembly - A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip. | 09-25-2014 |
20140339697 | Solder Bump for Ball Grid Array - A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1. | 11-20-2014 |
20140346672 | Integrated Circuit Structure Having Dies with Connectors - An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion. | 11-27-2014 |
20140361432 | Pillar Design for Conductive Bump - A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material. | 12-11-2014 |
Chia-Horng Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110080396 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 04-07-2011 |
20110115780 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 05-19-2011 |
20110285693 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 11-24-2011 |
20120200551 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 08-09-2012 |
Chia-Te Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100263945 | Rechargeable Electromagnetic Pen - A rechargeable electromagnetic pen is disclosed. The rechargeable electromagnetic pen comprises a rechargeable and storable electrical power source system, an electrical power receiving terminal and a signal transformation circuit. The electrical power source system provides the rechargeable electromagnetic pen with electrical power for emitting electromagnetic signal to an array of antenna loops of a digital tablet. The electrical power-receiving terminal receives electrical power signal generating from electric energy transformation and transmission between the electrical power receiving terminal and a charge site. The signal transformation circuit processes and transforms the electrical power signal and charges the electrical power source system. | 10-21-2010 |
20110214923 | LIGHT WEIGHT AND FULL PLANAR ELECTROMAGNETIC DIGITIZER - A light weight and full planar electromagnetic digitizer is disclosed. The electromagnetic digitizer comprises a upper board, a lower board, a circuit board and an antenna board and a cushion board. The circuit board has at least one electronic device to control the antenna board to transmit or receive electromagnetic signals and process received electromagnetic signals. The cushion board has at least one hole or cave to accommodate the electronic device. The circuit board, the antenna board and the cushion board are stacked between the upper board and the lower board. | 09-08-2011 |
20110227588 | LAYOUT FOR ANTENNA LOOPS HAVING BOTH FUNCTIONS OF CAPACITANCE INDUCTION AND ELECTROMAGNETIC INDUCTION - The present invention relates to a layout for antenna loops having both functions of capacitance induction and electromagnetic induction, and particularly relates to the layout for antenna loops having both functions of capacitance induction and electromagnetic induction, wherein the capacitance detection elements are integrated with the antenna loops. In this layout for antenna loops, each of the antenna loops therein is separated into three sections, and there are several geometric structures fabricated in two of these sections. These geometric structures are capacitance detection elements. Therefore, the two sections are directly fabricated to be the capacitance detection elements because of these geometric structures. By this way, the antenna loops can be integrated with the capacitance detection elements and the capacitance detection elements do not prevent the antenna loops from receiving the electromagnetic signals. | 09-22-2011 |
20110298748 | INPUT APPARATUS WITH INTEGRATED DETECTION SECTIONS OF ELECTROMAGNETIC TYPE AND CAPACITIVE TYPE - An input apparatus with integrated detection sections of electromagnetic type and capacitive type is disclosed. The apparatus comprises a substrate, a control device and at least one signal processing device on the substrate. The substrate comprises an electromagnetic sensor coil layout and a capacitive sensor layout. | 12-08-2011 |
Chien-Chao Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090203202 | Strained Gate Electrodes in Semiconductor Devices - Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode. | 08-13-2009 |
Chien-Cheng Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100171915 | Liquid Crystal Display Device - An LCD device having a backlight module, a display module and an adhesive layer is provided. The backlight module has an inner fringe for holding the display module. The display module sequentially includes a lower polarizer, a display panel and an upper polarizer. The edge of the upper surface of the display panel is exposed because the area of the upper polarizer is smaller than the area of the display panel. The adhesive layer has a first adhesive film and a second adhesive film. The display module is disposed on the inner fringe of the backlight module by using the adhesive layer wherein the first adhesive film is on the side wall of the backlight module and portion of the edge of the upper surface of the display panel, the second adhesive film is on the portion of the first adhesive film and the exposed edge of upper surface of the display panel. | 07-08-2010 |
Chien-Hsing Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090013117 | SYSTEM AND METHOD FOR GENERATING INTERRUPT - A system and a method for generating an interrupt are provided. In the interrupt generating method, a time-out mechanism is executed by a second network component of a computer system after a packet processing action is finished. An interrupt is generated by the second network component only if a first network component of the computer system does not execute a polling action during a predefined period after the time-out mechanism is processed. Thus, it is not necessary to generate the interrupt every time after processing a network packet, so that less interrupts are generated and accordingly the loading of the computer system is reduced. Moreover, the reaction time of the computer system is kept to ensure the efficiency of the computer system. | 01-08-2009 |
Chien-Jung Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110096298 | ILLUMINATION SYSTEM AND PROJECTION APPARATUS - An illumination system includes a chip package, a first dichroic film, a second dichroic film, and a third dichroic film. The first dichroic film, the second dichroic film, and the third dichroic film are not parallel to each other and do not cross each other. The chip package includes a first light-emitting chip capable of emitting a first light beam, a second light-emitting chip capable of emitting a second light beam, and a third light-emitting chip capable of emitting a third light beam. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are arranged in a row. The first dichroic film reflects the first light beam and transmitting the second light beam, the second dichroic film reflects the second light beam, the first dichroic film and the second dichroic film transmit the third light beam, and the third dichroic film reflects the third light beam. | 04-28-2011 |
20110096299 | ILLUMINATION SYSTEM AND PROJECTION APPARATUS HAVING THE SAME - An illumination system includes a chip package, a first dichroic film, a second dichroic film, and a third dichroic film. The first dichroic film, the second dichroic film, and the third dichroic film are not parallel to each other and cross one another at an identical region. The chip package includes a first light-emitting chip capable of emitting a first light beam, a second light-emitting chip capable of emitting a second light beam, and a third light-emitting chip capable of emitting a third light beam. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are arranged to form a delta arrangement. The first dichroic film is capable of reflecting the first light beam, and the second dichroic film is capable of reflecting the second light beam. The first dichroic film is capable of transmitting the third light beam, and the third dichroic film is capable of reflecting the third light beam. | 04-28-2011 |
20130051439 | FREQUENCY CALIBRATION DEVICE AND METHOD FOR PROGRAMMABLE OSCILLATOR - A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator. | 02-28-2013 |
20130057473 | MOUSE DEVICE - There is provided a mouse device including a control chip and at least one control component. The control chip includes a voltage detection circuit coupled to the at least one control component through at least one multiplexing pin and detects at least one voltage value on the at least one multiplexing pin using the voltage detection circuit thereby identifying an operating state of the at least one control component. | 03-07-2013 |
Chi-Heng Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090172617 | Advisory System for Verifying Sensitive Circuits in Chip-Design - A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits. | 07-02-2009 |
Chi-Hsiang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110155460 | SUBSTRATE AND SUBSTRATE BONDING DEVICE USING THE SAME - A substrate and a substrate bonding device using the same are provided. The substrate includes a base, upper and lower metal layers, and upper and lower covering layers. The base has an upper surface, a lower surface and a through-hole passing there through, wherein the upper and lower covering layers respectively covers the upper and lower metal layers respectively disposed on the upper and lower surfaces of the base. The lower metal layer has an electrical bonding portion and a strengthening bonding portion insulated with each other. The strengthening bonding portion enhances the bonding strength between the substrate and another substrate. The upper metal layer is electrically connected to the electrical bonding portion via the through hole. The lower covering layer exposes the electrical bonding portion and the strengthening bonding portion so as to be respectively connected with two bonding portions of the another substrate. | 06-30-2011 |
20110255033 | Liquid Crystal Display Device - A liquid crystal display device includes a light guide plate, a light source module, a first tape, a circuit board holder and an elastic support piece, an optical film, a panel, and an elastic buffer piece. By implement of the liquid crystal display device of this invention, the thickness and the weight of the liquid crystal display device can be reduced. | 10-20-2011 |
Chi-Hsun Huang, Hsin Chu TW
Patent application number | Description | Published |
---|---|---|
20090033883 | PROJECTION APPARATUS AND METHOD FOR ACTIVATING A PROJECTION APPARATUS - A projection apparatus includes an illuminating unit, an imaging unit, a lens unit, and a control unit. The illuminating unit includes a light source, and a light source driving module operable to drive the light source to provide an illumination beam. The imaging unit is operable so as to modulate the illumination beam into an image beam. The lens unit is disposed on an optical path of the image beam for projecting the image beam. The control unit is coupled electrically to the illuminating unit and the imaging unit. The control unit is configured to execute an activating thread for initializing the imaging unit after controlling initial driving of the light source by the light source driving module, and a monitoring thread for monitoring the light source driving module for a success signal that indicates successful provision of the illumination beam by the light source. | 02-05-2009 |
20140333979 | LASER SCANNING DEVICE AND CONTROL METHOD THEREOF - A laser scanning device and a control method thereof are provided. The method includes: providing a control signal to an oscillating reflective mirror of the device; setting a frequency of the control signal gradually decreased from a maximal-setting-value of a resonant frequency of the mirror; judging whether a light detector receives a laser light reflected by the mirror according to an edge signal of the detector; judging whether a pulse width of the edge signal is equal to a predetermined pulse width when the detector receives the laser light: (1) increasing the frequency of the control signal when the pulse width of the edge signal is greater than the predetermined pulse width, (2) decreasing the frequency of the control signal when the pulse width of the edge signal is less than the predetermined pulse width. The time and labor for measuring the scanning frequency of the mirror may be saved. | 11-13-2014 |
Ching-Cheng Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080284016 | Reliable metal bumps on top of I/O pads after removal of test probe marks - In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad. | 11-20-2008 |
20110278727 | CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME - A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers. | 11-17-2011 |
20110291259 | Reliable metal bumps on top of I/O pads after removal of test probe marks - In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad. | 12-01-2011 |
Ching-Chou Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110199789 | LIGHT SOURCE APPARATUS - A light source apparatus including a light source, an optical fiber, a light guide module, and a light shape adjustment element is provided. The light source emits a light beam. The optical fiber disposed in a transmission path of the light beam has a light incident end and a light emitting end. The light beam enters the optical fiber through the light incident end and leaves the optical fiber through the light emitting end. The light guide module has a first surface, a second surface opposite to the first surface, and a light incident surface connecting the first surface and the second surface. The light beam from the light emitting end enters the light guide module through the light incident surface. The light shape adjustment element is connected to the light guide module and capable of changing a light shape of an emitted light from the light guide module. | 08-18-2011 |
Ching-Yu Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080308894 | Electro-Optical Apparatus and a Circuit Bonding Detection Device and Detection Method Thereof - This invention provides a circuit bonding detection device, a detection method thereof and an electro-optical apparatus incorporating the circuit bonding detection device. The circuit bonding detection device includes a substrate, a circuit module, a set of sensors, and a detection unit. A plurality of contact pads is disposed on the substrate. The circuit module includes a plurality of conductive bumps corresponding to the contact pads. The sensors are disposed on two sides of at least one of contact pads or of the corresponding conductive bumps. The detection unit is electrically coupled with the set of sensors and transmits a fault signal when at least one of the contact pads and the corresponding conductive bumps deforms and contacts the sensors. | 12-18-2008 |
Chin-Yi Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090159946 | Logic Non-Volatile Memory Cell with Improved Data Retention Ability - A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric. The first and the second floating gates are electrically disconnected. The memory cell further includes a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates. The third transistor is a selector of the memory cell and is electrically coupled to the first and the second transistors. | 06-25-2009 |
20150048433 | Contact Formation for Split Gate Flash Memory - An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array. | 02-19-2015 |
Chun-Kai Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090195562 | Display Device and Driving Method Thereof - A driving method for driving a display device is provided. The driving device includes at least a pixel. The pixel has a first, a second, and a third sub-pixels respectively associated with three primary colors. The driving method includes the steps of driving the first, second and third sub-pixels respectively in accordance with a first, a second and a third driving sequences during a first, a second and a third frame periods. Moreover, the first, the second and the third driving sequences are different from each other. A display device applying said driving method is also provided herein. | 08-06-2009 |
20090256833 | Method for Driving Display Device - A method for driving a display device is provided herein. The display device includes a plurality of scan lines. The method comprises following steps: dividing the scan lines into a plurality of groups, each of which comprises at least two scan lines, i.e. a first and a second scan line; during a first frame period, sequentially enabling the first and second scan line of each group in accordance with a first driving sequence; and during a second frame period, sequentially enabling the first and second scan line of each group in accordance with a second driving sequence, wherein the first driving sequence is different with the second driving sequence. | 10-15-2009 |
Hong-Ji Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100182558 | LIQUID CRYSTAL DISPLAY PANEL - According to the present invention, an LCD panel includes a first substrate, a second substrate placed opposite to the first substrate, and a liquid crystal layer placed between the first substrate and the second substrate. The first substrate includes a pixel electrode and a first common electrode. The pixel electrode includes a plurality of first protruding nodes, and the first common electrode includes a plurality of second protruding nodes interleaved with the plurality of first protruding nodes. The second substrate includes a second common electrode corresponding to the first common electrode. The second common electrode includes a plurality of third protruding nodes corresponding to the second protruding nodes. | 07-22-2010 |
20100220068 | Method for Mitigating Pooling Mura on Liquid Crystal Display Apparatus and Liquid Crystal Display Apparatus - A method for mitigating pooling mura on LCD apparatus and a LCD apparatus are provided. The method is adapted for a LCD apparatus having a plurality of pixels. The LCD apparatus is for displaying frames according to a received original display data, and each of at least a part of the pixels comprises two pixel electrodes to drive a plurality of liquid crystal molecules between the two pixel electrodes. The method comprises changing a corresponding portion of the original display data so as to rotate at least a part of the liquid crystal molecules between the two pixel electrodes of the pressed pixel toward a natural angle; and maintaining another corresponding portion of the original display data. The natural angle is a finally-presented tilt angle of the liquid crystal molecules between the corresponding two pixel electrodes having substantially no potential difference therebetween. | 09-02-2010 |
20110057898 | TOUCH-SENSING STRUCTURE FOR TOUCH PANEL AND TOUCH-SENSING METHOD THEREOF - In a touch-sensing structure for a touch panel and a touch-sensing method thereof, the touch-sensing structure includes a plurality of first conducting wires paralleled to each other and a first conductor. A terminal of each first conducting wire is electrically coupled to the first conductor, so as to divide the conductor into a plurality of first line segments. The resistance of each first conducting wire is smaller than that of each first line segment. Wherein, when the displaying area of the touch panel receives an external force, a first conducting wire corresponding to the position designated by the external force is electrically coupled to a reference potential. | 03-10-2011 |
Hon-Lin Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100090319 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 04-15-2010 |
20100102453 | Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure - A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV. | 04-29-2010 |
20100276787 | Wafer Backside Structures Having Copper Pillars - An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL. | 11-04-2010 |
20100330798 | Formation of TSV Backside Interconnects by Modifying Carrier Wafers - An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×10 | 12-30-2010 |
20110049706 | Front Side Copper Post Joint Structure for Temporary Bond in TSV Application - An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via. | 03-03-2011 |
20110165776 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 07-07-2011 |
20120056328 | Die Edge Contacts for Semiconductor Devices - A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. | 03-08-2012 |
20130328215 | Die Edge Contacts for Semiconductor Devices - A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. | 12-12-2013 |
Hsin-Chang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100238386 | Display panel and method of repairing bright point thereof - A display panel has a portion of a color filter or patterned color layer with a thickness of at least half of the cell gap of the display panel, wherein the repair method includes providing a energy light beam to the portion of the color filter or the patterned color layer in the sub-pixel region with a bright point defect to make the portion of the color filter or patterned color layer have porous structure so that bright point is repaired to become a grey point or a dark point | 09-23-2010 |
20130242240 | DISPLAY PANEL - A display panel has a portion of a color filter or patterned color layer with a thickness of at least half of the cell gap of the display panel, wherein the repair method includes providing a energy light beam to the portion of the color filter or the patterned color layer in the sub-pixel region with a bright point defect to make the portion of the color filter or patterned color layer have porous structure so that bright point is repaired to become a grey point or a dark point. | 09-19-2013 |
Hsuen-Ying Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090174831 | LIQUID CRYSTAL DISPLAY WITH UNIFORM FEED-THROUGH VOLTAGE - A liquid crystal display with uniform feed-through voltage includes a plurality of data lines for receiving a plurality of data signals respectively, a plurality of gate lines for receiving a plurality of gate signals respectively, a plurality of common lines for receiving a common voltage, a plurality of storage units, a plurality of first switches, and a plurality of second switches. Each storage unit includes a first liquid crystal capacitor and a second liquid crystal capacitor coupled to a corresponding common line. Each first switch is coupled to a corresponding data line, a corresponding gate line, and a corresponding first liquid crystal capacitor. Each second switch is coupled to a corresponding gate line, a corresponding first switch, and a corresponding second liquid crystal capacitor. The capacitance of the gate-source capacitor of each first switch is greater than the capacitance of the gate-source capacitor of each second switch. | 07-09-2009 |
Hua-Chiang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090051334 | Droop circuits and multi-phase DC-DC converters - A droop circuit of a DC-DC converter is provided, wherein the DC-DC converter includes an output inductor coupled between an output of the DC-DC converter and a phase node for providing an output voltage. A current sense device is coupled between the phase node and the output of the DC-DC converter, includes an inductor coupled to the phase node and senses a current from the phase node. A first resistor is coupled to the current sense device. An amplifier circuit includes an amplifier having an inverting input, a non-inverting input coupled to the first resistor and an output directly connected to the inverting input, and a second resistor coupled between the inverting input and the output of the DC-DC converter. The amplifier circuit provides a droop current according to the second resistor and a voltage difference between the non-inverting input and the output of the DC-DC converter, and the voltage difference is related to the current. | 02-26-2009 |
20090051335 | Multi-phase DC-DC converter and method for balancing channel currents - A multi-phase DC-DC converter is provided. A plurality of switching sets are coupled to an output, wherein each switching set includes a phase node. A plurality of inductors are separately coupled between the phase nodes and the output. A sense circuit has a plurality of sense units separately coupled to the phase nodes, each sensing a signal from the corresponding phase node and generating a sensing signal. A PWM generator includes a plurality of subtracting units, each subtracting a first signal from one of the sensing signals to generate a difference signal, wherein the first signal is generated by summing each of the sensing signals divided by a predetermined value except for the one of the sensing signals. The PWM generator generates a plurality of PWM signals to balance the currents of the inductors according to the difference signals. | 02-26-2009 |
20090153110 | Control method for multi-phase DC-DC controller and multi-phase DC-DC controller - A multi-phase DC-DC controller. The multi-phase DC-DC controller comprises converter channels, a channel control device and a power control device. Each converter channel comprises a switch device, a first output node and an inductor coupled between the switch device and the first output node. The channel control device generates adjusted pulse width modulation signals according to control signals of the converter channels to respectively control operation of the switch device in each converter channel. The power control device generates the control signals according to sensed currents in the converter channels so as to dynamically turn on or off each converter channel according to the sensed currents. | 06-18-2009 |
20090153114 | DC-DC converters with transient response control - A DC-DC converter used to convert an input voltage to an output voltage is disclosed. The DC-DC converter comprises a pulse-width-modulation (PWM) generator, a transient boost circuit, a logic circuit, a switching device, and a buck circuit. The pulse-width-modulation (PWM) generator generates a PWM signal according to the output voltage. The transient boost circuit generates an adjusting signal according to the variation of the output voltage. The logic circuit generates a switch signal according to the PWM signal and the adjusting signal. The switching signal is at a high level when the PWM signal or the adjusting signal is at the high level, and the switching signal is at a low level when the PWM signal and the adjusting signal are at the low level. The switching device converts the input voltage to a driving signal according to the switching signal. The buck circuit receives the driving signal to generate the output voltage. | 06-18-2009 |
20110316503 | Control Method for Multi-Phase DC-DC Controller and Multi-Phase DC-DC Controller - A multi-phase DC-DC controller. The multi-phase DC-DC controller comprises converter channels, a channel control device and a power control device. Each converter channel comprises a switch device, a first output node and an inductor coupled between the switch device and the first output node. The channel control device generates adjusted pulse width modulation signals according to control signals of the converter channels to respectively control operation of the switch device in each converter channel. The power control device generates the control signals according to sensed currents in the converter channels so as to dynamically turn on or off each converter channel according to the sensed currents. | 12-29-2011 |
Huan-Tsung Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
20080258185 | Semiconductor structure with dielectric-sealed doped region - Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. | 10-23-2008 |
20140252426 | Semiconductor Structure with Dielectric-Sealed Doped Region - Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. | 09-11-2014 |
Hung-Sheng Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110096567 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE - A light guide plate is adapted for a backlight module having at least one light emitting device, and the light guide plate includes a light emitting surface, a surface opposite to the light emitting surface, a light incident surface connected with the light emitting surface and the surface, and a plurality of microstructures disposed on the light emitting surface or the surface. 90 percent or more of the surface or the light emitting surface is flat. At least one of the light emitting devices is disposed beside the light incident surface and capable of emitting a light beam. The light incident surface is capable of making the light beam enter the light guide plate and the light emitting surface is capable of making the light beam transmit outside the light guide plate. A backlight module is also provided. | 04-28-2011 |
Jia-Bin Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100289432 | Light emitting apparatus and control method thereof - A light emitting apparatus and a control method thereof are provided. The light emitting apparatus has a semiconductor device capable of emitting light, and the control method includes the following descriptions. A driving power of the semiconductor device is reduced to an ideal power stepwise and gradually. After every time the driving power of the semiconductor device is reduced, the semiconductor device continually emits the light by the reduced driving power within a predetermined time. | 11-18-2010 |
Ji-Chung Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100088129 | Technology Selection and Pricing System - A method of selecting a technology for manufacturing an integrated circuit includes designating candidate technologies for manufacturing the integrated circuit; generating design and performance data from the integrated circuit, wherein the design and performance data are generated for each of the candidate technologies; and generating die prices from the integrated circuit, wherein the die prices are generated for each of the candidate technologies. | 04-08-2010 |
Jiun-Kai Huang, Hsin Chu TW
Patent application number | Description | Published |
---|---|---|
20110001504 | METHOD AND APPARATUS OF DEEMBEDDING - Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures. | 01-06-2011 |
20120267626 | Transmission Line Characterization Using EM Calibration - A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length. | 10-25-2012 |
Jung-Yen Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100171905 | TRANSFLECTIVE DISPLAY PANEL - A transflective display panel includes a first substrate, a plurality of electroluminescent (EL) elements disposed on the first substrate, a plurality of reflectors disposed on the first substrate, a second substrate disposed opposite to the first substrate, a plurality of transparent electrodes disposed on a side of the second substrate opposite to the first substrate, a plurality of color filter layers disposed on a side of the second substrate opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. Accordingly, a problem of insufficient contrast ratio of the transflective display panel can be solved, when the ambient light is too high. | 07-08-2010 |
20110037729 | OLED TOUCH PANEL AND METHOD OF FORMING THE SAME - A displaying region and a sensing region are defined in each pixel region of the OLED touch panel of the present invention. The readout thin film transistor of the sensing region is formed by the same processes with the drive thin film transistor of the displaying region. The top and bottom electrodes of the optical sensor are formed by the same processes with the top and bottom electrodes of the OLED. Accordingly, the present invention can just add a step of forming the patterned sensing dielectric layer to the processes of forming an OLED panel to integrate the optical sensor into the pixel region of the OLED panel. Thus, an OLED touch panel is formed. | 02-17-2011 |
Ke Ming Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100247742 | Three-dimensional object forming apparatus and method for forming three-dimensional object - A three-dimensional object forming apparatus is provided, which at least comprises: a construction stage, a printing module, plural temporary storage tanks, plural powder supplying tanks, a construction tank, a printing quality inspection component for forming a pattern to determine whether the printing module is blocked or not, a maintenance device, and a dust-proof device. | 09-30-2010 |
20110215117 | Quantitative Powder-Providing Module - The present invention is related to a quantitative powder-providing module, adaptive to a 3D prototyping mechanism, at least includes: a powder-providing tank, which is used for storing a constructive powder and having a powder-dropping opening; and a powder-propelling roller located inside the powder-providing tank and having a plurality of recesses for receiving the constructive powder; when one of the plurality of recesses corresponds to the powder-dropping opening, the constructive powder received in the corresponding recess is output through the powder-dropping opening; wherein each of the plurality of recesses has plural sections, and the amount of powder received in each of the plural sections of the recess is increased from the center of the recess, toward the two sides of the recess. | 09-08-2011 |
20110316907 | INKJET PRINTING SYSTEM - An inkjet printing system comprises: a liquid supply tank; a print device with at least one print cartridge, wherein there is an altitude difference between the print cartridge and the liquid supply tank; an internal pressure-adjusting device connecting to the liquid supply tank and the print cartridge; and working software for calculating a preliminary altitude, and a predetermined liquid supplementing altitude of the print cartridge. When a liquid level of a liquid inside the print cartridge is lower than the preliminary altitude and below an lower limit of the predetermined liquid supplementing altitude, the working software controls the internal pressure-adjusting device to suck partial gas from the print cartridge into the liquid supply tank to increase a negative pressure inside the print cartridge, and the liquid stored in the liquid supply tank is introduced into the print cartridge to balance the negative pressure inside the print cartridge. | 12-29-2011 |
K. T. Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110001194 | Hybrid Process for Forming Metal Gates - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon. | 01-06-2011 |
Kuan-Chieh Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090263674 | Forming Sensing Elements above a Semiconductor Substrate - An integrated circuit structure includes a substrate and a metallization layer over the substrate. The metallization layer includes a dielectric layer and metal lines in the dielectric layer. The integrated circuit structure further includes a sensing element over the metallization layer. The sensing element may be formed in passivation layers. | 10-22-2009 |
Kuan-Chun Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110141420 | MULTI-DOMAIN VERTICAL ALIGNMENT LIQUID CRYSTAL DISPLAY DEVICE AND PIXEL STRUCTURE THEREOF - An MVA LCD device includes a first alignment region, a second alignment region, a third alignment region, and a fourth alignment region. The liquid crystal molecules disposed in the first alignment region have a first aligning direction, and the azimuth angle of the first aligning direction is substantially between 70 and 110 degrees. The liquid crystal molecules disposed in the second alignment region have a second aligning direction, and the azimuth angle of the second aligning direction is substantially between 160 and 200 degrees. The liquid crystal molecules disposed in the third alignment region have a third aligning direction, and the azimuth angle of the third aligning direction is substantially between 250 and 290 degrees. The liquid crystal molecules disposed in the fourth alignment region have a fourth aligning direction, and the azimuth angle of the fourth aligning direction is substantially between −20 and 20 degrees. | 06-16-2011 |
20130002640 | DRIVING CIRCUIT OF A PIXEL OF A LIQUID CRYSTAL DISPLAY PANEL AND DRIVING METHOD THEREOF - A driving circuit of a pixel includes a driving capacitor for driving liquid crystals according to a voltage difference between first and second ends of the driving capacitor, a reference voltage source for providing a reference voltage, a first data line for providing a first driving voltage, a second data line for providing a second driving voltage, a first scan circuit for electrically connecting the first and the second data lines to the first and the second ends of the driving capacitor respectively when the first scan circuit is turned on, a first scan line for controlling on and off states of the first scan circuit, a second scan circuit for electrically connecting the first end and the second end of the driving capacitor when the second scan circuit is turned on, and a second scan line for controlling on and off states of the second scan circuit. | 01-03-2013 |
20140035889 | Display and Gate Driver thereof - A display and a gate driver are disclosed herein, in which the gate driver includes a number of gate driving units, and each of the gate driving units includes a control circuit, a boost circuit, a driver output circuit and a voltage stabilized circuit. The control circuit is electrically connected to a previous gate driving unit and a next gate driving unit. The boost circuit is electrically connected to the control circuit for driving the next gate driving unit. The driver output circuit is electrically connected to the boost circuit and a pixel array for driving at least one scan line in the pixel array. The voltage stabilizing circuit is electrically connected to the boost circuit and the driver output circuit. | 02-06-2014 |
Kun-Fu Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100096630 | Bottom-Gate Thin Film Transistor and Method of Fabricating the Same - A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 10 | 04-22-2010 |
20110012114 | Bottom-Gate Thin Film Transistor and Method of Fabricating the Same - A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 10 | 01-20-2011 |
Kung-Chieh Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110057898 | TOUCH-SENSING STRUCTURE FOR TOUCH PANEL AND TOUCH-SENSING METHOD THEREOF - In a touch-sensing structure for a touch panel and a touch-sensing method thereof, the touch-sensing structure includes a plurality of first conducting wires paralleled to each other and a first conductor. A terminal of each first conducting wire is electrically coupled to the first conductor, so as to divide the conductor into a plurality of first line segments. The resistance of each first conducting wire is smaller than that of each first line segment. Wherein, when the displaying area of the touch panel receives an external force, a first conducting wire corresponding to the position designated by the external force is electrically coupled to a reference potential. | 03-10-2011 |
20110157061 | Touch-Sensing Display Device and Touch-Sensing Module Thereof - A touch-sensing display device, specifically to a borderless touch-sensing display device, is disclosed. The touch-sensing display device includes a display module and a touch-sensing module. The touch-sensing module includes a first sensing sheet and a second sensing sheet, wherein a space exists between the first sensing sheet and the second sensing sheet. The first sensing sheet includes a lens layer, a plurality of first conductive portions, and a conductive film, wherein the conductive film is disposed on the lens layer while the first conductive portions are distributed on two opposite sides of the lens layer. The second sensing sheet includes a substrate, a plurality of second conductive portions, and a plurality of conductive strips, wherein the second conductive portions are selectively distributed on one of two sides of the substrate while the conductive strips are respectively connected to the second conductive portions and have different voltages. | 06-30-2011 |
Kuo-Bin Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100048011 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 02-25-2010 |
Kuo-Tai Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080303102 | Strained Isolation Regions - An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 12-11-2008 |
20090014813 | Metal Gates of PMOS Devices Having High Work Functions - A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device. | 01-15-2009 |
20090230479 | Hybrid Process for Forming Metal Gates of MOS Devices - A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer. | 09-17-2009 |
20140242776 | Strained Isolation Regions - A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 08-28-2014 |
Kuo-Tung Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100149762 | FIXING STRUCTURE AND BACKLIGHT MODULE USING THE SAME - A fixing structure and a backlight module using the same are provided. The fixing structure is used for fixing a circuit board. The circuit board with several openings has an upper surface and a lower surface. The fixing structure includes a back plate and several hooks. The back plate has a contact surface. These hooks are disposed on the contact surface. The hooks go through the openings so that the contact surface contacts the lower surface. The hooks move toward the walls of the openings and press against the upper surface so as to fix the circuit board onto the back plate. | 06-17-2010 |
Mei-Lien Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080309866 | Display Panel with Photo-Curable Sealant and Manufacture Method Thereof - A display panel and a manufacture method thereof are provided. The display panel includes a first substrate, a second substrate, and a sealant. The first substrate has a top surface which includes a signal transmission module parallel to an edge of the top surface. The sealant is disposed on the top surface and parallel to the signal transmission module, which is disposed between the top surface and sealant. The sealant is made of a photo-curable material and includes an inner isolation wall, which is exposed via the signal transmission module. The second substrate is disposed on the sealant and includes an inner surface. A light-shielding structure is disposed on the inner surface and close to an edge of the inner surface. The sealant at least partially overlaps the light-shielding structure. | 12-18-2008 |
20110117804 | Display Panel with Photo-Curable Sealant and Manufacture Method Thereof - A display panel and a manufacture method thereof are provided. The display panel includes a first substrate, a second substrate, and a sealant. The first substrate has a top surface which includes a signal transmission module parallel to an edge of the top surface. The sealant is disposed on the top surface and parallel to the signal transmission module, which is disposed between the top surface and sealant. The sealant is made of a photo-curable material and includes an inner isolation wall, which is exposed via the signal transmission module. The second substrate is disposed on the sealant and includes an inner surface. A light-shielding structure is disposed on the inner surface and close to an edge of the inner surface. The sealant at least partially overlaps the light-shielding structure. | 05-19-2011 |
Ming-Jie Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110076832 | DUAL ETCH METHOD OF DEFINING ACTIVE AREA IN SEMICONDUCTOR DEVICE - A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature. | 03-31-2011 |
20130056830 | Semiconductor Structure and Method - An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness. | 03-07-2013 |
20130092985 | Spacer for Semiconductor Structure Contact - An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1. | 04-18-2013 |
20140162432 | Semiconductor Structure and Method - An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness. | 06-12-2014 |
Po-Chin Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090135195 | Liquid Crystal Display and Method for Adjusting Backlight Brightness Thereof - A liquid crystal display includes a scaler module, a field-programmable gate array (FPGA) module, a buffer, a backlight module and a LCD module. The FPGA module includes a regional peak detector, a backlight control unit and a pixel value control unit. The regional peak detector is configured for detecting a maximum pixel value of each image region of each image. The backlight control unit is configured for selectively adjusting the backlight brightness of one or more image regions of each image. The pixel value control unit is configured for adjusting pixel values of the one or more image regions of each image by shifting binary pixel values to compensate for the influence of backlight adjustment. A method for adjusting backlight brightness of a liquid crystal display is also provided. | 05-28-2009 |
20090135206 | Color management system with advance function module and color management process for display device - A color management system for display device includes a color management controller, a color sensor, and an advance function module configured to implement a process (a) or a process (b) applied to multiple PWM signals generated from the color management controller. Process (a) includes the steps of using a reset signal generated by and synchronized with an image signal, and a counter with special bit length and counting frequency to generate a reference signal synchronized with the image signal, and using the reference signal to synchronize the PWM signals with the image signal as output. Process (b) includes the steps of using a reset signal with special frequency and a counter with special bit length and counting frequency to generate multiple synchronized reference signals with respective different phases, and generating multiple synchronized PWM signals with respective different phases as output by the use of the reference signals. | 05-28-2009 |
Sen-Huang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100297461 | COLOR FILTER BY COPPER AND SILVER FILM AND METHOD FOR MAKING SAME - The present invention discloses a color filter by copper and silver film, comprising: a lower copper layer; a lower silver layer formed on the lower copper layer; a medium formed on the lower silver layer; an upper copper layer formed on the medium; and an upper silver layer formed on the upper copper layer. | 11-25-2010 |
20110049565 | OPTOELECTRONIC DEVICE AND PROCESS FOR MAKING SAME - The present invention discloses an optoelectronic device, comprising: a substrate made of a first material; a region in the substrate, the region being made of a second material different from the first material; and a photo diode formed in the region by ion implantation. The second material for example is silicon germanium (Si1-xGex) or silicon carbide (Si1-yCy), wherein 003-03-2011 | |
20120020529 | DISPLACEMENT ESTIMATION METHOD AND DISPLACEMENT ESTIMATION DEVICE USING THE SAME - The present invention provides a displacement estimation method including the steps of: acquiring an image frame and determining a quality threshold according to a sampling parameter; calculating a quality parameter of the image frame; and comparing the quality parameter and the quality threshold to determine whether to post-process the image frame. In the displacement estimation method of the present invention, the quality threshold can be adjusted dynamically so as to reduce the possibility of outputting error displacement. The present invention further provides a displacement estimation device. | 01-26-2012 |
20120085656 | COLOR FILTER BY COPPER AND SILVER FILM AND METHOD FOR MAKING SAME - The present invention discloses a color filter by copper and silver film, comprising: a lower copper layer; a lower silver layer formed on the lower copper layer; a medium formed on the lower silver layer; an upper copper layer formed on the medium; and an upper silver layer formed on the upper copper layer. | 04-12-2012 |
20130072771 | OPTICAL FINGER MOUSE, ELECTRONIC DEVICE AND PHYSIOLOGICAL CHARACTERISTICS DETECTION DEVICE - There is provided an optical finger mouse including two light sources, an image sensor and a processing unit. The two light sources emit light of different wavelengths to illuminate a finger surface. The image sensor receives reflected light from the finger surface to generate a plurality of image frames. The processing unit detects a displacement and a contact status of the finger surface and a physiological characteristic of a user according to the plurality of image frames. There is further provided an electronic device and a physiological characteristic detection device. | 03-21-2013 |
20130113705 | OPTICAL MOUSE AND OPERATING METHOD THEREOF - There is provided an operating method of an optical mouse including a first mode and a second mode. In the first mode, the optical mouse detects a finger displacement, a contact status and a physiological characteristic according to a plurality of image frames associated with a finger surface. In the second mode, the optical mouse calculates a mouse displacement according to a plurality of image frames associated with a work surface. There is further provided an optical mouse. | 05-09-2013 |
20130114852 | HUMAN FACE RECOGNITION METHOD AND APPARATUS - A human face recognition method and apparatus are provided. A processor of the human face recognition apparatus calculates red, green, and blue component statistic information for each of a plurality of human face images. The processor uses an independent component analysis algorithm to analyze component statistic information of two colors and derive a piece of first component information and a piece of second component information. The processor transforms the pieces of first component information and second component information into a frequency domain to derive a piece of first frequency-domain information and a piece of second frequency-domain information. The processor calculates an energy value of the first frequency-domain information within a frequency range. The energy value is used to decide whether the human face images are captured from a human being. | 05-09-2013 |
20130127721 | OPTICAL FINGER MOUSE, MOUSE CONTROL MODULE AND PHYSIOLOGY DETECTION METHOD THEREOF - There is provided a mouse control module including two light sources, an image sensor, a processing unit and a communication unit. The two light sources emit light of different wavelengths to illuminate a finger surface. The image sensor receives reflected light from the finger surface to generate a plurality of image frames. The processing unit detects a displacement of the finger surface and a physiological characteristic of a user according to the plurality of image frames. The communication unit encodes and/or sequences the displacement and the physiological characteristic so as to generate finger and physiology information. There is further provided an optical finger mouse. | 05-23-2013 |
20130127722 | KEYBOARD MODULE AND DISPLAY SYSTEM - There is provided a keyboard module including a plurality of keyboard keys, an optical finger mouse and a transmission interface. The keyboard keys are configured to trigger a digital signal. The optical finger mouse is configured to detect a physiological characteristic and a displacement. The transmission interface is configured to send the digital signal, the physiological characteristic and the displacement to a display device. There is further provided a display system. | 05-23-2013 |
20130131473 | OPTICAL DISTANCE MEASUREMENT SYSTEM AND OPERATION METHOD THEREOF - There is provided an operation method of an optical distance measurement system including a first mode and a second mode. The first mode is configured to detect a finger distance. The second mode is configured to detect a physiological characteristic, wherein the optical distance measurement system transfers from the first mode to the second mode when the finger distance is within a predetermined range. There is further provided an optical distance measurement system. | 05-23-2013 |
20130131474 | REMOTE CONTROLLER AND DISPLAY SYSTEM - There is provided a remote controller including a plurality of press buttons, an optical finger mouse and a transmission interface. The press buttons are configured to trigger a control signal. The optical finger mouse is configured to detect a physiological characteristic and a displacement. The transmission interface is configured to output the control signal, the physiological characteristic and the displacement to a display device. There is further provided a display system. | 05-23-2013 |
20130229514 | DISPLACEMENT DETECTION DEVICE AND OPERATING METHOD THEREOF - There is provided a displacement detection device including an image sensor, a light source, a light control unit and a processing unit. The image sensor captures image frames at a sampling frequency. The light source provides, in a speed mode, light for the image sensor in capturing the image frames. The light control unit controls the light source with the speed mode to turn on at a lighting frequency or to turn off serially. The processing unit calculates a displacement according to the image frames captured when the light source turns on to be served as an estimated displacement for an interval during which the light source turns off. There is further provided an operating method of a displacement detection device. | 09-05-2013 |
20140023230 | GESTURE RECOGNITION METHOD AND APPARATUS WITH IMPROVED BACKGROUND SUPPRESSION - A gesture recognition method with improved background suppression includes the following steps. First, a plurality of images are sequentially captured. Next, a position of at least one object in each of the images is calculated to respectively obtain a moving vector of the object at different times. Then, an average brightness of the object in each of the images is calculated. Finally, magnitudes of the moving vectors of the object at different times are respectively adjusted according to the average brightness of the object in each of the images. There is further provided a gesture recognition apparatus using the method mentioned above. | 01-23-2014 |
20140028868 | DISPLACEMENT DETECTION DEVICE AND POWER SAVING METHOD THEREOF - A displacement detection device includes an image sensor, a light source and a processing unit. The image sensor is configured to successively capture images. The light source provides light with an emission frequency and an emission duration for the image sensor in capturing the images. The processing unit is configured to calculate a displacement according to the images and to adjust both the emission frequency and the emission duration according to the displacement. | 01-30-2014 |
20140148709 | SYSTEM AND METHOD FOR INTEGRATING HEART RATE MEASUREMENT AND IDENTITY RECOGNITION - A system for integrating heart rate measurement and identity recognition is provided. The system includes a storage unit, an image sensor, an identity recognition unit and a frequency extractor. The storage unit stores a user information database. The image sensor captures a plurality of skin images of a user during a time period. The identity recognition unit receives a physiological feature from the user and recognizes the user by comparing the physiological feature with the user information database in the storage unit. The frequency extractor obtains a frequency signal by extracting a motion signal from the skin images according to the brightness change of the different color lights in the skin images during a time period. The frequency signal represents a frequency in a specific frequency interval, and it represents heart rate information of the user. A method for use in the above-mentioned system is also disclosed. | 05-29-2014 |
20140312386 | OPTOELECTRONIC DEVICE HAVING PHOTODIODES FOR DIFFERENT WAVELENGTHS AND PROCESS FOR MAKING SAME - An optoelectronic device includes: a substrate made of a first material; a region in the substrate, the region being made of a second material different from the first material; an N-well in the region made of the second material; and a photo diode formed in the region by ion implantation. The second material for example is silicon germanium (Si | 10-23-2014 |
Shao-Chang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080211027 | ESD structure without ballasting resistors - An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor. | 09-04-2008 |
Sheng-Wen Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100283402 | BACKLIGHT MODULE FOR LCD DEVICE - A backlight module includes a connector capable of performing voltage conversion or a voltage converter capable of transmitting signals. The connector or the voltage converter, disposed between an inverter and a lamp set, receives low-voltage signals generated by the inverter, performs voltage conversion, and outputs high-voltage signals for driving the lamp set. | 11-11-2010 |
20110216055 | ELECTROPHORETIC DISPLAY AND METHOD OF DRIVING THE SAME - A method of driving an electrophoretic display is set forth for avoiding image-edge residual while sequentially displaying a first frame and a second frame. During the time of displaying the first frame, set a common voltage to be a first voltage, apply a second voltage different from the first voltage to a first pixel for writing a first data signal into the first pixel, and apply the first voltage to a second pixel adjacent to the first pixel for retaining a second data signal of the second pixel, which is different from the first data signal. During the time of displaying the second frame, set the common voltage to be the second voltage, apply the first voltage to the first pixel for writing the second data signal into the first pixel, and apply the first voltage to the second pixel for retaining the second data signal of the second pixel. | 09-08-2011 |
20110285617 | Electrophoretic Display and Pixel Structure Therein - A pixel structure is formed in a pixel area and coupled to a scan line and a data line. The pixel structure includes a first transistor, a second transistor and a pixel electrode. The first transistor is formed in the pixel area and coupled to the scan line and the data line. The second transistor is formed in the pixel area and coupled to the first transistor. The pixel electrode is formed in the pixel area and coupled to the second transistor. The pixel electrode includes a main portion and a first branch portion. The first branch portion is disposed between the first transistor and the second transistor. An electrophoretic display including the pixel structure is also disclosed herein. | 11-24-2011 |
20110286077 | DISPLAY DEVICE - A display device includes a display panel, a barrier layer, and a sealant. The display panel includes a backplane and a frontplane disposed on the backplane, wherein the frontplane includes a plurality of frontplane sidewalls. The frontplane sidewalls at least include a first frontplane sidewall and a second frontplane sidewall, forming a frontplane concavity. The barrier layer includes a first barrier layer sidewall and a second barrier layer sidewall, wherein the first barrier layer sidewall and the second barrier layer sidewall form a barrier layer concavity. The barrier layer concavity corresponds to the frontplane concavity, and at least one of the barrier layer concavity and the frontplane concavity does not include a right angle. The sealant is disposed in a sealant accommodating space defined by the frontplane sidewalls of the frontplane, an inner surface of the backplane and an inner surface of the barrier layer. | 11-24-2011 |
20120268442 | ELECTROPHORETIC DISPLAY APPARATUS AND IMAGE-UPDATING METHOD THEREOF - An electrophoretic display apparatus and an image-updating method thereof are provided. The electrophoretic display apparatus comprises a display panel and a source driver. The display panel comprises a plurality of pixels and a plurality of source lines, and each pixel electrode is electrically coupled to an AC common voltage through a corresponding capacitor. The capacitor comprises a plurality of charged particles. The source driver comprises a first data-latching circuit and a second data-latching circuit. Each of the data-latching circuits comprises a transistor, a capacitor and an inverter. The first data-latching circuit receives image data and a data shift-register output pulse. The second data-latching circuit is electrically coupled between an output terminal of the first data-latching circuit and a source line and is used for receiving a data output pulse. | 10-25-2012 |
Shen-Yi Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100238386 | Display panel and method of repairing bright point thereof - A display panel has a portion of a color filter or patterned color layer with a thickness of at least half of the cell gap of the display panel, wherein the repair method includes providing a energy light beam to the portion of the color filter or the patterned color layer in the sub-pixel region with a bright point defect to make the portion of the color filter or patterned color layer have porous structure so that bright point is repaired to become a grey point or a dark point | 09-23-2010 |
20130242240 | DISPLAY PANEL - A display panel has a portion of a color filter or patterned color layer with a thickness of at least half of the cell gap of the display panel, wherein the repair method includes providing a energy light beam to the portion of the color filter or the patterned color layer in the sub-pixel region with a bright point defect to make the portion of the color filter or patterned color layer have porous structure so that bright point is repaired to become a grey point or a dark point. | 09-19-2013 |
Shih-Lang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110000305 | Stress Sensor and Assembly Method Thereof - A stress sensor includes a circuit board having a stress sensitive structure, a pointing stick and a metallic back plate. The stress sensitive structure includes a stress deformation region and multiple resistors located on the stress deformation region. The pointing stick is disposed on a top of the circuit board and connected to the stress sensitive structure. The metallic back plate includes at least one fixing material coating region, and thus the fixing edges of the circuit board are fixed on the corresponding fixing material coating region. An assembly method for the stress sensor is also provided. | 01-06-2011 |
Shih-Shiung Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080310761 | Image Process Method and Apparatus for Image Enlargement and Enhancement - An image processing device includes an image acquisition module, a memory module, and an image signal processing module, for performing an image enlargement and enhancement. The image acquisition module sequentially reads in an image block, including a unit pixel matrix and an exterior pixel matrix, wherein each pixel matrix includes a plurality of pixels and each pixel is associated with a parameter. The memory module stores a plurality of predefined edge patterns. The image signal processing module compares a loaded image block with predefined edge patterns, and determines if it is an edge block. Then, the image signal processing module further classifies its pixels into two groups, and calculates a continuous separating boundary between the two groups. Finally, the image signal processing module enlarges an edge block by placing new pixels inside its unit pixel matrix, wherein the new pixel parameters are extrapolated from the two classified pixel groups to maintain a sharp edge boundary. For those that are not edge blocks, interpolations are performed by the image signal processing module to derive smooth enlargements. | 12-18-2008 |
Shu-Hui Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080230798 | ACTIVE MATRIX ORGANIC ELECTROLUMINESCENT SUBSTRATE AND METHOD OF MAKING THE SAME - An active matrix organic electroluminescent substrate includes a substrate having a controlling element region and a luminescent region, a thin film transistor, a first passivation layer, a conductive layer electrically connected to the thin film transistor, and a second passivation layer disposed on the first passivation layer and the conductive layer. The second passivation layer has an opening partially exposing the conductive layer, and a step-shaped structure located between the controlling element region and the luminescent region. | 09-25-2008 |
20110148780 | TOUCH PANEL AND FABRICATING METHOD THEREOF - A method of fabricating touch panel includes the following steps. A base is provided. A first transparent conductive layer is formed on the base. A first screen printing process is performed to form a first patterned sacrificial layer on the first transparent conductive layer, and the first patterned sacrificial layer is used to pattern the first transparent conductive layer to form a patterned sensing pad layer. A second screen printing process is carried out to form a patterned insulating layer. A second transparent conductive layer is formed on the base. A third screen printing process is performed to form a second patterned sacrificial layer, and the second patterned sacrificial layer is used to pattern the second transparent conductive layer to form a patterned bridge line layer. | 06-23-2011 |
Shun-Tien Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090237385 | Display Apparatus and Power Control Circuit thereof - In a display apparatus and a power control circuit thereof, the power control circuit includes an image signal input terminal, a resistor-capacitor (RC) filter and a switch. The image signal input terminal is configured for receiving an image signal and providing a waiting-for-processing signal corresponding to the image signal. The RC filter is configured for receiving the waiting-for-processing signal and filtering out an alternating-current (AC) component of the waiting-for-processing signal to generate a switch control signal. The switch is electrically connected between a power supply and an electronic element, and configured for receiving the switch control signal and making the switch control signal control on-off state of the switch. | 09-24-2009 |
Soon Kang Huang, Hsin Chu TW
Patent application number | Description | Published |
---|---|---|
20080293339 | Retainer Ring - A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer. | 11-27-2008 |
20100112912 | Retainer Ring - A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer. | 05-06-2010 |
20100187444 | FIELD-BY-FIELD LASER ANNEALING AND FEED FORWARD PROCESS CONTROL - A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area. | 07-29-2010 |
20100277850 | Multi-Zone Electrostatic Chuck and Chucking Method - A method for processing a semiconductor wafer comprises measuring data indicating an amount of warpage of the wafer. At least two different voltages are determined, based on the amount of warpage. The voltages are to be applied to respective portions of the wafer by an electrostatic chuck that is to hold the wafer. The at least two different voltages are applied to hold the respective portions of the wafer while performing a fabrication process on the wafer. | 11-04-2010 |
20100291840 | SYSTEM AND METHOD FOR CONDITIONING CHEMICAL MECHANICAL POLISHING APPARATUS USING MULTIPLE CONDITIONING DISKS - A chemical mechanical polishing (CMP) apparatus provides for polishing semiconductor wafers and for conditioning the polishing pad of the CMP apparatus using multiple conditioning disks at the same time. The conditioning disks may be moved together or independently along the surface of polishing pad to condition the entire surface of the rotating polishing pad. | 11-18-2010 |
20130210173 | Multiple Zone Temperature Control for CMP - To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed. | 08-15-2013 |
20130210323 | CMP Pad Cleaning Apparatus - The present disclosure relates to a two-phase cleaning element that enhances polishing pad cleaning so as to prevent wafer scratches and contamination in chemical mechanical polishing (CMP) processes. In some embodiments, the two-phase pad cleaning element comprises a first cleaning element and a second cleaning element configured to successively operate upon a section of a CMP polishing pad. The first cleaning element comprises a megasonic cleaning jet configured to utilize cavitation energy to dislodge particles embedded in the CMP polishing pad without damaging the surface of the polishing pad. The second cleaning element is configured to apply a high pressure mist, comprising two fluids, to remove by-products from the CMP polishing pad. By using megasonic cleaning to dislodge embedded particles a two-fluid mist to flush away by-products (e.g., including the dislodged embedded particles), the two-phase pad cleaning element enhances polishing pad cleaning. | 08-15-2013 |
20130217306 | CMP Groove Depth and Conditioning Disk Monitoring - Some embodiments relate to a chemical mechanical polishing (CMP) system. The CMP system includes a polishing pad having a polishing surface, and a wafer carrier to retain a wafer proximate to the polishing surface during polishing. A motor assembly rotates the polishing pad and concurrently rotates the wafer during polishing of the wafer. A conditioning disk has a conditioning surface that is in frictional engagement with the polishing surface during polishing. A torque measurement element measures a torque exerted by the motor assembly during polishing. A condition surface analyzer determines a surface condition of the conditioning surface or the polishing surface based on the measured torque. Other systems and methods are also disclosed. | 08-22-2013 |
20140159243 | Metal Conductor Chemical Mechanical Polish - The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment. | 06-12-2014 |
20140220863 | HIGH THROUGHPUT CMP PLATFORM - A chemical-mechanical polishing system has a first polishing apparatus configured to perform a first chemical-mechanical polish on a workpiece and a second polishing apparatus configured to perform a second chemical-mechanical polish on the workpiece. A rework polishing apparatus comprising a rework platen and a rework CMP head is configured to perform an auxiliary chemical-mechanical polish on the workpiece when the workpiece is positioned on the rework platen. A measurement apparatus measures one or more parameters of the workpiece, and a transport apparatus transports the workpiece between the first polishing apparatus, second polishing apparatus, rework polishing apparatus, and measurement apparatus. A controller determines a selective transport of the workpiece to the rework polishing apparatus by the transport apparatus only when the one or more parameters are unsatisfactory. | 08-07-2014 |
Tai-Chun Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080290420 | SiGe or SiC layer on STI sidewalls - A semiconductor structure includes a semiconductor substrate; an opening in the semiconductor substrate; a semiconductor layer in the opening and covering a bottom and sidewalls of the opening, wherein the semiconductor layer and the semiconductor substrate comprise different materials; and a dielectric material over the semiconductor layer and filling a remaining portion of the opening. | 11-27-2008 |
20090061586 | Strained Channel Transistor - A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped. | 03-05-2009 |
20100151648 | Strained Channel Transistor - A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped. | 06-17-2010 |
20130052837 | Apparatus and Methods for Annealing Wafers - A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region. | 02-28-2013 |
20130130184 | Apparatus and Method for Controlling Wafer Temperature - A wafer temperature control apparatus comprises a first temperature sensor and a second temperature sensor. The first temperature sensor is configured to receive a first temperature signal from a center portion of a backside of a susceptor. The second temperature sensor is configured to receive a second temperature signal from an edge portion of the susceptor. A plurality of controllers are configured to adjust each heating source's output based upon the first temperature signal and the second temperature signal. | 05-23-2013 |
20130221448 | FIN PROFILE STRUCTURE AND METHOD OF MAKING SAME - A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin. | 08-29-2013 |
20130241079 | NOVEL CONDUCTOR LAYOUT TECHNIQUE TO REDUCE STRESS-INDUCED VOID FORMATIONS - A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device. | 09-19-2013 |
20130277760 | Dummy FinFET Structure and Method of Making Same - A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET. | 10-24-2013 |
20130302975 | Fin Profile Structure and Method of Making Same - A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin. | 11-14-2013 |
20140231919 | Fin Deformation Modulation - A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively. | 08-21-2014 |
20140264491 | Semiconductor Strips with Undercuts and Methods for Forming the Same - An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip. | 09-18-2014 |
20150014790 | Fin Deformation Modulation - A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively. | 01-15-2015 |
Ta-Jen Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100123851 | Backlight Module and Display Device Using the Same - The present disclosure is a backlight module including a light guide plate, a supporter, and a light source module. The light guide plate has a light incident side. The supporter has a bottom plate, a sidewall, and a top plate corresponding to the bottom plate. The bottom plate extends from a first end of the sidewall toward the light guide plate, and the top plate extends along a second end of the sidewall toward the light guide plate. The length of the sidewall is longer than the length of the top plate, such that the top plate corresponding to the sidewall forms at least one breach to expose the second end of the sidewall. The bottom plate, the top plate, and the sidewall together form an accommodating space, and the light incident side of the light guide plate is disposed between the top plate and the bottom plate. The light source module is disposed in the accommodating space and partially exposed through the at least one breach. The light source module has at least one light emitting unit and a printed circuit board. The light emitting unit is disposed on the printed circuit board, such that an emitting surface of the light emitting unit can face the light incident side of the light guide plate. | 05-20-2010 |
20120113351 | BACKLIGHT MODULE - A backlight module is disclosed, which includes an outer frame having a sidewall and a hole formed on the sidewall, an inner frame disposed inside of the outer frame, and an adhesive device. The inner frame includes a block wall and a support. The block wall has an inner surface, an outer surface, and a rework section. The outer surface is in contact with the sidewall, and the rework section is disposed corresponding to the hole. The adhesive device is disposed on the support. | 05-10-2012 |
20120147626 | BACKLIGHT MODULE - The backlight module includes a holder having a holder sidewall, a light source disposed on the holder, a light guide plate, and a frame. An end of the light guide plated is fixed on the holder. The frame has a frame sidewall. The holder is assembled on the frame, wherein a gap is formed between the holder sidewall and the frame sidewall, and the gap is utilized as a buffer space of the deformation of the light guide plate. | 06-14-2012 |
20120300428 | Backlight Module - A backlight module is disclosed. The backlight module includes a light guide plate, a backlight source, an optical plate, and an optical coating layer. The light guide plate has a light emitting surface and a light incident end. The light incident end is located at an adjacent side of the light emitting surface. The backlight source is disposed corresponding to the light incident end and generates lights emitting to the light incident end. The optical plate is disposed above the light emitting surface. The optical plate includes an extension portion extending disposed above the backlight source. The optical coating layer is formed on a surface of the extension portion. | 11-29-2012 |
20130033891 | BACKLIGHT MODULE AND DISPLAY DEVICE USING THE SAME - An exemplary backlight module includes a frame, a light guide plate, a light source module and an optical film. The light guide plate is arranged on the frame and includes a light-incident surface and a light-emitting surface adjacent to the light-incident surface. The light source module includes a circuit board arranged between the frame and the light guide plate board, and a light emitting element arranged on the circuit board and facing the light-incident surface. The optical film includes a wavelength shifting portion arranged between the light emitting element and the light guide plate, a second extending portion arranged between the light guide plate and the frame, and a first extending portion connected between the wavelength shifting portion and the second extending portion and arranged between the light guide plate and the circuit board. A display device equipped with the backlight module is also provided. | 02-07-2013 |
20140078443 | BACKLIGHT MODULE - A backlight module is disclosed, which includes an outer frame having a sidewall and a hole formed on the sidewall, an inner frame disposed inside of the outer frame, and an adhesive device. The inner frame includes a block wall and a support. The block wall has an inner surface, an outer surface, and a breakable section. The outer surface is in contact with the sidewall, and the breakable section is disposed corresponding to the hole. The adhesive device is disposed on the support. | 03-20-2014 |
Te-Chun Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090289259 | PIXEL STRUCTURE OF DISPLAY PANEL AND METHOD OF MAKING THE SAME - A pixel structure of a display panel is provided. The pixel structure includes a first storage capacitor formed by a pixel electrode and a common electrode pattern, and a second storage capacitor formed by an electrode pattern and the common electrode pattern. Accordingly, the storage capacitance is greatly improved without sacrificing the aperture ratio, or the aperture ratio is improved by reducing the area of the storage capacitor while the storage capacitance is maintained. | 11-26-2009 |
20130168704 | Panel and method for fabricating the same - A panel is disclosed, in which, a patterned semiconductor layer is formed on an insulation layer. The patterned semiconductor layer includes a portion corresponding to an electrode and another portion corresponding to a wiring trace. The portion corresponding to the electrode may be formed as, for example, a channel, and the other portion corresponding to the wiring trace may protect the wiring trace during fabrication process or in the structure from scratching or corrosion. | 07-04-2013 |
20130168707 | ARRAY SUBSTRATE STRUCTURE OF DISPLAY PANEL AND METHOD OF MAKING THE SAME - An array substrate structure of a display panel includes a substrate, a plurality of first wirings, a first patterned insulating layer, a plurality of second wirings, a plurality of first protective patterns, and a plurality of second protective patterns. The substrate has a wiring region. The first wirings are disposed in the wiring region. The first patterned insulating layer is disposed on the first wirings. The second wirings are disposed on the first patterned insulating layer. The first protective patterns are disposed in the wiring region and disposed on the corresponding second wiring, respectively, where the first protective pattern includes a semiconductor material. The second protective patterns are disposed on the corresponding first protective pattern, respectively, where the second protective pattern includes an inorganic insulating material. | 07-04-2013 |
Tien-Chun Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090021665 | Active array substrate for flat panel display - An active array substrate for a flat panel display is disclosed. The active array substrate includes a substrate, a plurality of first conductive lines, a plurality of second conductive lines, a plurality of first repair lines, a plurality of second repair lines, a plurality of third repair lines. The substrate has a display area. The first repair lines cross and are electrically separated from the second conductive lines. The second repair lines cross and are electrically separated from the second conductive lines. Each of the third repair lines is in electrical connection respectively with one of the first repair lines and one of the second repair lines. The second conductive lines are divided into a plurality of second conductive line groups and each of the second conductive line groups respectively corresponds to one of the third repair lines. | 01-22-2009 |
Tzu-Tse Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090196040 | Light source module of projector - A light source module adapted to a projecting device including a light bulb, a fan, and an air tunnel structure is provided. The fan is located by the light bulb for cooling the light bulb. The air tunnel structure is located respective to the location of the light bulb, for removing the heat generated by the light bulb. The air tunnel structure has a curved inner wall, a plurality of fins, and a tank. The curved inner wall is located inside the air tunnel structure respective to the location of the light bulb. The fins are formed on the curved inner wall for blocking the fragments generated by the explosion of the light bulb. The tank is located by a side of the curved inner wall for carrying the fragments clashing the fins. | 08-06-2009 |
20090219492 | DETECTING DEVICE - A detection device is mounted in a projector for detecting relations between an object and the projector. The detection device includes a detecting switch, a connector and a detecting circuit. When the object is placed into the detecting switch, the detecting switch is in an off state. When the object is withdrawn from the detecting switch, the detecting switch is in an on state. The connector is electrically connected to the detecting switch. The detecting circuit is electrically connected to the connector for activating the projector to be operated in a first mode in response to the off state of the detecting switch and activating the projector to be operated in a second mode in response to the on state of the detecting switch. The first mode and the second mode are associated with the temperature inside the projector. | 09-03-2009 |
20130003027 | PROJECTION APPARATUS AND LIGHT SOURCE ADJUSTING METHOD THEREOF - A projection apparatus including a digital micro mirror device (DMD), a light source, a lens, a photoelectric conversion device, a decision device and an adjustment module is provided. When the DMD is switched to a first operating state, the DMD reflects a light beam emitted by the light source to the lens. When the DMD is switched to a second operating state, the DMD reflects the light beam to the photoelectric conversion device. The photoelectric conversion device generates a signal value according to a light intensity of the light beam. The decision device compares the signal value with a predetermined value. When the signal value is smaller than the predetermined value, the decision device generates a driving signal value. The driving signal value is used for driving the adjustment module to sequentially adjust a position of the light source along a plurality of axes. | 01-03-2013 |
Wan-Ting Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100315353 | Flexible Touch Display Apparatus - A flexible touch display apparatus includes a flexible substrate, a display unit, a flexible insulation layer and a touch sensor layer. The display unit is disposed on the flexible substrate, the flexible insulation layer is disposed on the display unit, and the touch sensor layer is formed on the flexible insulation layer. The flexible touch display apparatus is light in weight, thin in thickness, flexible and unbreakable. | 12-16-2010 |
Wei-Hao Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090237947 | LAMP POSITION ADJUSTMENT DEVICE AND LAMP MODULE HAVING THE SAME - A lamp position adjustment device includes a bottom frame, a lamp holder, and a lamp mount. The lamp holder is disposed on the bottom frame for supporting the lamp, and the lamp mount is disposed between the lamp holder and the bottom frame. The lamp mount includes a base portion, a first side portion and a second side portion that are respectively connected to two opposite sides of the base portion, a first positioning mechanism, and a second positioning mechanism. The first positioning mechanism is disposed on the base portion to enable the lamp mount to be slidably connected to the bottom frame, and the second positioning mechanism is disposed on the first side portion and the second side portion to enable the lamp mount to be slidably connected to the lamp holder. | 09-24-2009 |
Wei-Kai Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100201903 | FLAT DISPLAY PANEL AND METHOD OF REPAIRING CONDUCTIVE LINES THEREOF - A flat display panel includes a plurality of bridge lines disposed between adjacent common lines. When a short defect occurs, the common line near the short defect can be directly cut off in order to repair the short defect and the common voltage can be transferred through the bridge lines to maintain the normal operation of the flat display panel. | 08-12-2010 |
20120026444 | LIQUID CRYSTAL DISPLAY PANEL, PIXEL ARRAY SUBSTRATE AND PIXEL STRUCTURE THEREOF - A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor. | 02-02-2012 |
20120026447 | LIQUID CRYSTAL DISPLAY PANEL, PIXEL ARRAY SUBSTRATE AND PIXEL STRUCTURE THEREOF - A pixel structure includes at least one first sub-pixel electrode, at least one second sub-pixel electrode, at least one common line, at least one first transistor electrically connected to the first sub-pixel electrode, and at least one second transistor electrically connected to the second sub-pixel electrode. The common line overlaps and is coupled respectively with the first sub-pixel electrode and the second sub-pixel electrode so as to respectively form a first storage capacitor and a second storage capacitor. The second storage capacitor is larger than the first storage capacitor. A first adjusting capacitor of the first transistor is larger than a second adjusting capacitor of the second transistor. | 02-02-2012 |
20120200819 | FLAT DISPLAY PANEL AND METHOD OF REPAIRING THE SAME - A flat display panel includes a bridge line disposed between adjacent common lines. When a short defect occurs, the common line near the short defect can be directly cut off in order to repair the short defect and the common voltage can be transferred through the bridge line to maintain the normal operation of the flat display panel. | 08-09-2012 |
Wei-Pang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100171905 | TRANSFLECTIVE DISPLAY PANEL - A transflective display panel includes a first substrate, a plurality of electroluminescent (EL) elements disposed on the first substrate, a plurality of reflectors disposed on the first substrate, a second substrate disposed opposite to the first substrate, a plurality of transparent electrodes disposed on a side of the second substrate opposite to the first substrate, a plurality of color filter layers disposed on a side of the second substrate opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. Accordingly, a problem of insufficient contrast ratio of the transflective display panel can be solved, when the ambient light is too high. | 07-08-2010 |
Wen-Chiang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110080383 | Display panel with optimum pad layout of the gate driver - A display panel includes a display area, a first bonding area, and a second bonding area. The second bonding area is used for bonding with a gate driver. The second bonding area includes a plurality of input pads and a plurality of output pads. The plurality of input pads is disposed on the two sides of the second bonding area in the first direction and on the two sides of the second bonding area only the plurality of input pads is disposed in the second direction. The plurality of output pads is disposed on the center region of the second bonding area in the first direction and on the center region of the second bonding area only the plurality of output pads is disposed in the second direction. | 04-07-2011 |
20110273226 | GATE DRIVING CIRCUIT - An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled. | 11-10-2011 |
20140062986 | DRIVING CIRCUIT CHIP AND DRIVING METHOD FOR DISPLAY - A driving method for a display apparatus used in a driving circuit chip, includes: receiving first and second voltages; outputting the first and second voltages to a first input-stage circuit of a first amplifier and a second input-stage circuit of a second amplifier, respectively, in a first period; outputting the first and second voltages to the second input-stage circuit and the first input-stage circuit, respectively, in a second period; receiving a third voltage outputted from the first input-stage circuit and a fourth voltage outputted from the second input-stage circuit; outputting the third and fourth voltages to the first and second output-stage circuits, respectively, in the first period; and outputting the third and fourth voltages to the second and first output-stage circuits, respectively, in the second period. A driving circuit chip is also provided. | 03-06-2014 |
Wen-Ruei Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090213339 | Projector and optical engine thereof - An optical engine includes a light source system for providing an incident light beam, a reflective light valve, a first case, a projection lens and a second case. The reflective light valve is disposed in the first case for receiving the incident light beam, reflecting and outputting an image light beam or a dumped light beam. The first case provides a first opening located in the light path of the dumped light beam. The projection lens is connected to the first case for receiving and projecting the image light beam to form an image. The second case intercommunicates with the first case via the first opening. The dumped light beam enters the second case through the first opening, and is reflected twice or more inside the second case. Moreover, the inner wall of the second case applies to absorb the energy of the dumped light beam. | 08-27-2009 |
Wen-Sheh Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110171795 | FinFET LDD and Source Drain Implant Technique - A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region. | 07-14-2011 |
20120267626 | Transmission Line Characterization Using EM Calibration - A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length. | 10-25-2012 |
Yao-Te Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100240215 | Multi-Sacrificial Layer and Method - MEMS devices and methods for utilizing sacrificial layers are provided. An embodiment comprises forming a first sacrificial layer and a second sacrificial layer over a substrate, wherein the second sacrificial layer acts as an adhesion layer. Once formed, the first sacrificial layer and the second sacrificial layer are patterned such that the second sacrificial layer is undercut to form a step between the first sacrificial layer and the second sacrificial layer. A top capacitor electrode is formed over the second sacrificial layer, and the first sacrificial layer and the second sacrificial layer are removed in order to free the top capacitor electrode. | 09-23-2010 |
20130277770 | MEMS Devices and Methods of Forming the Same - A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug. | 10-24-2013 |
20140042625 | BONDING LAYER STRUCTURE AND METHOD FOR WAFER TO WAFER BONDING - A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate. | 02-13-2014 |
20140220735 | Method and Apparatus for a Wafer Seal Ring - A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer. The wafer having the wafer seal ring formed thereon may be bonded to a wafer that may not have a wafer seal ring. A pair of wafers may be formed with respective wafer seal rings formed in a corresponding manner. The pair of wafers may be bonded together with the wafer seal rings aligned and bonded together to form a seal ring structure between the bonded wafers. | 08-07-2014 |
20150031159 | MEMS Devices and Methods of Forming the Same - A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug. | 01-29-2015 |
Yen-Chang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20100135003 | Backlight Module and Liquid Crystal Display Module Using the Backlight Module - This present invention discloses a backlight module and a flat display device using the backlight module. The backlight module has a plastic base having a plastic plate and a plastic frame, wherein a light guide plate is disposed on the plastic plate. The plastic plate is light reflective and has a thickness ranging from 0.2 mm to 0.9 mm. The plastic plate is used to reflect light leaking from the light guide plate. The reflectivity of the plastic plate to the visible light with wavelength ranging from 410 nm to 780 nm ranges from 80% to 95%. | 06-03-2010 |
20100165658 | Light Guide Plate Having Lateral Optical Structures and Backlight Module Having the Light Guide Plate - The present invention discloses a light guide plate and a backlight module having the same. The light guide plate includes a light emitting surface, a light incident surface, a light reflecting surface, and a plurality of prisms disposed on the light reflecting surface. The disposition direction of the prisms can be parallel or perpendicular to the lengthwise direction of the light reflecting surface. An inclined angle may exist between the disposition direction of the prisms and the lengthwise of the light reflecting surface. The backlight module includes a light guide plate, a light source, and an optical film set, wherein the light source is disposed near the light incident surface. The optical film set partially covers the light emitting surface, wherein a distance exists between a vertex of the prism and an edge of the optical film set. | 07-01-2010 |
Yen-Chen Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090184656 | BACKLIGHT SYSTEM HAVING A LAMP CURRENT BALANCE AND FEEDBACK MECHANISM AND RELATED METHOD THEREOF - A lamp current balance and feedback system and related method are disclosed for balancing the input and output currents of a lamp by making use of a lamp current balance and feedback mechanism. The operation of the lamp current balance and feedback mechanism includes coupling the input current of the lamp for generating a first balance current by a first transformer, coupling the output current of the lamp for generating a second balance current by a second transformer, coupling the first and second transformers for substantially equalizing the first and second balance currents, generating a feedback signal based on the first or second balance current by a feedback circuit, generating a pulse width modulation signal based on the feedback signal by a pulse width modulation signal generation circuit, and driving the input and output currents of the lamp based on the pulse width modulation signal by a driving circuit. | 07-23-2009 |
Yen-Liang Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110157071 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of floating gate type ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each floating gate type ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
20110157084 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of diode ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each diode ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
Yi-Chen Huang, Hsin Chu TW
Patent application number | Description | Published |
---|---|---|
20080308899 | TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16. | 12-18-2008 |
20130181262 | Performing Treatment on Stressors - A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region. | 07-18-2013 |
Yi-Chih Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20090153791 | Chip on film structure - The chip on film structure for a liquid crystal display is disclosed. The chip on film structure includes a film substrate, a driver chip disposed on the film substrate, a plurality of the input pad, and a plurality of output pads. The input pads and the output pads are disposed on two opposite sides of the driver chip, and are electrically connect to the driver chip respectively. Each input pad comprises an extending portion extending from the input pads to a first cutting edge respectively, and a width of the extending portion is thinner than a width of the input pad, and the extending portions are cut along the first cutting edge. | 06-18-2009 |
Zi-Long Huang, Hsin Chu TW
Patent application number | Description | Published |
---|---|---|
20110068831 | LOW POWER LINE DRIVER AND METHOD THEREOF - A line driver for a communications system requiring multiple power sources for different modes of operation comprises a current source and a voltage source coupled in parallel with the current source. The current source has a first terminal and a second terminal. The line driver further comprises a first source resistor coupled to the first terminal of the current source and a second source resistor coupled to the second terminal of the current source. The current source provides a driving current and the voltage source provides a driving voltage at the same time during operations of the communications system. | 03-24-2011 |
20110075741 | MULTIMODE ETHERNET LINE DRIVER - A multimode line driver circuit is provided. The multimode line driver circuit has a first driver circuit for receiving a first differential input signal and transmitting a first differential output signal, and a second driver circuit for receiving a second driver circuit for receiving a second differential input signal and transmitting a second differential output signal. The multimode line driver circuit also has a first switch coupling the first driver circuit to a first power supply and a second switch coupling the second driver circuit to a second power supply. The multimode line driver circuit also has a transformer coupled to the output interface for transforming the first differential output and the second differential output and a mode controller configured to close the first switch in the first mode and to close the second switch in the second mode. | 03-31-2011 |
20110163807 | IMPEDANCE MATCHING CIRCUIT AND METHOD THEREOF - A circuit comprises an amplifier circuit and a trimming circuit. The amplifier circuit includes an operational amplifier. The operational amplifier has a first input configured to receive input signals, and the operational amplifier also has a second input and an amplifier output. One of the first input or the second input is a negative input. The trimming circuit is coupled to the amplifier output. The trimming circuit includes a termination resistor coupled in parallel with at least one trimming resistor. The termination resistor is coupled to a first switch in series, and the trimming resistor is coupled to a second switch in series. The amplifier output is connected back to the negative input through the first switch. | 07-07-2011 |