Patent application number | Description | Published |
20100283518 | DELAY APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay apparatus of a semiconductor integrated circuit includes a control signal generating unit configured to generate a block control signal and a unit control signal in response to a delay control signal; a plurality of delay blocks, connected in series to each other, and configured to generate a delay clock signal by delaying an input clock signal, wherein each of the delay blocks includes a predetermined number of unit delayers, and the plurality of the delay blocks are configured to be selectively activated in response to the block control signal; and a minute delay unit including a predetermined number of unit delayers and configured to generate an output clock signal by delaying the delay clock signal by adjusting an activation number of the provided unit delayers in response to the unit control signal. | 11-11-2010 |
20100290306 | CIRCUIT AND METHOD FOR SHIFTING ADDRESS - A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands. | 11-18-2010 |
20110102006 | CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS - A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV. | 05-05-2011 |
20110102065 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal. | 05-05-2011 |
20110102066 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips. | 05-05-2011 |
20110103156 | DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response to a chip selection signal, and outputs data to a connected rank or receives data from the connected rank. The data input/output section outputs the data transmitted from the rank selecting section through a data pad to an external device during a read operation, and outputs the data inputted to the data pad to the rank selecting section during a write operation. | 05-05-2011 |
20110188324 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal. | 08-04-2011 |
20120154008 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include a master chip, first to n | 06-21-2012 |
20120176849 | SEMICONDUCTOR APPARATUS AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips. | 07-12-2012 |
20120194243 | SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF - A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals. | 08-02-2012 |
Patent application number | Description | Published |
20110103167 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation. | 05-05-2011 |
20110128039 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal. | 06-02-2011 |
20110156736 | SEMICONDUCTOR APPARATUS AND PROBE TEST METHOD THEREOF - Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes. | 06-30-2011 |
20110169542 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DELAYING - A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal. | 07-14-2011 |
20110187444 | VOLTAGE TRIMMING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A voltage trimming circuit of a semiconductor memory apparatus may include a first voltage generation block configured to select voltage levels of a first node and a second node and divide a voltage between the first node and the second node to generate a first division voltage group; a second voltage generation block configured to select voltage levels of a third node and a fourth node and divide a voltage between the third node and the fourth node to generate a second division voltage group; a first switch block configured to select one division voltage of the first division voltage group to output the selected division voltage as a first reference voltage; and a second switch block configured to select one division voltage of the second division voltage group to output the selected division voltage as a second reference voltage. | 08-04-2011 |
20110188331 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having a plurality of chips stacked therein is disclosed. At least two of the plurality of chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two of the plurality of chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips. | 08-04-2011 |
20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 08-25-2011 |
20110211406 | ADDRESS DELAY CIRCUIT - An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address. | 09-01-2011 |
20110242928 | ADDRESS DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses. | 10-06-2011 |
20110292707 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines. | 12-01-2011 |
20120119764 | TEST MODE CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS AND CONTROL METHOD THEREOF - Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block. | 05-17-2012 |