Patent application number | Description | Published |
20130113075 | METAL-INSULATOR-METAL CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided. | 05-09-2013 |
20130200519 | Through silicon via structure and method of fabricating the same - The present invention relates to a method of fabricating a through silicon via (TSV) structure, in which, a dielectric layer is disposed to cover surface of each of a device region of a substrate and a sidewall and a bottom of a via hole in a TSV region of the substrate, and the via hole having the dielectric layer covering the sidewall and the bottom is filled with a conductive material. The present invention also relates to a TSV structure, in which, a dielectric layer disposed in the device region of a substrate extends to the via hole in a TSV region of the substrate to cover surface of the sidewall of the via hole to serve as a dielectric liner, and a conductive material is filled into the via hole having the dielectric layer covering the sidewall. | 08-08-2013 |
20140357050 | METHOD OF FORMING ISOLATING STRUCTURE AND THROUGH SILICON VIA - A method of forming an isolation structure and a through silicon via includes the following steps. First, at least a first trench and at least a second trench are formed in the substrate by a single etch step. Then, an insulating layer is formed to simultaneously fill up the first trench and cover a sidewall and a bottom of the second trench. After that, a conductive layer is formed to fill in the second trench. Subsequently, the insulating layer and the conductive layer on a front side of the substrate are removed. Later, a back side of the substrate is thinned to expose the conductive layer in the second trench. The insulating layer in the first trench serves as an insulating filling, and the insulating layer on the sidewall of the second trench serves as a liner of the through silicon via. | 12-04-2014 |
20150050751 | METHOD OF CONTROLLING THRESHOLD VOLTAGE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer. | 02-19-2015 |
20150140778 | METHOD FOR MANUFACTURING METAL-INSULATOR-METAL CAPACITOR STRUCTURE - A method for manufacturing the MIM capacitor structure is provided. A first damascene electrode layer is formed in the first opening formed in a first dielectric layer. An insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. A second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. The insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. A second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer. | 05-21-2015 |
Patent application number | Description | Published |
20110221041 | Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die - A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. | 09-15-2011 |
20110221055 | Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. | 09-15-2011 |
20110221057 | Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. | 09-15-2011 |
20120018874 | Semiconductor Device and Method of Forming RDL over Contact Pad with High Alignment Tolerance or Reduced Interconnect Pitch - A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers. | 01-26-2012 |
20120018904 | Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis - A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer. | 01-26-2012 |
20120074534 | Semiconductor Device and Method of Forming Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. | 03-29-2012 |
20120112340 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 05-10-2012 |
20120199965 | Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. | 08-09-2012 |
20130056879 | Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. | 03-07-2013 |
20130075936 | Semiconductor Device and Method of Forming Interconnect Substration for FO-WLCSP - A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement. | 03-28-2013 |
20130113092 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 05-09-2013 |
20130175696 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 07-11-2013 |
20130249111 | Semiconductor Device and Method of Forming RDL Wider than Contact Pad Along First Axis and Narrower than Contact Pad along Second Axis - A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer. | 09-26-2013 |
20140084424 | Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. | 03-27-2014 |
20140246779 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 09-04-2014 |
20140252654 | Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. | 09-11-2014 |
20150155248 | Semiconductor Device and Method of Forming Repassivation Layer for Robust Low Cost Fan-Out Semiconductor Package - A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief. | 06-04-2015 |
Patent application number | Description | Published |
20090108052 | Selective soldering using fiber optic device - A fiber optic device for enabling soldering is described. The fiber optic device includes an entry portion comprising an optical fiber bundle for receiving a single light beam wherein the optical fiber bundle splits the light beam into a plurality of separate portions, each of the separate portions for enabling soldering. The fiber optic device further includes an exit portion for emitting each of the plurality of separate portions of the light beam in a pattern to enable soldering at a plurality of locations simultaneously utilizing the single light beam. | 04-30-2009 |
20090127341 | Bar-code reading tool - A bar-code-reading tool. A first mirror is disposed to receive light emitted by a bar-code reader. A second mirror is disposed to receive light reflected from a bar-code label affixed to an object. The first mirror and the second mirror are arranged in a folded optical path that is disposed for the bar-code reader to read the bar-code label. A fixture holds the object comprising the bar-code label on a planar base of the fixture and disposes the bar-code label in the folded optical path. The fixture is arranged so that the object is disposed above the planar base, and the bar-code reader is disposed below the planar base. | 05-21-2009 |
20090300899 | SEAL ATTACH PRESS TOOL - A press tool and method for attaching a seal to a surface are described. The seal attach press tool comprises a contact member having a curved contact surface, e.g., an arced surface. In a process of attaching a seal over an opening on a surface, the curved contact surface of the contact member is rolled over and in contact with the surface of the seal, thereby facilitating bonding the seal to the surface. According to an embodiment, the curved contact surface of the contact member comprises an elastomer and/or is covered with an elastomer pad. | 12-10-2009 |