Patent application number | Description | Published |
20100208381 | Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal. | 08-19-2010 |
20100208504 | Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains. | 08-19-2010 |
20100284209 | INTEGRATED CIRCUIT MEMORY SYSTEMS AND PROGRAM METHODS THEREOF INCLUDING A MAGNETIC TRACK MEMORY ARRAY USING MAGNETIC DOMAIN WALL MOVEMENT - Provided are nonvolatile memory devices and program methods thereof. an integrated circuit memory system includes a memory array comprising at least one magnetic track, each of the at least one magnetic track including a plurality of magnetic domains and at least one read/write unit coupled thereto, decoding circuitry coupled to the memory array that is operable to select at least one of the magnetic domains, a read/write controller coupled to the memory array that is operable to read data from at least one of the plurality of magnetic domains and to write data to at least one of the plurality of magnetic domains via the at least one read/write unit coupled to each of the at least one magnetic track, and a domain controller coupled to memory array that is operable to move data between the magnetic domains on each of the at least one magnetic track. | 11-11-2010 |
20100284216 | INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME - An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data. | 11-11-2010 |
20110095287 | Nonvolatile memory device and nonvolatile memory array including the same - A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer. | 04-28-2011 |