Patent application number | Description | Published |
20090140429 | Metal interconnection of a semiconductor device and method of manufacturing the same - A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove. | 06-04-2009 |
20110097891 | Method of Manufacturing the Semiconductor Device - A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface. | 04-28-2011 |
20120083097 | Methods of Forming a Semiconductor Package Using a Seed Layer and Semiconductor Packages Formed Using the Same - Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided. | 04-05-2012 |
20120214302 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part. | 08-23-2012 |
20130134603 | Semiconductor Devices Including Protected Barrier Layers - Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern. | 05-30-2013 |
20130200525 | VIA CONNECTION STRUCTURES, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS OF FABRICATING THE STRUCTURES AND DEVICES - A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure. | 08-08-2013 |
20130200526 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME - Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. | 08-08-2013 |
20130207241 | Semiconductor Devices Having Through-Vias and Methods for Fabricating the Same - The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole. | 08-15-2013 |
20130207242 | Semiconductor Devices Having Through-Vias and Methods for Fabricating the Same - Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer. | 08-15-2013 |
20130210222 | SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIA STRUCTURES AND METHODS FOR FABRICATING THE SAME - In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer. | 08-15-2013 |
20140048952 | SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA STRUCTURES AND REDISTRIBUTION STRUCTURES - Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer. | 02-20-2014 |
20140110894 | Wafer Carrier Having Cavity - A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer. | 04-24-2014 |
20140179103 | SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME - A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed. | 06-26-2014 |
20140199810 | Methods for Forming Semiconductor Devices Using Sacrificial Layers - A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer. | 07-17-2014 |
20150068948 | WAFER LOADERS HAVING BUFFER ZONES - Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone. | 03-12-2015 |
20150093896 | SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME - The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole. | 04-02-2015 |
Patent application number | Description | Published |
20120280692 | APPARATUS AND METHOD FOR MANAGING BATTERY PACK - The present invention discloses an apparatus and method for managing a battery pack, which can rapidly and accurately diagnose the coupling state of a bus bar to battery modules in the battery pack. In accordance with the present invention, provided is an apparatus for managing a battery pack having a plurality of battery modules and a bus bar coupled between the battery modules to electrically connect the battery modules, the apparatus comprising a coupling detection unit for detecting the coupling state of the bus bar to the battery modules; and a controlling unit for determining whether the coupling state of the bus bar has a defect on the basis of the coupling state detected by the coupling detection unit. | 11-08-2012 |
20120326724 | APPARATUS AND METHOD FOR ESTIMATING AVAILABLE TIME OF BATTERY - Disclosed are an apparatus and method for estimating an available time of a battery relatively accurately in consideration of a driving pattern of a user. The apparatus for estimating an available time of a battery includes a current measuring unit for measuring an output current of the battery, a SOC estimating unit for estimating SOC (State Of Charge) of the battery, and a controller for estimating an available time of the battery by using a measured current value obtained by the current measuring unit, an estimated SOC value obtained by the SOC estimating unit and an entire capacity of the battery. | 12-27-2012 |
20140009123 | APPARATUS AND METHOD FOR ESTIMATING STATE OF HEALTH OF BATTERY - The present disclosure describes an apparatus and method for estimating state of health (SOH) of a battery. The apparatus for estimating state of health of a battery includes a sensing unit for measuring a battery voltage and current within a predetermined charging voltage range; a memory unit storing the battery voltage and current values measured by the sensing unit and SOH-based ampere counting values, obtained by an ampere counting experiment of a battery whose actual degradation degree is known; and a control unit for calculating an ampere counting value by counting the measured current values stored in the memory unit within the charging voltage range, and estimating a SOH value by mapping the SOH value corresponding to the calculated ampere counting value from the SOH-based ampere counting values stored in the memory unit. | 01-09-2014 |
20140074416 | APPARATUS AND METHOD FOR ESTIMATING BATTERY STATE - Disclosed is an apparatus and method for estimating a battery state, the apparatus including a measurement unit for measuring a terminal voltage, a charging/discharging current and a current offset value of a battery, a prediction unit for predicting a state variable and an output variable according to a state equation including SOC and an overpotential of the battery as state variables and includes a terminal voltage of the battery as an output variable, a correction unit for correcting the predicted state variable, a SOC estimation unit for estimating SOC of the battery by means of the corrected state variable, and a control unit for selecting a single state variable to estimate SOC of the battery according to the measured current offset value, so that the SOC estimation unit estimates SOC of the battery by means of the selected state variable. | 03-13-2014 |
20140084851 | APPARATUS AND METHOD FOR CHARGING BATTERY - Disclosed is an apparatus (and method) for charging a battery having a voltage measuring unit for measuring a voltage, a control unit for outputting a charge control signal corresponding to an early charging mode in which the battery is charged until a voltage of the battery rises to a preset cut-off voltage (Vc) and a charge control signal corresponding to a late charging mode in which the battery is charged while lowering a charge power in phases, and a charging unit for providing a charge power corresponding to the charge control signal to the battery, wherein a point of lowering the charge power in phases is associated with a point at which the voltage of the battery reaches the cut-off voltage again by the lowered charge power. Therefore, a voltage level reached at full charge of a battery may be raised in a simple and efficient way. | 03-27-2014 |