Schroter
Charles Schroter, Los Gatos, CA US
Patent application number | Description | Published |
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20090265508 | Scheduling of Housekeeping Operations in Flash Memory Systems - A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming. | 10-22-2009 |
Charles M. Schroter, Los Gatos, CA US
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20100318720 | Multi-Bank Non-Volatile Memory System with Satellite File System - A multi-bank non-volatile memory system is presented. A first of the banks has a main copy of the file system and each of the other banks has a satellite copy of the file system. The back end firmware of the controller executes a thread for each of the banks. After the boot process, during normal memory operations, each of the threads can operate using its own copy of the file system without interrupting the other threads in order to access the file system. | 12-16-2010 |
Charles Michael Schroter, Los Gatos, CA US
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20120084489 | SYNCHRONIZED MAINTENANCE OPERATIONS IN A MULTI-BANK STORAGE SYSTEM - A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above. | 04-05-2012 |
David A. Schroter, Roundrock, TX US
Patent application number | Description | Published |
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20160092212 | DYNAMIC ISSUE MASKS FOR PROCESSOR HANG PREVENTION - Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask. | 03-31-2016 |
20160092233 | DYNAMIC ISSUE MASKS FOR PROCESSOR HANG PREVENTION - Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask. | 03-31-2016 |
David A. Schroter, Round Rock, TX US
Patent application number | Description | Published |
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20090210662 | MICROPROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR DIRECT PAGE PREFETCH IN MILLICODE CAPABLE COMPUTER SYSTEM - A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided. | 08-20-2009 |
20090217009 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS - A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value. | 08-27-2009 |
20110153991 | DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS - A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit. | 06-23-2011 |
20110154107 | TRIGGERING WORKAROUND CAPABILITIES BASED ON EVENTS ACTIVE IN A PROCESSOR PIPELINE - A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. | 06-23-2011 |
20110320782 | PROGRAM STATUS WORD DEPENDENCY HANDLING IN AN OUT OF ORDER MICROPROCESSOR DESIGN - A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data. | 12-29-2011 |
Terence Schroter, Edmonton CA
Patent application number | Description | Published |
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20100108383 | Drilling Apparatus and Method - A drilling apparatus includes an upper drill string, a lower drill string including a rotary drilling motor, an orientable rotatable connection between the drill strings, a reactive torque control device associated with the orientable rotatable connection, an orientation sensing device for providing a sensed actual orientation of the lower drill string, and a feedback control system configured to actuate the control device in response to the sensed actual orientation to achieve a target orientation of the lower drill string. A drilling method includes actuating the control device to prevent relative rotation of the drill strings, providing a sensed actual orientation of the lower drill string, comparing the sensed actual orientation with a target orientation of the lower drill string, actuating the control device to allow the lower drill string to rotate to provide the target orientation, and actuating the control device to prevent relative rotation of the drill strings. | 05-06-2010 |
Terence A. Schroter, Edmonton CA
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20150233203 | Multiple Channel Rotary Electrical Connector - A multiple channel rotary electrical connector can include multiple first contacts which are radially spaced apart from each other, and multiple second contacts which electrically contact respective ones of the first contacts while there is relative rotation between the first and second contacts. The second contacts may be radially spaced apart from each other. A well tool can include one section which rotates relative to another section of the well tool, and a multiple channel rotary electrical connector which includes multiple annular-shaped contacts that rotate relative to each other. A method of operating a well tool in a subterranean well can include producing relative rotation between sections of the well tool, and communicating multiple channels of electrical signals between the sections while there is relative rotation between the sections. The communicating can include electrically contacting multiple annular-shaped contacts with each other. | 08-20-2015 |
Terence Allan Schroter, Edmonton CA
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20100282511 | Wired Smart Reamer - A wired reamer for use on a downhole drillstring is disclosed. In some embodiments, the reamer includes a reamer body comprising a pathway therethrough and wiring located within the pathway for transmitting at least one of power or communications. In other embodiments, the reamer includes a reamer body comprising a pathway enclosed within the reamer body, wiring located within the pathway for transmitting at least one of power or communications, a sensor and a processor located within the reamer body. The sensor is connected with the wiring for transmitting data measured by the sensor through the wiring, and the processor is connected with the wiring for receiving the data from the sensor. | 11-11-2010 |
20130046417 | Apparatus and a Control Method for Controlling the Apparatus - In an apparatus of the type comprising a first assembly, a second assembly, an orientable rotatable connection between the first assembly and the second assembly, and a control device associated with the orientable rotatable connection, a method for controlling the actuation of the control device. Particular embodiments of the method include comparing an actual orientation of the second assembly with a target orientation, actuating the control device to perform a control device actuation cycle if the actual orientation is not acceptable, determining an updated actual orientation of the second assembly, comparing the updated actual orientation with the target orientation, and repeating the control device actuation cycle if the updated target orientation is not acceptable. A first exemplary embodiment of the method represents a target approach to achieving the target orientation. A second exemplary embodiment of the method represents an incremental approach to achieving the target orientation. | 02-21-2013 |