Patent application number | Description | Published |
20090315069 | THIN GALLIUM NITRIDE LIGHT EMITTING DIODE DEVICE - Disclosed is a light emitting diode (LED) device that comprises a crystal structure of a sapphire substrate-free gallium nitride (GaN) LED, wherein the crystal structure is mounted on a first surface of a sub-mount substrate in the form of a unit chip, and the first surface of the sub-mount substrate has a surface area greater than the surface area of a region in which the unit chip is bonded. Preforms for manufacturing the LED device and a method for manufacturing the LED device are also disclosed. The sapphire substrate, on which the crystal structure of the light emitting diode has grown, is processed into a unit chip before being removed. Thus, any crack in the crystal structure of the light emitting diode that may occur during the removal of the sapphire substrate can be prevented. Therefore, a thin light emitting diode device can be manufactured in a mass production system. | 12-24-2009 |
20120269498 | UNIT FOR SUPPORTING A SUBSTRATE AND APPARATUS FOR TREATING A SUBSTRATE WITH THE UNIT - A substrate treatment apparatus and a supporting unit are provided. The substrate treatment apparatus includes a chamber in which a substrate is processed; a supporting unit that is disposed in the chamber and is configured to support the substrate; and a heating member that is configured to apply heat to the substrate supported by the supporting unit. The supporting unit includes a plate; a plurality of supporting pins upwardly protruding from the plate; and at least one auxiliary pin upwardly protruding from the plate. A distance between a central point of the plate and the at least one auxiliary pin is different from a distance between the central point of the plate and the supporting pins. | 10-25-2012 |
20130115760 | METHOD OF FORMING A THIN LAYER STRUCTURE - A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets. | 05-09-2013 |
20130171744 | METHODS OF THERMALLY TREATING A SEMICONDUCTOR WAFER - A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient. | 07-04-2013 |
20140322832 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster. | 10-30-2014 |
20140357071 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DOPED LAYER - A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region. | 12-04-2014 |
Patent application number | Description | Published |
20140361427 | FLEXIBLE STACK PACKAGES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME - Flexible stack packages are provided. The flexible stack package includes a first unit package and a second unit package which are sequentially stacked. Each of the first and second unit packages has a fixed area and a floating area. The fixed area of the first unit package is connected and fixed to the fixed area of the second unit package by a fixing part. | 12-11-2014 |
20140361437 | PACKAGE SUBSTRATES AND METHODS OF FABRICATING THE SAME - Package substrates are provided. The package substrate includes a core layer having a first surface defining trench portions and ridge portions between the trench portions, at least one first trace on a bottom surface of each of the trench portions, and second traces on respective ones of top surfaces of the ridge portions. Related methods are also provided. | 12-11-2014 |
20150028473 | STACK PACKAGES AND METHODS OF FABRICATING THE SAME - Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided. | 01-29-2015 |
20160064359 | STACK PACKAGES AND METHODS OF FABRICATING THE SAME - Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip. | 03-03-2016 |
Patent application number | Description | Published |
20140290993 | MULTILAYER CERAMIC CAPACITOR, MANUFACTURING METHOD THEREOF, AND CIRCUIT BOARD FOR MOUNTING ELECTRONIC COMPONENT - There is provided a multilayer ceramic capacitor including: a ceramic body including a plurality of dielectric layers laminated therein; an active part including a plurality of first and second internal electrodes alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, and forming capacitance; an upper cover layer formed on the active part and including an upper marking electrode therein; and first and second external electrodes formed on the end surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively, wherein when a thickness of the dielectric layer is d and a distance between a first internal electrode formed in the uppermost portion of the active part and the upper marking electrode is A1, 2d≦A1 is satisfied. | 10-02-2014 |
20140334062 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND BOARD FOR MOUNTING THE SAME - There are provided a multilayer ceramic electronic component and a board for mounting the same. The multilayer ceramic electronic component includes: a hexahedral ceramic body including dielectric layers and satisfying T/W>1.0 when a width thereof is defined as W and a thickness thereof is defined as T; first and second internal electrodes stacked to face one another, with the dielectric layer interposed therebetween, within the ceramic body; and insulating layers formed on both lateral surfaces of the ceramic body and having a thickness less than that of the ceramic body, wherein when the sum of the width of the ceramic body and widths of the insulating layers is defined as Wb, 0.90≦W/Wb≦0.97 is satisfied. | 11-13-2014 |
20150270220 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern. | 09-24-2015 |
20150303181 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer. | 10-22-2015 |
20150340303 | MULTI CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces. | 11-26-2015 |
20150348942 | FLEXIBLE STACK PACKAGES HAVING WING PORTIONS - A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the flexible layer, and a contact portion disposed on the chip to penetrate the flexible layer and exposed at a surface of the flexible layer. Each of the first and second packages includes a fixing portion and a wing portion. A first adhesion part is disposed between the fixing portion of the first package and the fixing portion of the second package to combine the first package with the second package. A first stretchable interconnector electrically connects or couples the contact portion of the first package to the contact portion of the second package. | 12-03-2015 |
Patent application number | Description | Published |
20110309358 | SEMICONDUCTOR CHIP WITH FINE PITCH LEADS FOR NORMAL TESTING OF SAME - A semiconductor chip includes a semiconductor substrate having a top surface and a bottom surface. A circuit layer having bonding pads may be formed over the top surface of the semiconductor substrate. Through electrodes may be formed to pass from a bottom surface to a top surface of the semiconductor substrate, and the through electrodes may comprise through parts connected with the bonding pads and projecting parts formed over the bottom surface of the semiconductor substrate and electrically connected with the through parts. Test pad parts may be disposed over the bottom surface of the semiconductor substrate and is connected with the through electrodes to test normal operation of the circuit layer and electrical connections of the through electrodes and the circuit layer. | 12-22-2011 |
20130099375 | SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body. | 04-25-2013 |
20140021602 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure. | 01-23-2014 |
20140145343 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor structure including the first conductive layers. | 05-29-2014 |
20140175605 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR APPARATUS WITH EMBEDDED CAPACITOR - A semiconductor chip includes a semiconductor substrate having one and the other surfaces and formed with a plurality of semiconductor devices; an internal wiring layer having multi-layered internal wiring lines which are formed over the one surface and are electrically connected with the plurality of semiconductor devices, an uppermost internal wiring line among the internal wiring lines being formed with a power supply pad and a ground pad; a dielectric layer formed over the uppermost internal wiring line in such a way as to expose the power supply pad and the ground pad; an external connection reinforcing line formed over the power supply pad or the ground pad which is exposed, and extending onto the dielectric layer; and an embedded capacitor constituted by the external connection reinforcing line, and the dielectric layer and a portion of the is uppermost internal wiring line which correspond to the external connection reinforcing line. | 06-26-2014 |
20140368461 | DISPLAY APPARATUS - A display apparatus having a screen on which recording by a user's touch can be performed is provided. The display apparatus includes a display configured to provide the screen, an accommodator configured to accommodate the display and having a screen aperture formed thereon with a predetermined depth to expose the screen, a touch position sensor configured to sense the position of a touch device that is used by a user when a distance between the screen and the touch device is shorter than the predetermined depth, a vibration sensor mounted on the display and configured to sense vibration of the display due to a contact of the touch device with the screen, and a controller configured to control the display to perform recording on a point of the screen that corresponds to the sensed position of the touch device when the vibration is sensed. | 12-18-2014 |
20150061120 | STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME - Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed. | 03-05-2015 |
20150270229 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate having a front surface, a circuit unit formed within the semiconductor substrate and extending from the front surface into the semiconductor substrate, and a rear surface opposite the front surface, and a girder beam disposed outside of the circuit unit and within the semiconductor substrate. | 09-24-2015 |
Patent application number | Description | Published |
20120323243 | DRILL FOR IMPLANT SURGERY - A drill for an implant surgery is provided which allows a mucous membrane in the maxillary sinus to be quickly and safely lifted without being damaged during a surgery for the maxillary sinus. The drill for use in an implant surgery includes a connection portion formed at an upper end of a body of the drill to be connected with a driving device; and a cutting portion formed at a lower end of the body and having a cutting blade for drilling, wherein an outer circumferential edge of a distal end of the cutting portion protrudes rather than a center of the distal end of the cutting portion. | 12-20-2012 |
20140194881 | DRILL, DRILL COVER, AND SURGICAL INSTRUMENT FOR COLLECTING AUTOLOGOUS BONE EMPLOYING SAME - A drill and drill cover and autogenous bone collector using the same are provided. The autogenous bone collector comprises s shaft unit connected to a driving device and a cutting unit which revolves and collects bone paticles of a patient. The cross-sectional area of the cutting unit is from 10% to 40% of an area of an imaginary circle having a radius corresponding to a distance from the center of the cutting unit to the outermost end portion of the cutting unit. | 07-10-2014 |
20140199657 | MEMBRANE FOR ALVEOLAR BONE REGENERATION - A membrane for alveolar bone regeneration to guide bone generation by adapting to a bone graft material, which fills a bone defect area, includes a central hole through which an implant is inserted into an alveolar bone, wherein the membrane includes: a coupling part to couple the membrane with the implant; a side bending part that is downwardly bent from the coupling part to have an overall curved shape with a gentle slope; and lateral covering parts that protrude from edges of the side bending part and are bent and curved toward an alveolar bone defect area, wherein the side bending part and the lateral covering parts are pre-formed in three-dimensions to fit a final shape of the alveolar bone that is to be regenerated. | 07-17-2014 |
20140349251 | DENTAL MEMBRANE - A dental membrane disposed in a deficient region of an alveolar bone to form a space for regeneration of the alveolar bone or to surround a bone graft, wherein the dental membrane is fixed by an insert inserted and fixed in the alveolar bone and a cover member combined to the insert, the dental membrane including: an upper portion surrounding a top surface of the deficient region of the alveolar bone; and a side bending portion bended downward from the upper portion and surrounding a side surface of the deficient region of the alveolar bone, wherein the upper portion includes: a combined portion combined to the insert and the cover member to be fixed; and a protruding portion extending and protruding upward from the combined portion. | 11-27-2014 |
Patent application number | Description | Published |
20110054915 | COMPUTING CIRCUITS AND METHOD FOR RUNNING AN MPEG-2 AAC OR MPEG-4 AAC AUDIO DECODING ALGORITHM ON PROGRAMMABLE PROCESSORS - The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated. | 03-03-2011 |
20130293299 | VOLTAGE VARIABLE TYPE DIGITAL AUDIO AMPLIFYING DEVICE FOR NOISE COMPENSATION AND METHOD THEREOF - The present invention relates to a voltage variable type digital audio amplifying device for noise compensation and a method therefore, and more specifically, varies the power according to an audio input signal, and compensates for the noise generated when varying the power, thereby enhancing audio output efficiency and easily removing noise. | 11-07-2013 |
20130297410 | SYSTEM AND METHOD FOR AUTIONING ADVERTISEMENT USING DIGITAL CONTENTS RANKING AND METHOD THEREFOR - The present invention relates to an auction for an advertisement that can be used for streaming of digital contents, and more specifically, to an auction for an advertisement that can be used for streaming of digital contents that can maximize the economic profit of a contents provider by maximizing the use of an advertisement. In particular, the present invention relates to a system and a method for conducting an advertisement auction considering popularity ranking of contents, specific contents, profile of users. The present invention enables a contents provider to use the characteristics of on-line contents to conduct the advertisement auction, thereby maximizing the economic profits, and building a foundation for maintaining a business that provides contents for free or at cost. | 11-07-2013 |
20140023208 | DIGITAL AUDIO AMPLIFICATION DEVICE USING HARMONICS AND METHOD THEREOF - The present invention relates to a digital audio amplification device using harmonics and a method thereof, and more specifically, the invention differentially generates characteristics of harmonics (for instance, amplitude or frequency components of harmonics) of an audio signal in order to compensate the audio signal that exceeds a preset threshold value according to the amplitude and characteristics of the audio signal, if the audio signal exceeds the preset threshold value, thereby easily improving the amplitude and the pitch of audio during digital audio amplification. | 01-23-2014 |
20140028509 | TERMINAL AND METHOD FOR USING A PIEZOELECTRIC MODULE AS AN ANTENNA - Terminals, apparatuses and methods for operating a piezoelectric module included in a terminal in one or more operation modes, including: a control unit which determines an operation mode of a piezoelectric module that includes a piezoelectric element, the piezoelectric module operating according to the operation mode determined by the control unit; and a voltage control unit which applies an operation voltage for generating an operation frequency according to the operation mode determined by the control unit to the piezoelectric module. The one or more operation modes includes an antenna mode in which the piezoelectric module operates as an antenna in the terminal. Accordingly, the antenna is implemented using the piezoelectric module in the terminal, thereby promoting and enhancing mounting characteristics and durability of the terminal. | 01-30-2014 |
20140222611 | SYSTEM AND METHOD FOR A CURATOR RECOMMENDED SALE OF COMMODITIES - The present disclosure relates to a curator recommended sale system and method. The curator recommended sale system includes a commodity list generation unit configured to receive commodities for sale of a vendor from a vendor terminal, generate a list of the commodities for sale, receive recommended commodities by a curator based on the list of commodities for sale from a curator terminal, and generate a list of the recommended commodities, a payment unit configured to process payment on a recommendation commodity included in the list of recommended commodities when a purchase request for the recommendation commodity is received from the terminal of a purchaser selecting the curator, and a profit share unit configured to pay a commission to the curator according to sales of the recommendation commodity. | 08-07-2014 |
Patent application number | Description | Published |
20130187745 | TRANSMISSION-LINE TRANSFORMER IN WHICH SIGNAL EFFICIENCY IS MAXIMISED - Provided is a transmission line transformer having increased signal efficiency. The transmission line transformer is formed on an integrated circuit (IC), wherein a first transmission line disposed in one direction. Second and third transmission lines have same length direction as the first transmission line and are spaced apart from each other in a lateral direction above or below the first transmission line. Accordingly, an area of the first transmission line and areas of the second and third transmission lines, which face each other, are increased, thereby improving a coupling factor. Also, since a secondary transmission line is divided into two regions and uses the second and third transmission lines that have narrower widths than the first transmission line, parasitic capacitance components generated between the first through third transmission lines and a semiconductor substrate may be decreased. | 07-25-2013 |
20130200981 | TRANSMISSION LINE TRANSFORMER WHICH MINIMIZES SIGNAL LOSS - Provided is a transmission line transformer, and more particularly, a transmission line transformer capable of decreasing a power loss caused by a parasitic resistance component of the transmission line transformer and improving a coupling factor by forming a primary transmission line and a secondary transmission line parallel to each other on an integrated circuit (IC) by using a highest layer metal line, and forming a lower layer metal line immediately below the highest layer metal line in addition to the highest layer metal line in a region where the primary transmission line and the secondary transmission line face each other, while forming the transmission line transformer used in a high frequency circuit via a semiconductor process. | 08-08-2013 |
20130207224 | DIODE FOR ELECTROSTATIC PROTECTION - Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode. | 08-15-2013 |
20140232462 | POWER AMPLIFIER USING DIFFERENTIAL STRUCTURE - Provided is a power amplifier which includes: a first transistor and a second transistor each having a first end connected to a first power source supplying a first voltage and to which signals having a same size but opposite polarities are input; a third transistor and a fourth transistor having first ends respectively connected to the first ends of the first transistor and the second transistor; and a fifth transistor having a first end connected to second ends of the third and fourth transistors and controlling oscillation of the third or fourth transistor. | 08-21-2014 |
20140232466 | LINEAR AMPLIFIER AND MULTISTAGE LINEAR AMPLIFIER - Disclosed is a linear amplifier which includes: a common source transistor with the gate connected with an input node; a first common gate transistor connected with the common source transistor in a cascode type, with the drain connected with an output node; and a second common gate transistor connected in parallel with the first common gate transistor, with the gate connected with the input node and the drain connected with the output node. | 08-21-2014 |
20140264627 | MULTI-GATE TRANSISTOR - Disclosed is a multi-gate transistor which includes a plurality of gates that is branched from one port, that is alternately formed to face each other, and in which currents flow in the adjacent gates in an opposite direction to each other; a source that is formed on one side or the other side of each of the plurality of gates; and a drain that is formed on the other side or the one side of each of the plurality of gates. | 09-18-2014 |
20140327083 | COMBINATION-TYPE TRANSISTOR AND METHOD FOR MANUFACTURING SAME - Disclosed is a combination-type transistor including a first MOSFET that includes a gate, a first source formed on one side of the gate, and a first drain formed on the other side of the gate; a second MOSFET that includes the gate, a second drain formed on the one side of the gate, and a second source formed on the other side of the gate; a first BJT that is formed such that the first source of the first MOSFET is used as an emitter, the second drain of the second MOSFET is used as a collector, and the substrate is used as a base; and a second BJT that is formed such that the second source of the second MOSFET is used as an emitter, the first drain of the first MOSFET is used as a collector, and the substrate is used as a base. | 11-06-2014 |
20150109067 | CONTROL DEVICE OF LC CIRCUIT USING SPIRAL INDUCTOR - Provided is a control device of a LC circuit using a spiral inductor, comprising: a spiral inductor in which a first metal line connected to a first terminal and a second metal line connected to a second terminal cross at least one time to be connected in a spiral shape, and that includes at least one crossing part; at least one transistor in which a drain terminal and a source terminal are respectively connected to a first metal line portion and a second metal line portion that correspond to the crossing part; a variable capacitor that is connected to a first terminal and a second terminal of the spiral inductor in parallel; and a controller that respectively sends control signals to the transistor and the variable capacitor to control a resonant frequency or an output. | 04-23-2015 |
Patent application number | Description | Published |
20140193672 | THERMAL TO ELETRIC CONVERTING CELL - Disclosed are a metal support thermal to electric converting cell, a thermal to electric power generator using the same, and a method for manufacturing the thermal to electric converting cell. Unlike a conventional method for manufacturing the thermal to electric converting cell by sintering a solid electrolyte, a method provided by the present invention is to manufacture the thermal to electric converting cell by coating a metal support capable of collecting electricity and functioning as an electrode with the solid electrolyte in the form of a high density thin film, so that the cell has durability and stability at a high temperature and a high pressure and has improved efficiency due to the thin film structure. | 07-10-2014 |
20140202513 | AMTEC UNIT CELL WITH PARTIALLY OPENED INTERNAL ELECTRODE AND METHOD FOR MANUFACTURING THE AMTEC CELL - Disclosed are an open internal electrode AMTEC unit cell, a method for manufacturing the same and a method for connecting circuits. In order to overcome the difficulty in collecting electricity within a conventional AMTEC unit cell, an internal electrode of which a portion is open to the outside, so that the internal electrode and an external electrode can be electrically connected to each other at the outside of the unit cell, and a metal support is used as the internal electrode, so that the internal electrode has durability and stability, and a solid electrolyte is formed in the form of a thin film, and as a result, the AMTEC unit cell has an improved efficiency and a simpler manufacturing process. | 07-24-2014 |
20140242327 | FIBER-REINFORCED CERAMIC COMPOSITE MATERIAL HONEYCOMB AND METHOD FOR PREPARING THE SAME - Disclosed herein is a fiber-reinforced ceramic composite material honeycomb, including: a plurality of inner tubes, each of which is made of a fiber-reinforced ceramic composite material; and an outer shell which is made of a fiber-reinforced ceramic composite material and which surrounds the plurality of inner tubes. | 08-28-2014 |
20140251405 | AMTEC CELL AND METHOD FOR MANUFACTURING THE AMTEC CELL - Disclosed is a modularized AMTEC cell which does not require a separate collector by using a metal support as an internal electrode, has durability and stability even at a high temperature and a high pressure, very easily joins the cell to a housing by inserting the cell into an insulating portion and sealing, minimizes the number of the parts and expands easily the system scale through the serial-parallel structure. | 09-11-2014 |
20140299171 | MANUFACTURING METHODS OF MATERIALS POWDER FOR PERFORMANCE IMPROVED ELECTRODE AND USING THE SAME ELECTRODE AND ITS APPLICATION - Disclosed is a material for an electrode having an excellent performance and an excellent durability by maintaining high electrical conductivity and by restraining the growth of the grain at a high temperature. The material can be manufactured by synthesizing composite materials through use of a metallic material of Mo and a ceramic material, and then the composite materials can be used as the electrode. | 10-09-2014 |
20140332046 | ALKALI METAL THERMAL TO ELECTRIC CONVERTER SYSTEM INCLUDING HEAT EXCHANGER - Disclosed is a thermal to electric power generator comprising: a plurality of thermal to electric power generation cells; a case in which the plurality of the thermal to electric power generation cells are placed; a condensing unit which is disposed on an upper portion of the case and collects and condenses a working fluid which has passed through the plurality of the thermal to electric power generation cells; an evaporator which is disposed on a lower portion of the case, converts the working fluid into vapor by transferring heat to the working fluid; a heat exchanger which is placed on a surface other than an upper surface of the outside of the case contacting with the condensing unit; a circulator which connects the condensing unit and the evaporator; and a joiner which joins the evaporator to the plurality of the thermal to electric power generation cells. | 11-13-2014 |
20140332047 | SERIAL AND PARALLEL CONNECTION STRUCTURES OF THERMAL TO ELECTRIC CONVERTING CELLS USING POROUS CURRENT COLLECTING MATERIAL AND APPLICATION OF THE SAME - Disclosed is a method for collecting current by using a liquefied or gaseous working fluid present inside an electric power generator system. Through the method, a porous structure like a metal felt capable of infusing the liquefied working fluid is inserted and connected to the cell, and then the working fluid present around the cell is naturally infused, so that current is collected. For this purpose, a current collector is provided, which is located between adjacent thermal to electric power generation cells among a plurality of the thermal to electric power generation cells. | 11-13-2014 |
20150328582 | ELECTRODE-SUPPORT TYPE OF GAS-SEPARATION MEMBRANE MODULE, TUBULAR STRUCTURE OF SAME, PRODUCTION METHOD FOR TUBULAR STRUCTURE, AND HYDROCARBON REFORMING METHOD USING SAME - The present invention provides: an electrode-supporting type of gas-separation membrane module for selectively effecting the passage of a gas via an electron exchange reaction due to a coupling-material layer and gas exchange via an ion-conducting separation layer; a tubular structure of same; a production method for the tubular structure; and a hydrocarbon-reforming method using the gas-separation membrane module. The present invention is advantageous in that outstanding chemical and mechanical durability can be ensured by using a fluorite-based ion-conducting membrane which is chemically stable in CO2 and H2O atmospheres in particular, at high temperature, and in that a pure gas can be produced inexpensively since the passage of gas occurs due to an internal circuit even without applying a voltage from the outside. | 11-19-2015 |
Patent application number | Description | Published |
20090310339 | BACKLIGHT UNIT FOR LIQUID CRYSTAL DISPLAY DEVICE - Provided is a backlight unit for a liquid crystal display device. The backlight unit includes: a chassis; a printed circuit board connected to a side of the chassis, the printed circuit board including a plurality of light emitting diodes, and a pair of conductive pads through which power is supplied to the light emitting diodes, wherein the pair of conductive pads are disposed on an end of the printed circuit board; and a power socket into which the pair of the conductive pads are inserted. | 12-17-2009 |
20110057965 | LIQUID CRYSTAL DISPLAY DEVICE INCLUDING EDGE-TYPE BACKLIGHT UNIT AND METHOD OF CONTROLLING THE LIQUID CRYSTAL DISPLAY - A method of controlling a liquid crystal display (LCD) device including an LCD panel and an edge-type backlight unit is provided. The method includes: controlling turn-on and turn-off periods of an upper light source unit and a lower light source unit of the edge-type backlight unit to be synchronized with a period during which a 3D image is output on the LCD panel, wherein the upper light source unit includes a light source disposed at an upper edge of the edge-type backlight unit, and the lower light source unit includes a light source disposed at a lower edge of the edge-type backlight unit. | 03-10-2011 |
20110096105 | METHOD AND APPARATUS FOR COMPENSATING FOR TEMPERATURE VARIATIONS OF A LIQUID CRYSTAL DISPLAY PANEL FOR A 3-DIMENSIONAL DISPLAY - Methods and apparatuses are provided for compensating for a temperature of a liquid crystal display (LCD) panel. The method includes selecting a lookup table corresponding to a detected temperature of the LCD panel from among lookup tables for a 3-dimensional (3D) display of the LCD panel; and adjusting luminance to be output to the LCD panel based on the selected lookup table. | 04-28-2011 |
20110102422 | TWO-DIMENSIONAL/THREE-DIMENSIONAL IMAGE DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A display apparatus which displays two-dimensional (2D) and three-dimensional (3D) images and a method of driving the same. In the 2D/3D image display apparatus, an image signal input unit inputs, to a display panel, a left image signal, a left inversion image signal, at least one 2D image signal, a right image signal and a right inversion image signal, a left shutter of shutter glasses is open in synchronization with the left image signal, a right shutter of the shutter glasses is open in synchronization with the right image signal, and the left shutter and the right shutter of the shutter glasses are closed in synchronization with the left inversion image signal, the at least one 2D image signal, and the right inversion image signal. | 05-05-2011 |
20110148863 | 3D DISPLAY DRIVING METHOD AND 3D DISPLAY APPARATUS USING THE SAME - A method for driving a 3D display and a display apparatus using the same are provided. The display apparatus includes a storage unit to store a received image and a controlling unit to drive a display by adjusting the brightness value using a first look-up table when the previous frame is different from the current frame and adjusting the brightness value using a second look-up table when the previous frame is the same as the current frame. According to the exemplary embodiment, an overdrive method may be applied to a 3D image display apparatus effectively. | 06-23-2011 |
20110148943 | METHOD FOR DRIVING THREE-DIMENSIONAL (3D) DISPLAY AND 3D DISPLAY APPARATUS USING THE SAME - A method for driving a three dimensional (3D) display and a 3D display apparatus using the same are provided. The 3D display apparatus includes a storage unit which stores a received image; and a controller which compares a previous frame of the received image with a current frame of the received image, and determines whether or not to input an image of the current frame to a liquid crystal panel based on whether the previous frame is identical to the current frame. Therefore, a method for driving a 3D display which does not cause characteristics of a liquid crystal to be deteriorated and a 3D display apparatus using the same are provided. | 06-23-2011 |
20110157165 | METHOD AND APPARATUS FOR DISPLAYING 3-DIMENSIONAL IMAGE AND METHOD AND APPARATUS FOR CONTROLLING SHUTTER GLASSES - An image display method includes alternately receiving left and right images of a 3D image; and turning on a backlight such that the backlight is on only in periods when the left images are displayed or only in periods when the right images are displayed. A method of controlling shutter glasses separately for left and right images of a three-dimensional (3D) image includes alternately receiving the left and right images of the 3D image; and opening two shutters of the shutter glasses only in periods when the left images are received or only in periods when the right images are received. | 06-30-2011 |
20110193897 | METHOD AND APPARATUS FOR CONTROLLING THE PARTITIONS OF A BACKLIGHT UNIT OF A 3D DISPLAY APPARATUS - A method and apparatus for controlling a backlight unit of a three-dimensional (3D) display apparatus receiving a 3D video sequence is provided. The method includes determining the image brightness level of the 3D video sequence displayed on a liquid crystal display (LCD) unit, for each of a plurality of partial regions of the LCD unit to which a plurality of sub-blocks of the backlight unit emit light; determining turn-on times of the plurality of sub-blocks of the backlight unit, based on the image brightness of each of the partial regions of the LCD unit; and determining turn-on periods of the plurality of sub-blocks of the backlight unit by synchronizing with a switching period between a set including a left visual point frame and a right visual point frame of the 3D video sequence. | 08-11-2011 |
20110267341 | STEREOSCOPIC DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A stereoscopic display apparatus includes a display panel which scans an image at a frame frequency that is an odd-numbered multiple of a field frequency, an image signal input unit which inputs an image signal to the display panel, a backlight unit which emits light to the display panel, and a shutter controller which controls an opening and a closing of a left eye shutter and a right eye shutter of shutter glasses. | 11-03-2011 |
20110292041 | STEREOSCOPIC DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A stereoscopic display apparatus is provided. The display apparatus includes a display panel for scanning an image alternately at a first frame frequency and a second frame frequency, different from the first frame frequency, an image signal input unit for inputting an image signal to the display panel, a backlight unit for emitting light to the display panel, and a shutter controller for selectively controlling an opening and closing of a left eye shutter and a right eye shutter of shutter glasses. | 12-01-2011 |
20120086712 | 3D DISPLAY PANEL AND 3D DISPLAY APPARATUS USING THE SAME AND DRIVING METHOD THEREOF - A three-dimensional (3D) display panel, a 3D display apparatus using the same, and a driving method thereof are provided. The 3D display apparatus includes: an image display panel which displays an image; a phase shift panel which alternately shifts a polarization direction of light outputted from the image display panel; a backlight unit which provides a backlight; and a control unit which turns off the backlight unit during a crosstalk period where the phase shift panel performs the shift operation and to turn on the backlight unit for a stabilization period after the crosstalk period. | 04-12-2012 |
20120306945 | IMAGE SIGNAL PROCESSING DEVICE FOR SEQUENTIALLY DRIVING A PLURALITY OF LIGHT SOURCES, DISPLAY APPARATUS USING THE IMAGE SIGNAL PROCESSING DEVICE, AND DISPLAY METHOD THEREOF - An image signal processing device, a display apparatus, and a display method are provided. The image signal processing device includes: a light source driver which turns on a plurality of light sources providing different colors, in a given order; a sub-frame calculator which divides a frame of an input image signal into a plurality of sub-frames; a display processor which sequentially outputs the plurality of sub-frames on a display panel; and a sync signal processor which outputs a sync signal to the backlight driver to turn on the plurality of light sources in each of the plurality of sub-frames, in the given order. | 12-06-2012 |
20130342589 | DISPLAY METHOD AND APPARATUS HAVING A DISPLAY PANEL WITH A BACKLIGHT UNIT UTILIZING WHITE AND BLUE LIGHT SOURCES - A display apparatus is disclosed. The display apparatus includes a panel unit which comprises a plurality of sub pixels having different colors; a backlight unit which provides backlight to the panel unit using a white light source and a blue light source; an image processing unit which converts image data into first color frame data and second color frame data; a panel driving unit which turns on a first color sub pixel according to the first color frame data, and which turns on a second color sub pixel according to the second color frame data; a backlight driving unit for driving the backlight unit; and a control unit which controls the backlight driving unit to consecutively turn on the white light source and the blue light source according to operations of the panel driving unit. Accordingly, brightness may be enhanced. | 12-26-2013 |
20150015828 | TRANSFLECTIVE IMAGE DISPLAY APPARATUS AND CONTROL METHOD THEREOF - A transflective image display apparatus includes a transmissive polarizing plate; a color filter disposed below the transmissive polarizing plate and including a white color filter and at least two of a red color filter, a green color filter, and a blue color filter; a liquid crystal display panel disposed below the color filter; an electrical polarization control unit disposed below the liquid crystal display panel; a reflective polarizing plate disposed below the electrical polarization control unit; a backlight unit disposed below the reflective polarizing plate and including a white light source and a light source configured to emit light corresponding to at least one of the red color filter, the green color filter, and the blue color filter; and a controller configured to control the liquid crystal display panel, the electrical polarization control unit, and the backlight unit periodically in at least two states according to a predetermined condition. | 01-15-2015 |
20150194088 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - A control method of a display apparatus including a panel configured to include red (R), green (G), and white (W) subpixels, and a backlight configured to provide the panel with backlight using at least one of a white light source and a blue light source, including: converting image data into R, G, and blue (B) subframe data; turning on the R, G, and W subpixels according to the R, G, and B subframe data; and turning on the W subpixel, setting a brightness of the white light source to a brightness value of the R, G, and B subframe data, providing the panel with white light at the set brightness, turning on subpixels corresponding to remaining subframe data, setting at least one of the brightness of the white light source and a brightness of the blue light source, and providing the panel with light at the set brightnesses, is provided. | 07-09-2015 |
20150277173 | TILED DISPLAY AND BEZELLESS LIQUID CRYSTAL DISPLAY APPARATUS - A tiled display includes a plurality of bezelless liquid crystal display (LCD) panels in which pixels are exposed from at least one of a top side, a bottom side, a left side, and a right side thereof; at least one backlight unit disposed below the plurality of bezelless LCD panels and configured to emit light. The plurality of bezelless LCD panels are disposed such that sides from which the pixels are exposed are connected to each other, the backlight unit comprises a plurality of light emitting diodes (LEDs) configured to emit the light to the bezelless LCD panel, and the plurality of LEDs are disposed at equal intervals below the plurality of bezelless LCD panels including a portion where the plurality of bezelless LCD panels are connected to each other. | 10-01-2015 |
Patent application number | Description | Published |
20080310243 | Semiconductor memory device for reducing precharge time - A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size. | 12-18-2008 |
20090034348 | WRITE DRIVER CIRCUIT OF AN UNMUXED BIT LINE SCHEME - A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver. | 02-05-2009 |
20090251984 | Static memory device and static random access memory device - A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group. | 10-08-2009 |
20140001564 | SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF DESIGNING THE SAME, AND METHOD OF FABRICATING THE SAME | 01-02-2014 |
20140085966 | FIELD EFFECT TRANSISTORS INCLUDING ASYMMETRICAL SILICIDE STRUCTURES AND RELATED DEVICES - A fin Field Effect Transistor (finFET) can include a source region and a drain region of the finFET. A gate of the finFET can cross over a fin of the finFET between the source and drain regions. First and second silicide layers can be on the source and drain regions respectively. The first and second silicide layers can include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces are different sizes. | 03-27-2014 |
20140101395 | SEMICONDUCTOR MEMORY DEVICES INCLUDING A DISCHARGE CIRCUIT - Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell. | 04-10-2014 |
Patent application number | Description | Published |
20090068823 | Plasma Ion Doping Method and Apparatus - In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described. | 03-12-2009 |
20100025749 | SEMICONDUCTOR DEVICE - A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer | 02-04-2010 |
20100035425 | Integrated Circuit Devices Having Partially Nitridated Sidewalls and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 02-11-2010 |
20100072545 | Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor - A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current. | 03-25-2010 |
20120282769 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING ELECTRICALLY CONDUCTIVE LAYERS THEREIN WITH PARTIALLY NITRIDATED SIDEWALLS - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 11-08-2012 |
Patent application number | Description | Published |
20120128360 | OPEN OPTICAL ACCESS NETWORK SYSTEM - The present invention relates to an open optical access network system in which one optical access network is open to enable a plurality of service providers and a plurality of subscribers to simultaneously use the optical access network, to thereby improve the efficiency of using the optical access network, wherein each subscriber can be provided with a plurality of different services from the plurality of service providers, thereby enabling the flexible selection of services and the flexible change in services, thus improving the efficiency of using an optical infrastructure. | 05-24-2012 |
20120148191 | ANGLED PHYSICAL CONTACT RECEPTABLE STUB AND ANGLED PHYSICAL CONTACT TRANSMITTER OPTICAL SUB-ASSEMBLY HAVING THE SAME - An APC receptacle stub and an APC TOSA having the same are provided. The APC receptacle stub includes a first APC stub and a second APC stub. The first APC stub has an optical fiber inserted thereto and is provided with one end section polished in an APC shape. The second APC stub has an optical fiber inserted thereto and is provided with one end section polished in an APC shape and an opposite end section which is coupled to an opposite end section of the first APC stub through rotation adjustment in the same axial direction as an axial direction of the opposite end section of the first APC stub. The APC receptacle stub enables easy optical alignment and is applicable to a light source that is sensitive to reflection. | 06-14-2012 |
20120155876 | SEED LIGHT MODULE FOR WAVELENGTH DIVISION MULTIPLEXING-PASSIVE OPTICAL NETWORK AND METHOD FOR DRIVING THE SAME - A seed light module for a WDM-PON system is provided. The seed light module includes a reflector configured to reflect a part of seed light that is generated from a light source generator, and an optical attenuator configured to attenuate the intensity of the reflected seed light and provide the attenuated seed light, which corresponds to a signal generated by attenuating the intensity of the reflected seed light, to the light source generator. | 06-21-2012 |
20120163822 | APPARATUS AND METHOD FOR DRIVING WAVELENGTH-INDEPENDENT LIGHT SOURCE - An apparatus for driving a wavelength-independent light source is provided. The apparatus includes a seed light signal generation unit configured to generate seed light signals with one or more wavelengths based on a wavelength identification signal, a wavelength light detection unit configured to detect the wavelength identification signal from the seed light signals, an extraction unit configured to extract wavelength information corresponding to the detected wavelength identification signal and extract a driving condition of a wavelength-independent light source corresponding to the extracted wavelength information, and a driving unit configured to drive the wavelength-independent light source according to the extracted driving condition. | 06-28-2012 |
Patent application number | Description | Published |
20110305087 | FLASH MEMORY DEVICE AND READING METHOD THEREOF - A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through bit lines and having page buffers. The page buffers include a bit line connection unit connected between a corresponding bit line and a sensing node, that controls a voltage of the sensing node according to the sensing node voltage control signal; a precharge unit which precharges the sensing node according to the precharge voltage responsive to a precharge control signal; and a data input/output unit sensing a voltage level of the sensing node responsive to a latch control signal and outputting the data of the selected memory cell. | 12-15-2011 |
20120020167 | FLASH MEMORY DEVICE AND A METHOD OF PROGRAMMING THE SAME - A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device. | 01-26-2012 |
20120145272 | AIR DUCT - An air duct disposed at a front end module that includes a radiator grille of a vehicle, a bumper cover having an opening, and an intercooler according to various embodiments of the present invention may include a first duct that guides air into the intercooler through the radiator grille, a second duct that guides air into the intercooler through an opening of the bumper cover and is integrally formed with the first duct, and a separation wall formed between the first duct and the second duct. | 06-14-2012 |
20130146376 | ENGINE ENCAPSULATION STRUCTURE OF VEHICLE - An engine encapsulation structure of a vehicle may include an engine room encapsulation member disposed at an upper portion of an engine compartment and covering an upper portion of a power train having an engine and a transmission, an underbody encapsulation member disposed at a lower portion of the engine compartment and covering a lower portion of the power train, wherein the engine room encapsulation member and the underbody encapsulation member form an inner space and enclose the power train in the inner space when being assembled each other, and a front inlet formed at a front portion of the assembly to allow air through the front inlet and to cool the power train while the air passes through the inner space of the assembly, the air being discharged through a rear outlet formed to the assembly. | 06-13-2013 |
20140133227 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING - A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block. | 05-15-2014 |
Patent application number | Description | Published |
20140300525 | METHODS FOR ANTENNA SWITCH MODULES - Methods for antenna switch modules are disclosed. In certain implementations, a method of making an antenna switch module is provided. The method includes providing a package substrate implemented to receive one or more electrical components, attaching a silicon on insulator (SOI) die to the package substrate, and providing an integrated filter. The SOI die includes a capacitor and a switch coupled to a plurality of radio frequency (RF) signal paths. The integrated filter filters an RF signal received on a first RF signal path of the plurality of RF signal paths, and includes the capacitor of the SOI die and an inductor. | 10-09-2014 |
20140319652 | HIGH QUALITY FACTOR FILTER IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) INTEGRATED DEVICE - Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die. | 10-30-2014 |
20160066414 | PATTERNED GROUNDS AND METHODS OF FORMING THE SAME - A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element. | 03-03-2016 |
Patent application number | Description | Published |
20090072699 | CATHODE RAY TUBE WITH IMPROVED MASK ASSEMBLY - A cathode ray tube including a shadow mask. The shadow mask includes an aperture portion including a plurality of beam guide holes, a non-aperture portion surrounding the aperture portion, and a skirt portion that is bent from an edge of the non-aperture portion toward an electron gun. The non-aperture portion includes a pair of longer sides, a pair of shorter sides, and four corner portions, and a first width of the non-aperture portion measured at the longer side and a second width of the non-aperture portion measured at the shorter side are formed to be less than a third width of the non-aperture portion measured at the corner portions. The shadow mask satisfies the following conditions: 2 mm≦w | 03-19-2009 |
20130100332 | PHOTOGRAPHING APPARATUS AND METHOD - A photographing apparatus includes: a lens unit; a light transmission adjustment unit that adjusts light transmittance of light that passes through the lens unit; a photographing unit that is disposed a reflected light path of the light transmission adjustment unit and that generates an image data according to received light, and a view finder that is disposed on a transmitted light path of the light transmission unit. | 04-25-2013 |
20140273318 | METHOD OF FORMING METALLIC BONDING LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE THEREWITH - A method of forming a metal bonding layer includes forming a first bonding metal layer and a second bonding metal layer on surfaces of first and second bonding target objects, respectively. The second bonding target object is disposed on the first bonding target object to allow the first and second bonding metal layers to face each other. A eutectic metal bonding layer is formed through a reaction between the first and second bonding metal layers. At least one of the first and second bonding metal layers includes a reaction delaying layer formed of a metal for delaying the reaction between the first and second bonding metal layers. | 09-18-2014 |
20150099316 | METHOD OF FORMING METALLIC BONDING LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME - A method of forming a metal bonding layer includes forming first and second bonding metal layers on one surfaces of first and second bonding objects, respectively. The second bonding object is disposed on the first bonding object such that the first bonding metal layer and the second bonding metal layer face each other. A eutectic metal bonding layer is formed through a reaction between the first and second bonding metal layers. At least one of the first bonding metal layer and the second bonding metal layer includes an oxidation prevention layer formed on an upper surface thereof. The oxidation prevention layer is formed of a metal having an oxidation reactivity lower than an oxidation reactivity of the bonding metal layer on the upper surface which the oxidation prevention layer is disposed. | 04-09-2015 |
20160109861 | Wearable Device - A wearable device may include: an analog watch unit that includes a time indicating unit that indicates time, and a drive unit that drives the time indicating unit; a touch screen that senses an input for adjusting the drive unit; and a control unit that controls the drive unit in response to the sensed input. | 04-21-2016 |
Patent application number | Description | Published |
20090162865 | BREAST CANCER RELATED PROTEIN, GENE ENCODING THE SAME, AND METHOD OF DIAGNOSING BREAST CANCER USING THE PROTEIN AND GENE - An isolated protein having an amino acid sequence of SEQ ID No. 4 and having an activity inducing apoptosis, and a gene encoding the same are provided. Also, a microarray having a substrate on which the gene or fragment thereof is immobilized is provided. Also, a method of diagnosing breast cancer using an antibody specifically binding to the protein and a method of diagnosing breast cancer by determining whether the gene is expressed in a cell or not, are provided. | 06-25-2009 |
20100281553 | PRODUCTION METHOD OF CYST EXPRESSED TRANSGENIC ANIMAL USING PKD2 GENE - Disclosed herein is a method for producing a cyst-expressed transgenic animal using a PDK2 gene. The production method comprises preparing a PKD2 protein expression vector, inserting the expression vector into the nucleus of a fertilized egg to produce a PKD2 expression vector-containing fertilized egg, and transplanting the produced fertilized egg into the uterus of a surrogate mother. According to the invention disclosed herein, there is provided a method for producing transgenic animals, in which cysts are expressed only by the overexpression of the PKD2 gene. Also, transgenic mice are provided which can be effectively used in the investigation of cyst expression mechanisms and cyst control systems. | 11-04-2010 |
20120219985 | METHOD FOR THE TOXICITY ASSESSMENTS OF NANO-MATERIALS - The present invention relates to a method for the toxicity assessment of nano-materials, and more specifically, it is relates to an objective, reproducible and accurate assessment method for the unbiased toxicity testings of nano-materials, which minimize artifacts of the conventional methods for the toxicity assessment of the nano-materials by considering the dose characteristics of the nano-material itself using Selective multi-Plane Illumination Microcopy (SPIM); and the response characteristics of the nano-material using the improved or novel cellular responses assessment methods for nano-materials (e.g., modified MTT assay using image cytometric analysis, normal-inverted exposure apparatus, and modified flow cytometry), and a system and an apparatus thereof. | 08-30-2012 |
20130280136 | CLARIFIER FOR BIDET WITH PHYTONCIDE FILTER - Disclosed is a filtering device for a bidet, including a base, a blower sucking air into the bidet, a filter casing mounted to the base, a phytoncide filter unit contained in the filter casing, a door opening and closing the filter casing, and a duct connecting the blower and the filter casing. | 10-24-2013 |
20140017163 | METHOD OF PREPARING SN-BASED OXIDE SEMICONDUCTOR NANOPOWDER AND METHOD OF MANUFACTURING PHOTOELECTRIC ELECTRODE USING SN-BASED OXIDE SEMICONDUCTOR NANOPOWDER - Disclosed herein is a method of preparing a ternary oxide semiconductor compound, including the steps of: dissolving an inorganic salt source including Sn and an inorganic salt source including at least one selected from the alkali earth metal group consisting of Ba, Sr and Ca in a mixed solvent of water and hydrogen peroxide to form a mixed solution; precipitating the mixed solution by changing the PH thereof to obtain a precipitate and then aging the precipitate; and drying and then annealing the aged precipitate to prepare MSnO | 01-16-2014 |
20140068414 | METHOD AND APPARATUS FOR SHARING JAVASCRIPT OBJECT IN WEBPAGES - A method and apparatus for sharing webpage JavaScript objects are disclosed. An embodiment of the invention provides a method for sharing JavaScript objects of webpages that are provided by a server by way of a browser executed at a user client. The method includes: (a) storing a shared JavaScript object from among one or more JavaScript objects of a first webpage in a predefined object storage area; (b) checking for a shared JavaScript object in a second webpage; and (c) forming the second webpage with the shared JavaScript object extracted, where the object storage area is positioned in a JavaScript context. | 03-06-2014 |
20160065153 | INVERTER TYPE POWER AMPLIFIER - The present disclosure relates to an inverter type power amplifier. An exemplary embodiment of the present disclosure provides an inverter type power amplifier including: a first transistor including a gate to which an AC type of input signal is applied through an input port, a first terminal connected a power source voltage, and a second terminal connected to an output port; a second transistor including a gate through which the input signal is applied thereto, a first terminal connected to a ground, and a second terminal connected to the output port; a feedback resistor including a first terminal connected to the input port and a second terminal connected to the output port; and an AC blocking block including a first terminal connected to the output port and a second terminal connected to a DC output port. | 03-03-2016 |