Patent application number | Description | Published |
20090172429 | POWER MODE CONTROL METHOD AND CIRCUITRY - In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states. | 07-02-2009 |
20090248927 | INTERCONNECT BANDWIDTH THROTTLER - An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has take place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. | 10-01-2009 |
20110145909 | Interface Logic For A Multi-Core System-On-A-Chip (SoC) - In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. | 06-16-2011 |
20130339789 | METHOD AND APPARATUS FOR OUTPUT OF HIGH-BANDWIDTH DEBUG DATA/TRACES IN ICS AND SOCS USING EMBEDDED HIGH SPEED DEBUG - Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces. | 12-19-2013 |
20130339790 | APPARATUS, SYSTEM AND METHOD FOR A COMMON UNIFIED DEBUG ARCHITECTURE FOR INTEGRATED CIRCUITS AND SoCs - A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data. | 12-19-2013 |
20140108684 | INTERCONNECT BANDWIDTH THROTTLER - An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has taken place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. Characteristics such as performance, thermal considerations, and average power are adjustable using the interconnect bandwidth throttler. | 04-17-2014 |
20140108695 | INTERFACE LOGIC FOR A MULTI-CORE SYSTEM-ON-A-CHIP (SOC) - In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. | 04-17-2014 |
20150186232 | DEBUG INTERFACE - Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents. | 07-02-2015 |
Patent application number | Description | Published |
20100279973 | SYNTHESIS OF PURINE NUCLEOSIDES - A process for preparing phosphoramidate prodrugs or cyclic phosphate prodrugs of nucleoside derivatives, which is a compound, its stereoisomers, salts (acid or basic addition salts), hydrates, solvates, or crystalline forms thereof. | 11-04-2010 |
20100298257 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent 5 RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 11-25-2010 |
20110245484 | STEREOSELECTIVE SYNTHESIS OF PHOSPHORUS CONTAINING ACTIVES - Disclosed herein are phosphorus-containing actives, their use as actives for treating diseases, and a stereoselective process for preparing the same. Also disclosed herein are useful synthetic intermediates and processes for preparing the same. | 10-06-2011 |
20110251152 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 10-13-2011 |
20120316327 | SYNTHESIS OF PURINE NUCLEOSIDES - A process for preparing phosphoramidate prodrugs or cyclic phosphate prodrugs of nucleoside derivatives, which is a compound, its stereoisomers, salts (acid or basic addition salts), hydrates, solvates, or crystalline forms thereof. | 12-13-2012 |
20130137654 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent 5 RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 05-30-2013 |
20130165401 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent 5 RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 06-27-2013 |
20130165644 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent 5 RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 06-27-2013 |
20130288997 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 10-31-2013 |
20130310551 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 11-21-2013 |
20130338349 | PREPARATION OF 2'-FLUORO-2'-ALKYL-SUBSTITUTED OR OTHER OPTIONALLY SUBSTITUTED RIBOFURANOSYL PYRIMIDINES AND PURINES AND THEIR DERIVATIVES - The present invention provides (i) processes for preparing a 2′-deoxy-2′-fluoro-2′-methyl-D-ribonolactone derivatives, (ii) conversion of intermediate lactones to nucleosides with potent anti-HCV activity, and their analogues, and (iii) methods to prepare the anti-HCV nucleosides containing the 2′-deoxy-2′-fluoro-2′-C-methyl-β-D-ribofuranosyl nucleosides from a preformed, preferably naturally-occurring, nucleoside. | 12-19-2013 |
20140121366 | NUCLEOSIDE PHOSPHORAMIDATES - Disclosed herein are nucleoside phosphoramidates and their use as agents for treating viral diseases. These compounds are inhibitors of RNA-dependent 5 RNA viral replication and are useful as inhibitors of HCV NS5B polymerase, as inhibitors of HCV replication and for treatment of hepatitis C infection in mammals. | 05-01-2014 |