Lin, Zhubei City
Chao-Yi Lin, Zhubei City TW
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20130176467 | Image Capturing Device, Dust Removal System and Vibrating Dust Removal Method Thereof - An image capturing device, a dust removal system and a vibrating dust removal method thereof. The image capturing device comprises an image sensor, a vibrating dust removal unit, an optical component adapter, a detector, a touch screen and a controller. The image sensor receives an optical signal and converts the optical signal into an image signal. The vibrating dust removal unit produces a vibration to remove dust from the image sensor. The detector detects whether a detachable optical component is connected to the optical component adapter and generates a detecting signal. The touch screen displays the image signal and allows a user to designate a dust-removal position. The controller receives the detecting signal to enter into a dust-removal mode or controls the frequency or amplitude of the vibration produced by the vibrating dust removal unit according to the dust-removal position. | 07-11-2013 |
20130286273 | Image Capture Device and Dustproof Method Thereof - An image capture device and a dustproofing method thereof. The image capture device comprises a switch module, optical-component adaptor module, optical-component adaptor detecting module, mask module, power detecting module and controlling module. The switch module switches the image capture device on or off and produces an on signal or off signal correspondingly. The optical-component adaptor detecting module detects whether a removable optical-component is connected with the optical-component adaptor module and produces a detecting signal. The power detecting module measures the residual power in the image capture device and produces a residual power signal. The controlling module, according to the on signal, off signal, detecting signal and the residual power signal controls the mask module to shield or un-shield the photosensor. Therefore, when the image capture device is powered off or during replacement of removable optical-components, the mask module shields the photosensor to render it dustproof. | 10-31-2013 |
Cheng-Chieh Lin, Zhubei City TW
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20120138085 | METHODS AND APPARATUS FOR INTEGRATING AND CONTROLLING A PLASMA PROCESSING SYSTEM - Methods and apparatus for controlling a plasma processing system in a purely pull mode or a hybrid pull mode. In the purely pull mode, the back end assumes master control at least for requesting and scheduling loading of production wafers. In the hybrid pull mode, the back end assumes master control at least for tool maintenance/cleaning while the front end retains master control for production wafers. | 06-07-2012 |
20140361846 | COMMUNICATION DEVICE AND CONTROL METHOD THEREOF - A communication device is provided in the present invention. The communication device comprises an oscillation signal source, a tunable capacitor array, a frame counter; and a control module. The control module is configured to jointly or separately control the tunable capacitor array and the frame counter to compensate a first frequency offset of the oscillation signal source when the communication device operates in a first mode, and to jointly or separately control the tunable capacitor array and the frame counter to compensate a second frequency offset of the oscillation signal source when the communication device operates in a second mode. | 12-11-2014 |
Chia-Ho Lin, Zhubei City TW
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20100278385 | FACIAL EXPRESSION RECOGNITION APPARATUS AND FACIAL EXPRESSION RECOGNITION METHOD THEREOF - A facial expression recognition apparatus and a facial expression recognition method thereof are provided. The facial expression recognition apparatus comprises a gray image generating unit, a face edge detection unit, a motion skin extraction unit, a face contour generating unit and a facial expression recognition unit. The gray image generating unit generates a gray image according to an original image. The face edge detection unit outputs a face edge detection result according to the gray image. The motion skin extraction unit generates a motion skin extraction result according to the original image, and generates a face and background division result according to the motion skin extraction result. The face contour generating unit outputs a face contour according to the gray image, the face edge detection result and the face and background division result. The facial expression recognition unit outputs a facial expression recognition result according to the face contour. | 11-04-2010 |
Chia-Hsiang Lin, Zhubei City TW
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20130075364 | PATTERNING PROCESS AND MATERIALS FOR LITHOGRAPHY - Methods for forming a pattern in a lithography process for semiconductor wafer manufacturing are provided. In an example, a method includes forming a photoresist layer over a material layer; performing a first exposure process on the photoresist layer, thereby forming an exposed photoresist layer having soluble portions and unsoluble portions; treating the exposed photoresist layer, wherein the treating includes one of performing a second exposure process on the exposed photoresist layer and forming an adsorbing chemical layer over the exposed photoresist layer; and developing the exposed and treated photoresist layer to remove the soluble portions of the photoresist layer, wherein the unsoluble portions of the photoresist layer form a photoresist pattern that exposes portions of the material layer. | 03-28-2013 |
20130313121 | Method of Forming Interconnects for Three Dimensional Integrated Circuit - A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer. | 11-28-2013 |
Chia-Huang Lin, Zhubei City TW
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20130150001 | Mobile device - The present invention discloses a mobile phone comprising a gravity sensor, a processor, and a memory. The gravity sensor senses inertia data along a specific direction, the processor couples with the gravity sensor and receives a output signal from the gravity sensor, and the memory stores at least one personal information and operates under the processor's control. When either the gravity sensor or the processor detects a vertical free-fall motion, the processor performs a information security process to lock the personal information to become inaccessible. | 06-13-2013 |
Chia-Jun Lin, Zhubei City TW
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20120117647 | Computer Worm Curing System and Method and Computer Readable Storage Medium for Storing Computer Worm Curing Method - A computer worm curing system includes a string receiving module, a string generating module and a string replying module. The string receiving module receives an infected string, which is generated by a computer worm, from an infected host, which is infected by the computer worm, through a network. The infected string includes a shellcode, and the shellcode is executed utilizing a vulnerable process. The string generating module generates a curing code for curing the computer worm, and replaces the shellcode in the infected string with the curing code to generate a curing string, such that the curing string can be executed utilizing the vulnerable process. The string replying module replies the curing string to the infected host, such that the curing code of the curing string can be executed utilizing the vulnerable process of the infected host to cure the infected host of the computer worm. | 05-10-2012 |
Chie-Iuan Lin, Zhubei City TW
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20140030880 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remove the MG hard mask from the MG stack in the predetermined area. | 01-30-2014 |
Chien-Kuang Lin, Zhubei City TW
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20110276730 | PACKET BASED DATA TRANSFER SYSTEM AND METHOD FOR HOST-SLAVE INTERFACE - In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host. | 11-10-2011 |
Chih-Han Lin, Zhubei City TW
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20130244430 | Double Patterning Method for Semiconductor Devices - A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer. | 09-19-2013 |
20130252425 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate. | 09-26-2013 |
20130320410 | METAL GATE ELECTRODE OF A SEMICONDUCTOR DEVICE - The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode. | 12-05-2013 |
20140001559 | Dummy Gate Electrode of Semiconductor Device | 01-02-2014 |
Chih-Jou Lin, Zhubei City TW
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20130271198 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 10-17-2013 |
20140043082 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 02-13-2014 |
Chih Nan Lin, Zhubei City TW
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20100017628 | Systems for Using Different Power Supply Configurations with a Common Motherboard - In some embodiments, an information handling system may include a motherboard including a processor and memory coupled to the processor; one or more power supply units configured to provide power to the motherboard; and a connection system configured to deliver voltage from the one or more power supply units to the motherboard in both: (a) a first configuration including a single power supply unit providing power to the motherboard; and (b) a second configuration including multiple power supply units providing power to the motherboard. | 01-21-2010 |
Chih-Pao Lin, Zhubei City TW
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20120007784 | INVERTED-F ANTENNA AND WIRELESS COMMUNICATION APPARATUS USING THE SAME - An inverted-F antenna is disclosed including: a radiating body including a plurality of radiating portions, and some of the radiating portions located on a same plane; a shorting element extending outward from the radiating body and forming a first predetermined included angle with one of the radiating portions; a feeding element extending outward from the radiating body and forming a second predetermined included angle with one of the radiating portions; and a protrusion extending outward from the radiating body and forming a third predetermined included angle with one of the radiating portions; wherein at least one of the first, second, and third predetermined included angles is substantially a right angle. | 01-12-2012 |
20130069826 | SWITCHED BEAM SMART ANTENNA APPARATUS AND RELATED WIRELESS COMMUNICATION CIRCUIT - A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth beam adjusting elements; a first, a second, a third, and a fourth beam control modules; a first, a second, a third, and a fourth radiation strips positioned within an area surrounded by the first to eighth beam adjusting elements; and a radiation strip control module for selecting either the first and second radiation strips or the third and fourth radiation strips to transmit signals. When the first beam control module conducts the first and second beam adjusting elements, the third beam control module does not conduct the fifth and sixth beam adjusting elements. When the second beam control module conducts the third and fourth beam adjusting elements, the fourth beam control module does not conduct the seventh and eighth beam adjusting elements. | 03-21-2013 |
20130099974 | SWITCHED BEAM SMART ANTENNA APPARATUS AND RELATED WIRELESS COMMUNICATION CIRCUIT - A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, and a fourth beam adjusting elements substantially perpendicular to a substrate; a radiation strip positioned within an area surrounded by the first to fourth beam adjusting elements and substantially perpendicular to the substrate; a first beam control module positioned between the first beam adjusting element and the substrate; a second beam control module positioned between the second beam adjusting element and the substrate; a third beam control module positioned between the third beam adjusting element and the substrate; and a fourth beam control module positioned between the fourth beam adjusting element and the substrate. When the first beam control module turns on the first beam adjusting element, at least one of the second through the fourth beam control modules turns off corresponding beam adjusting element. | 04-25-2013 |
20140184459 | DUAL BAND ANTENNA - A dual-band antenna, disposed in a substrate, is provided. The dual-band antenna includes: a feeding part and a slot antenna. The feeding part, disposed on a first side of the substrate, is used for feeding electromagnetic signals with a first resonance frequency and a second resonance frequency, wherein the second resonance frequency is substantially equal to twice the first resonance frequency. The slot antenna includes: a rectangular part with two long edges and two short edges, and a funnel part with a bottom edge, a top edge, and two side edges, wherein the bottom edge is shorter than the top edge, and the two side edges are equal in length substantially, the bottom edge of the funnel part is next to a short edge of the rectangular part, and a center line of the slot antenna corresponds to wavelength of the first frequency. | 07-03-2014 |
20140210673 | DUAL-BAND ANTENNA OF WIRELESS COMMUNICATION APPARATUS - A dual-band antenna of a wireless communication apparatus includes a first radiation part for receiving or transmitting signals at a first frequency band; a second radiation part for generating a coupling effect together with the first radiation part to receive or transmit signals at a second frequency band having a center frequency lower than a center frequency of the first frequency band, wherein the second radiation part comprises multiple radiation sections, and at least one of the multiple radiation sections is positioned on a first plane; a feeding element for coupling with a signal receiving terminal of the wireless communication apparatus; and a shorting element for coupling with a fixed-voltage region of the wireless communication apparatus. The first radiation part does not physically contact with the second radiation part, and at least a portion of the first radiation part is not positioned on the first plane. | 07-31-2014 |
Chih-Yen Lin, Zhubei City TW
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20120212951 | LAMP TUBE STRUCTURE AND ASSEMBLY THEREOF - A lamp tube structure includes a first end cap, a second end cap, a heat sink holder, a light emitting element array and a lamp cover. The first end cap includes a pair of electrical terminals and a first insulating portion. The electrical terminals are integrated into the first insulating portion by insert molding, and one end of each electrical terminal is protruded from an outside of the first insulating portion. The second end cap includes a grounding terminal and a second insulating portion. The grounding terminal is integrated into the second insulating portion by insert molding, and one end of the grounding terminal is protruded from an outside of the second insulating portion. The light emitting element array is disposed on top surface of the heat sink holder. A bottom surface of the lamp cover is fixed on the heat sink holder for receiving the light emitting element array. | 08-23-2012 |
20140146570 | DETACHABLE BULB - A detachable bulb includes a lighting source module and a driving module. The lighting source module includes a support plate, a lighting module, a heat sink, and a light-permeable cover. The heat sink has a cavity, a first end, a second end and an engaging slot disposed on an outer periphery thereof. The support plate is secured on the first end of the heat sink. The light-permeable cover disposed on the first end of the heat sink covering the lighting module. The driving module includes a driving body with a socket, a shell, and a power receiving base. The shell is around the driving body and has several engaging parts that detachably engage with the engaging slot. The power receiving base is electrically connected to the driving body. | 05-29-2014 |
Chin-Sheng Lin, Zhubei City TW
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20140217614 | INTEGRATED CIRCUIT FILM AND METHOD OF MANUFACTURING THE SAME - An integrated circuit film and a method of manufacturing the same are disclosed. The integrated circuit film includes a circuit board containing a circuit route; a first set of pads located on a first surface of the circuit board and configured to be applicable to ISO 7816 standard; and a semiconductor device mounted on the circuit board for communicating with at least one of the first set of pads. The first set of pads are arranged in two rows and the semiconductor device is mounted on the circuit board in a space between the two rows of pads. | 08-07-2014 |
20140218171 | INTEGRATED CIRCUIT FILM AND METHOD FOR MANIPULATING THE SAME - An integrated circuit film comprising a circuit board and a control circuit is provided. The circuit board has an IC-installation part and a contact part and having a first surface and a second surface opposite to the first surface. The contact part comprises a first set of pads and a second set of pads. The first set of pads are located on the first surface for communicating with an electrical communication device. The second set of pads are located on the second surface for communicating with a smart card. The control circuit is mounted on the IC-installation part for communicating with the electrical communication device through one of the first set of pads configured in accordance with a single wire protocol (SWP), a communication protocol. | 08-07-2014 |
Chun-Wei Lin, Zhubei City TW
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20130043120 | SPUTTERING TARGET WITH REVERSE EROSION PROFILE SURFACE AND SPUTTERING SYSTEM AND METHOD USING THE SAME - A sputtering target is provided that includes a planar backing plate and a target material formed over the planar backing plate and including an uneven sputtering surface including thick portions and thin portions and configured in conjunction with a sputtering apparatus such as a magnetron sputtering tool with a fixed magnet arrangement. The uneven surface is designed in conjunction with the magnetic fields that will be produced by the magnet arrangement such that the thicker target portions are positioned at locations where target erosion occurs at a high rate. Also provided is the magnetron sputtering system and a method for utilizing the target with uneven sputtering surface such that the thickness across the target to become more uniform in time as the target is used. | 02-21-2013 |
De-Hui Lin, Zhubei City TW
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20110159730 | SOFT HEAD STRUCTURE IN THE DECORATION LAMP STRING - The present invention is to provide an improvement of soft head structure in the decoration lamp string. It mainly is that the soft head is set with two groove rails on the upper and lower wall surfaces of accommodating grooves for laying the conductive wires, and the conductive copper plates in conductive wires are put in the accommodating grooves by a vertical way from the groove rails and snap-clip on the linking grooves of accommodating grooves. Therefore, the combining of conductive wires and soft head can be suitable to be operated through the automatic machinery. | 06-30-2011 |
20110159742 | STRUCTURE OF BULB SOCKET OF DECORATIVE LIGHT STRING - Disclosed is a structure of bulb socket of decorative light string. The socket forms an accommodation chamber for accommodating electrical wires. The accommodation chamber has top and bottom walls respectively forming opposing channels. The electrical wires have conductive plates mounted thereto and the conductive plates are insertable, in a vertical condition, through the channels into the accommodation chamber for being subsequently received and retained in retention slots formed inside the accommodation chamber. This allows the operation of assembling the socket and the electrical wires to be performed automatically with machines. | 06-30-2011 |
20110318954 | SOCKET STRUCTURE OF MINIATURE LIGHT BULB SET - A socket assembly is provided for a miniature light bulb set, including a socket body, a base member that receives power cords set thereon, and a holder that receives and holds a light bulb. The socket body has a bottom portion having front and rear sides forming cord cavities each of which forms a rim to form the structure for positioning and retaining the cord. The base member has left and right sidewalls each forming a retention block that projects outwards and has an increased thickness of material for forming the structure for coupling with the socket body. | 12-29-2011 |
20140273568 | BULB SOCKET HAVING TERMINALS CONNECTED TO A PARTIALLY STRIPPED CORD - A connection seat of bulb socket of decorative lamp string includes a main body having upper and bottom portions. The top portion includes a partition board on which an LED is seated with two terminals on opposite sides of the partition board. The bottom portion has a partition board and two stop boards having inside inclination surfaces. The terminals of the LED are arranged to extend into the bottom portion and positioned against the partition board of the bottom portion. A power cord has two conductors respectively received between the partition board and the stop boards and in engagement with the two terminals of the LED. A bottom cap is mounted to the bottom portion in such a way that two raised bars of the cap push the core conductors to securely fix the core conductors and the terminals of the LED between the partition board and the stop boards. | 09-18-2014 |
20140355277 | CONNECTION DEVICE OF LIGHT RECEPTACLE OF DECORATION LIGHT STRING - A light of a light string includes a receptacle having upper and lower sections. The upper section includes a support plate on which an LED straddles. The lower section includes therein a separation board and two stop boards having a wedge-like shape arranged at each side of the separation board. The pins of the LED extend into the lower section and each positioned against an upright face of the separation board and the stop boards. Metal cores of electrical wires that are partially stripped are received between the stop boards to contact the pins of the LED. A bottom lid having holding board provided thereon is coupled to the lower section, so that the holding boards force the metal cores of the electrical wires into tight engagement with the pins of the LED by being fixed between the separation board and the stop boards. | 12-04-2014 |
20150016125 | ATTACHMENT BASE FOR A LIGHTING UNIT OF A DECORATIVE LIGHTING STRING - The present invention provides an attachment base for a lighting unit of a decorative lighting string comprising an upper base member inserted with an LED lamp and mounted onto an lower base member; the upper base member comprising locking hooks extended downward from two lateral sides of a bottom portion thereon; the lower base member comprising buckle holes adjacent to a bottom portion on two lateral sides corresponding to the locking hooks; characterized in that inner bottom surfaces of rear of the two buckle holes on the lower base member comprise blocking plate; a distance between the blocking plate and the buckle hole is slightly greater than a thickness of the locking hook. With such blocking plates, once the locking hooks are secured onto the buckle hole, the locking hooks abut the blocking plate to prevent the looking hook to disengage from the buckle hole under external forces. | 01-15-2015 |
Diann-Fang Lin, Zhubei City TW
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20110031594 | CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure that comprises a conductive base. An adhesive layer is formed on the conductive base. An electronic element is formed on the adhesive layer. Conductors form a signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors. | 02-10-2011 |
20110031607 | CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure comprising a conductive base. An adhesive layer is formed on the conductive base. An electronic element is formed on the adhesive layer. Conductors are forming signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors. | 02-10-2011 |
20110108977 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material. | 05-12-2011 |
20110180891 | CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure comprising an optical sensor element. A filling material is filled around the optical sensor element. At least one conductor element is formed through the filling material from top side to the back side for signal connection. A redistribution layer is formed on the at least one conductor element and coupled to die pad of the optical sensor element. A transparent material is formed on the redistribution layer. | 07-28-2011 |
20110193216 | PACKAGE STRUCTURE - The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes an dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying with the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material. | 08-11-2011 |
20110209908 | CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure comprising a redistribution layer. An adhesive layer is formed on the redistribution layer. An electronic element is formed on the adhesive layer. Conductors are forming signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors. | 09-01-2011 |
Fang Lin, Zhubei City TW
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20150054142 | Wafer Surface Conditioning for Stability in Fab Environment - Hydroxyl moieties are formed on a surface over a semiconductor substrate. The surfaces are silylized to replace the hydroxyl groups with silyl ether groups, the silyl ether groups being of the form: —OSiR | 02-26-2015 |
Hao-Wu Lin, Zhubei City TW
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20130019949 | COMPOUNDS FOR ORGANIC THIN-FILM SOLAR CELLS AND ORGANIC THIN-FILM SOLAR CELLS - Provided are compounds with a donor moiety, a first acceptor moiety and a second acceptor moiety, as shown by Formula (I): | 01-24-2013 |
20140261658 | ORGANIC SOLAR CELL - An organic solar cell includes a conductive substrate, an organic material, and two metal layers. The conductive substrate includes an electrode. The organic material is disposed above the conductive substrate. The metal layers are disposed above the organic material, and a gap is configured between the two metal layers. The width of the gap is between 1 nm and 5000 nm. | 09-18-2014 |
20150060119 | CONDUCTIVE STRUCTURE AND MANUFACTURING METHOD THEREOF - A conductive structure comprises a plurality of first nanowires and a plurality of second nanowires. The first nanowires extend along a first direction substantially. The second nanowires extend along a second direction substantially, and at least a part of the second nanowires electrical connect to the first nanowires. The included angle between the first and second directions is nonzero. A manufacturing method of the conductive structure is also disclosed. | 03-05-2015 |
Heng-Kuang Lin, Zhubei City TW
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20120292663 | Structure and Method for Monolithically Fabrication Sb-Based E/D Mode MISFETs - The invention provides two Sb-based n- or p-channel layer structures as a template for MISFET and complementary MISFET development. Four types of MISFET devices and two types of complementary MISFET circuit devices can be developed based on the invented layer structures. Also, the layer structures can accommodate more than one complementary MISFETs and more than one single active MISFETs to be integrated on the same substrate monolithically. | 11-22-2012 |
20130075822 | STRUCTURES AND METHODS OF SELF-ALIGNED GATE FOR SB-BASED FETS - The advantage of narrow-bandgap Sb-based devices is the realization of high-frequency operation with much lower power consumption. However, some properties such as chemical stability are the key issues for developing Sb-based devices. The process temperature of the ion implant and thermal annealing in conventional silicon industry is over 1000° C. Sb-based materials are easily degraded at temperature greater 300° C. Thus, this invention provides three processes for self-aligned gate with lower process temperature (<300° C.) to reduce device access region resistance and maintain material quality. | 03-28-2013 |
Hsi-Chien Lin, Zhubei City TW
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20120112329 | CHIP PACKAGE - An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof. | 05-10-2012 |
20130154077 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad. | 06-20-2013 |
Hsien Chang Lin, Zhubei City TW
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20120306812 | TOP-EMITTING OLED DISPLAY HAVING TRANSPARENT TOUCH PANEL - A top-emitting OLED display having a transparent touch panel includes a substrate, an upper cover plate, an OLED device, a capacitive touch device, and a protective layer. The OLED device is stacked on the substrate, and the capacitive touch device is stacked on upper surface of the upper cover plate. The capacitive touch device includes a capacitor structure which is composed of a first transparent conductive layer, an isolating layer, and a second transparent conductive layer. The protective layer is disposed on top of the capacitor structure. | 12-06-2012 |
Hsien-Keng Lin, Zhubei City TW
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20140218323 | TOUCH DETECTION METHOD AND ASSOCIATED APPARATUS - A method for touch detection is provided for detecting a touch point on a display device. The method includes: providing a display signal, according to which the display device has two parts of a vertical blanking interval within each frame period, wherein the two parts of the vertical blanking interval are discontinuous; and performing a touch detection in the two parts of the vertical blanking interval, respectively. The touch detection method is capable of performing multiple touch detections within one frame period. | 08-07-2014 |
20140292715 | SELF-CAPACITIVE TOUCH PANEL - A self-capacitive touch panel including two sensing regions is provided. Each of the sensing regions includes a first sensing channel, a second sensing channel, a border electrode and multiple central electrodes. The border electrode utilizes the first sensing channel exclusively. The central electrodes share the second sensing channel. The border electrode has a first centroid, which represents a position where a capacitance change contributed by the border electrode occurs. The central electrodes have a second centroid, which represents a position where a capacitance change contributed by the central electrode occurs. An average distance from the first centroid to all possible touch points in the border electrodes is shorter than an average distance from the second centroid to all possible touch points in the central electrodes. | 10-02-2014 |
Hsien-Ming Lin, Zhubei City CN
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20130001949 | KINETIC ENERGY GENERATION DEVICE - A kinetic energy generation device includes a rotation mechanism, a speed increaser coupled to the rotation mechanism, and a power generation element coupled to the speed increaser. The rotation mechanism includes a central shaft and an outer circumferential zone surrounding the central shaft. The outer circumferential zone receives therein partition plates set in radial direction and spaced from each other so that the partition plates show upward inclination. The central shaft is rotatably coupled to the speed increaser, and the speed increaser is coupled to the power generation element so as to constitute the kinetic energy generation device. The rotation mechanism is arranged under a water flow in order to allow each of the receiving zones to receive a weight of water, so that the weight of water causes the rotation mechanism to rotate in a given direction and thus drives the speed increaser to generate electrical power. | 01-03-2013 |
Hsiu-Jen Lin, Zhubei City TW
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20120178251 | METHOD OF FORMING METAL PILLAR - The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar. | 07-12-2012 |
20120299181 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film. | 11-29-2012 |
20130009307 | Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers - A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed. | 01-10-2013 |
20130062761 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 03-14-2013 |
20130099371 | SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent. | 04-25-2013 |
20130099385 | Packages and Methods for Forming the Same - A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size. | 04-25-2013 |
20130115735 | Apparatus and Methods for Molded Underfills in Flip Chip Packaging - Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed. | 05-09-2013 |
20130122652 | Methods for Performing Reflow in Bonding Processes - A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region. | 05-16-2013 |
20130143364 | METHOD OF PROCESSING SOLDER BUMP BY VACUUM ANNEALING - A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate. | 06-06-2013 |
20130181338 | Package on Package Interconnect Structure - A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer. | 07-18-2013 |
20130214401 | System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. | 08-22-2013 |
20130285238 | STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES - A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. | 10-31-2013 |
20130334561 | METHOD FOR BONDING LED WAFER, METHOD FOR MANUFACTURING LED CHIP AND BONDING STRUCTURE - A method for bonding an LED wafer, a method for manufacturing an LED chip, and a bonding structure are provided. The method for bonding an LED wafer includes the following steps. A first metal film is formed on an LED wafer. A second metal film is formed on a substrate. A bonding material layer whose melting point is lower than or equal to about 110° C. is formed on the surface of the first metal film. The LED wafer is placed on the substrate. The bonding material layer is heated at a pre-solid reaction temperature for a pre-solid time to perform a pre-solid reaction. The bonding material layer is heated at a diffusion reaction temperature for a diffusing time to perform a diffusion reaction, wherein the melting points of the first and the second inter-metallic layers after diffusion reaction are higher than about 110° C. | 12-19-2013 |
20140027431 | Warpage Control in the Packaging of Integrated Circuits - A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component. | 01-30-2014 |
20140151878 | System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. | 06-05-2014 |
20140159233 | PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate. | 06-12-2014 |
20140193952 | Methods for Metal Bump Die Assembly - Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating. | 07-10-2014 |
20140264856 | Package-on-Package Structures and Methods for Forming the Same - A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. | 09-18-2014 |
20140367867 | Packaging Methods and Packaged Semiconductor Devices - An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux. | 12-18-2014 |
20150044819 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 02-12-2015 |
Hui-Min Lin, Zhubei City TW
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20130119444 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess. | 05-16-2013 |
20140021517 | Semiconductor Device and Fabrication Method Thereof - A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance. | 01-23-2014 |
I-Liang Lin, Zhubei City TW
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20110238397 | METHOD AND APPARATUS FOR TRANSACTION RECORDING AND VISUALIZATION - Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time. | 09-29-2011 |
Jen-Chieh Lin, Zhubei City TW
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20110291054 | POLYMERIC FUSED THIOPHENE SEMICONDUCTOR FORMULATION - A formulation including: | 12-01-2011 |
Jium Ming Lin, Zhubei City TW
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20110009926 | Nerve-Stimulating And Signal-Monitoring Device And Method Of Manufacturing The Same And Nerve-Stimulating And Signal-Monitoring System - A nerve-stimulating and signal-monitoring device includes a flexible substrate, a modulation/demodulation module, a SOC unit and a plurality of stimulation probes. The modulation/demodulation module demodulates coded nerve-stimulating radio-frequency signals or modulates sending coded epidermal nerve response signals. The SOC unit and the modulation/demodulation module can be integrally packaged and bonded on the flexible substrate. The SOC unit decodes and transforms the coded nerve-stimulating radio-frequency signals to obtain nerve-stimulating electrical probe-driving signals. The stimulation probes protrude from the flexible substrate, are configured to transmit the nerve-stimulating electrical probe-driving signals to epidermal nerves, and are electrically coupled to the SOC unit. The SOC unit can receive, amplify, analyze, classify and encode epidermal nerve response signals sent to the modulation/demodulation module for modulating, and such coded epidermal nerve response signals are subsequently transmitted by an antenna to the monitor station for decoding, monitoring and analysis. | 01-13-2011 |
20110100123 | Thermal Bubble Type Angular Accelerometer - An RFID, Bluetooth as well as zigbee based thermal bubble type angular accelerometer includes a flexible substrate, a base layer, at least one cavity, and at least one sensing assembly. The base layer is formed on the flexible substrate. The at least one cavity is formed on the base layer. The at least one sensing assembly is suspended over the at least one cavity. The sensing assembly comprises a heater and two temperature sensing elements, wherein the two temperature sensing elements are substantially symmetrically disposed on opposite sides of the heater, and the heaters and the two temperature sensing elements extend in a radial direction. | 05-05-2011 |
Jiu-Nan Lin, Zhubei City TW
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20100117271 | Process for producing zinc oxide varistor - A process for producing zinc oxide varistors is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintering material through two independent procedures, so that the doped zinc oxide and the high-impedance sintering material are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess one or more of varistor properties, thermistor properties, capacitor properties, inductor properties, piezoelectricity and magnetism. | 05-13-2010 |
Jui-Lung Lin, Zhubei City TW
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20110261878 | BIT RATE CONTROL METHOD AND APPARATUS FOR IMAGE COMPRESSION - Method and apparatus of bit rate control for image compression are provided. The method includes the following steps. With respect to a color channel, image complexity of spatial domain image data of an image is obtained according to the spatial domain image data. A scale factor with respect to the color channel is estimated according to the image complexity and a target bit rate. During image compression of the image, frequency domain image data of the image is quantized according to the estimated scale factor. | 10-27-2011 |
Jun Nan Lin, Zhubei City TW
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20080286898 | Material composition having core-shell microstructure used for varistor - A material composition having a core-shell microstructure suitable for manufacturing a varistor having outstanding electrical properties, the core-shell microstructure of the material composition at least comprising a cored-structure made of a conductive or semi-conductive material and a shelled-structure made from a glass material to wrap the cored-structure, and electrical properties of the varistors during low temperature of sintering process can be decided and designated by precisely controlling the size of the grain of the cored-structure and the thickness and insulation resistance of the insulating layer of the shelled-structure of material composition. | 11-20-2008 |
Lai-Ching Lin, Zhubei City TW
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20140022006 | SWITCH CIRCUIT AND CHARGE PUMP USING THE SAME THEREOF - The switch circuit comprises a first switch, a second switch, a third switch, a forth switch, a fifth switch, a sixth switch and a seventh switch. The first switch couples the voltage input terminal to one terminal of a flying capacitor. The second switch couples one terminal of the flying capacitor to one terminal of the output capacitor. The third switch couples one terminal of the flying capacitor to a common terminal. The fourth switch couples the other terminal of the flying capacitor to one terminal of the output capacitor. The fifth switch couples one terminal of the output capacitor to a positive voltage output terminal. The sixth switch couples the other terminal of the flying capacitor to the common terminal. The seventh switch couples the other terminal of the flying capacitor to a negative voltage output terminal. | 01-23-2014 |
Lawrence Lin, Zhubei City TW
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20100155963 | DUMMY VIAS FOR DAMASCENE PROCESS - An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer. | 06-24-2010 |
Long-Shih Lin, Zhubei City TW
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20140008723 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE WITH LOW PARASITIC BJT GAIN AND STABLE THRESHOLD VOLTAGE - A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure. | 01-09-2014 |
20140159103 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed. | 06-12-2014 |
20140231964 | Multiple Layer Substrate - A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration. | 08-21-2014 |
20140322871 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device. | 10-30-2014 |
Mei-Wei Lin, Zhubei City TW
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20140170250 | PHARMACEUTICAL COMPOSITIONS AND METHOD FOR INHIBITING ANGIOGENESIS - The disclosure provides a pharmaceutical composition for inhibiting angiogenesis, including an effective amount of an extract of | 06-19-2014 |
Meng Yong Lin, Zhubei City TW
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20140145734 | Capacitor Sensing Circuit - The present invention provides a capacitor sensing circuit, comprising a driving unit, a switching unit, a differential integrator circuit, and a post-processing circuit. The driving unit is for providing driving signals and timing required by the capacitor sensing circuit, the switching unit switches signals according to two inverting timings, φ | 05-29-2014 |
Ming-Tsun Lin, Zhubei City TW
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20130170211 | ASSEMBLED TYPE LAMP WALL - An assembled type lamp wall comprises a base, at least one fastening holder and at least one lamp panel, wherein the fastening holder has a fitting portion provided for joining the base and a bottom portion that is stably in contact with ground. The fitting portion of the fastening holder is disposed with at least one screw through hole. The base has a plurality of screw holes aligning the at least one screw through hole and respectively and circularly disposed at a location of joining the fastening holder so that the several lamp panels can be horizontally extended and arranged on the base, and other screw holes align the screw through holes on the fastening holder, and a purpose of easily regulating the lamp panels | 07-04-2013 |
20130340338 | Hydroponic Device for Liquid Supply - The present invention is to provide a hydroponic device for liquid supply, which includes a plate, a bottle and a pump. The plate has an open space for filing liquid therein, and a diversion panel is mounted in the open space to separate a first flume, a second flume and a connection set. The bottle pours the liquid (e.g. culture solution) slowly into the plate via breaking through the surface tension of water. The motor is connected to the second flume and the connection set to pump the liquid, and the first flume introduces the liquid into the second flume through the connection set, to form a circulating fluid loop. As such, the present invention achieves the purposes of reducing the losses of water and nutrient for hydroponic culture such that the liquid can be utilized repeatedly via flowing through the circulating loop to accelerate the growing of plants. | 12-26-2013 |
20140000163 | WATER CULTURE HYDROPONICS SYSTEM | 01-02-2014 |
20140069009 | HYDROPONIC CIRCULATION LIQUID SUPPLY DEVICE - A hydroponic circulation liquid supply device is composed of a tray body, a liquid supply platform and a motor. The tray body has a containing space for disposing a liquid supply platform. The liquid supply platform is formed with a liquid supply region and a guide passage region communicating with each other by disposing a first rib. The liquid supply region is disposed with a plurality of second ribs to form a liquid supply passage. A water collection region is further disposed in the tray body. The liquid supply region and the guide passage region have a section difference plane. The motor is engaged with the water collection region and the liquid supply region respectively to form a flowing circulation loop of transporting culture liquid, and the flowing speed of culture liquid can be slowed down. | 03-13-2014 |
Mong-Ea Lin, Zhubei City TW
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20130048941 | SOLID STATE LIGHT EMITTING SEMICONDUCTOR STRUCTURE AND EPITAXY GROWTH METHOD THEREOF - A solid state light emitting semiconductor structure and an epitaxy growth method thereof are provided. The method includes the following steps: A substrate is provided. A plurality of protrusions separated from each other are formed on the substrate. A buffer layer is formed on the protrusions, and fills or partially fills the gaps between the protrusions. A semiconductor epitaxy stacking layer is formed on the buffer layer, wherein the semiconductor epitaxy stacking layer is constituted by a first type semiconductor layer, an active layer and a second type semiconductor layer in sequence. | 02-28-2013 |
20130062634 | SOLID STATE LIGHT SOURCE MODULE AND ARRAY THEREOF - A solid state light source array including a transparent substrate and N rows of solid state light emitting element series is provided. Each row of the solid state light emitting element series includes M solid state light emitting elements connected in series, wherein N, M are integrals and N≧1, M≧2. Each of the solid state emitting elements includes a first type electrode pad and a second type electrode pad. The first and the M | 03-14-2013 |
20130095591 | MANUFACTURING METHOD OF SOLID STATE LIGHT EMITTING ELEMENT - A manufacturing method of a solid state light emitting element is provided. A plurality of protrusion structures separated to each other are formed on a first substrate. A buffer layer is formed on the protrusion structures and fills the gaps between protrusion structures. An epitaxial growth layer is formed on the buffer layer to form a first semiconductor stacking structure. The first semiconductor stacking structure is inverted to a second substrate, so that the first semiconductor epitaxial layer and the second substrate are connected to form a second semiconductor stacking structure. The buffer layer is etched by a first etchant solution to form a third semiconductor stacking structure. A second etchant solution is used to permeate through the gaps between the protrusion structures, so that the protrusion structures are etched completely. The first substrate is removed from the third semiconductor stacking structure to form a fourth semiconductor stacking structure. | 04-18-2013 |
20140070241 | SOLID STATE LIGHT SOURCE ARRAY - A solid state light source array including a transparent substrate and N rows of solid state light emitting element series is provided. Each row of the solid state light emitting element series includes M solid state light emitting elements connected in series, wherein N, M are integers and N≧1, M≧2. Each of the solid state emitting elements includes a first type electrode pad and a second type electrode pad. The first and the M | 03-13-2014 |
Pao-Chuan Lin, Zhubei City TW
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20130148383 | DC-AC CONVERTER AND CONVERSION CIRCUIT - A DC-AC converter is provided. The DC-AC converter includes a time-varying DC power generating circuit, an AC power generating circuit and a transmission capacitor. The time-varying DC power generating circuit is controlled by a pulse width modulation (PWM) signal to transform a DC source into a time-varying DC power. With reference to the time-varying DC power, the AC power generating circuit is controlled by a first polarity switching and a second polarity switching signal to generate an AC power. The transmission capacitor, coupled to the time-varying DC power generating circuit and the AC power generating circuit, transmits the time-varying DC power from the time-varying DC generating circuit to the AC power generating circuit. | 06-13-2013 |
Pao-Hung Lin, Zhubei City TW
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20110149622 | Interleaved Bridgeless Power Factor Corrector and Controlling Method thereof - In an interleaved bridgeless power factor corrector and a controlling method thereof, the interleaved bridgeless power factor corrector includes an AC input power supply, two input inductors, four active components, two passive components, an output capacitor, and an output resistor, wherein the four active components are cascaded in a full bridge form to act as control switches and rectifying switches having different phases; besides, the interleaved bridgeless power factor corrector is connected to a control signal processor and a control circuit, which can output complementary switch signals to control the interleaved bridgeless power factor corrector, thereby achieving output/input ripple cancellation and frequency multiplication. | 06-23-2011 |
Ping-Yuan Lin, Zhubei City TW
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20140061444 | Proximity Sensor Package and Packing Method Thereof - A proximity sensor package and a packaging method thereof are disclosed. The proximity sensor package includes a light emitting unit and a light sensor. The light sensor has a first surface having a light sensing area. The light emitting unit is disposed on the first surface of the light sensor outside the light sensing area. | 03-06-2014 |
20140097451 | PROXIMITY SENSOR AND CIRCUIT LAYOUT METHOD THEREOF - A proximity sensor and a circuit layout method thereof are disclosed. The proximity sensor includes a light sensor and a light emitting unit. The light sensor includes a semiconductor substrate and a bonding pad. The semiconductor substrate has a first circuit region. At least one semiconductor device is disposed in the first circuit region. The bonding pad is disposed above the first circuit region and a gap is existed between the bonding pad and the at least one semiconductor device. The bonding pad is connected to the semiconductor substrate out of the first circuit region. The light emitting unit is disposed on the bonding pad of the light sensor. | 04-10-2014 |
20140131551 | PROXIMITY SENSOR AND OPERATING METHOD THEREOF - A proximity sensor includes a proximity sensing unit and a signal processing unit. The proximity sensing unit detects whether an object to be detected is close by to obtain a measured value. The signal processing unit compares the measured value with an initial noise cross-talk value to determine whether the initial noise cross-talk value should be updated. If the determined result of the signal processing unit is no, the signal processing unit compares the measured value with a default value to determine whether the object to be detected is located in a detection range of the proximity sensing unit. | 05-15-2014 |
20140374866 | Photo Sensing Chip Having a Plurality of Photo Sensors and Manufacturing Method Thereof - A photo sensing chip and a manufacturing method thereof are disclosed. The photo sensing chip includes a silicon substrate and a plurality of photo sensors formed on the silicon substrate. The photo sensors include a first photo sensor and a second photo sensor. The first photo sensor has a first P-N junction and a first depletion region is formed at first P-N junction for receiving a first light band of an incident light to generate a first photo current. The second photo sensor has a second P-N junction and a second depletion region is formed at second P-N junction for receiving a second light band of the incident light to generate a second photo current. A first process parameter corresponds to the first depletion region and a second process parameter corresponds to the second depletion region, wherein the first process parameter and the second process parameter are different. | 12-25-2014 |
20150048374 | Light Sensor and Manufacturing Method Thereof - A light sensor and a manufacturing method thereof are disclosed. The light sensor is capable of being coupled to a carry object and includes a sensing chip and a plurality of conductive connecting elements. The sensing chip includes a first surface and a second surface opposite to each other. The sensing chip also includes a sensing unit disposed between the first surface and the second surface and at least partially exposed by a window formed on the second surface. The first surface faces the carry object when the light sensor is coupled to a carry object. The conductive connecting elements are disposed on the first surface and coupled to the sensing unit in order to couple the light sensor to the carry object. | 02-19-2015 |
Shih-Chin Lin, Zhubei City TW
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20130003481 | HIDDEN REFRESH METHOD AND OPERATING METHOD FOR PSEUDO SRAM - In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation. | 01-03-2013 |
Shih-Yao Lin, Zhubei City TW
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20100215873 | SYSTEM FOR DISPLAY IMAGES AND FABRICATION METHOD OF DISPLAY PANELS - A system for displaying images including a display panel and a fabrication method of a display panel are provided. The display panel includes a first substrate and a second substrate opposite to the first substrate, wherein a total thickness of assembling the first and the second substrates is reduced by a thinning process, and by utilizing an acrylic-based or an epoxy acrylic-based polymer film to cover the outer surfaces of the first and the second substrates. | 08-26-2010 |
Shin-Ping Lin, Zhubei City TW
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20110167216 | Redundant array of independent disks system - A Redundant Array of Independent Disks (RAID) system is disclosed in this invention. The RAID system includes a plurality of data storage units and a parity storage medium. The parity storage medium can be singular storage hardware or a logical storage module including multiple storage units. The parity storage medium cooperates with the data storage units to form a RAID. The parity storage medium is used for storing parity information of the RAID. A first write speed of the parity storage medium is faster than a second write speed of each data storage unit. | 07-07-2011 |
Shyue-Shyh Lin, Zhubei City TW
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20110291200 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure. | 12-01-2011 |
20120240088 | SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS - A method of designing an integrated circuit includes defining at least one dummy layer covering at least one of a portion of a first metallic layer and a portion of a second metallic layer of an integrated circuit. The second metallic layer is disposed over the first metallic layer. The first metallic layer, the second metallic layer and a gate electrode of the integrated circuit have a same routing direction. A logical operation is performed to a file corresponding to the at least one of the portion of the first metallic layer and the portion of the second metallic layer covered by the dummy layer so as to size at least one of the portion of the first metallic layer and the portion of the second metallic layer. | 09-20-2012 |
20120280287 | Integrated Circuit Layouts with Power Rails under Bottom Metal Layer - A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer. | 11-08-2012 |
20120313256 | Non-Hierarchical Metal Layers for Integrated Circuits - An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. | 12-13-2012 |
20120331426 | CELL ARCHITECTURE AND METHOD - A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks. | 12-27-2012 |
20130157452 | SEMICONDUCTOR DEVICE INCLUDING POLYSILICON RESISTOR AND METAL GATE RESISTOR AND METHODS OF FABRICATING THEREOF - A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. | 06-20-2013 |
20130256902 | INTERCONNECT STRUCTURE HAVING SMALLER TRANSITION LAYER VIA - An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via. | 10-03-2013 |
20130328131 | Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors - Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor. | 12-12-2013 |
20140061817 | Hybrid Gate Process for Fabricating FinFET Device - Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches. | 03-06-2014 |
Sung-Chieh Lin, Zhubei City TW
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20110273949 | ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME - A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse. | 11-10-2011 |
20120020177 | ELECTRICAL FUSE MEMORY - Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row. | 01-26-2012 |
20120038410 | CIRCUIT AND METHOD FOR CHARACTERIZING THE PERFORMANCE OF A SENSE AMPLIFIER - An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current. | 02-16-2012 |
20120057423 | ELECTRICAL FUSE MEMORY ARRAYS - Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column. | 03-08-2012 |
20120086495 | VOLTAGE LEVEL SHIFTER - An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node. | 04-12-2012 |
20120212993 | ONE TIME PROGRAMMING BIT CELL - A one time programming (OTP) memory cell includes a first transistor and a second transistor. The first transistor has a first drain, a first source, a first gate, and a first normal operational voltage value higher that a second normal operational voltage value of the second transistor. The second transistor has a second drain, a second source, and a second gate. The first source is coupled to the second drain. The second source is configured to detect data stored in the OTP memory cell. | 08-23-2012 |
20120257435 | NON-SALICIDE POLYSILICON FUSE - The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage. | 10-11-2012 |
20130038375 | VOLTAGE LEVEL SHIFTER - A circuit includes a power switch and a level shifter. The level shifter has a node and an assistant circuit. The node is configured to control the power switch. The assistant circuitry is coupled to the node and configured for the node to receive a first voltage value through the assistant circuit. The first voltage value is different from a second voltage value of an input signal received by the level shifter. | 02-14-2013 |
20130039117 | ELECTRICAL FUSE BIT CELL - An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal. The eFuse has a first end and a second end. The first end, the first program terminal, and the second read terminal are coupled together. The read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode. The program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode. | 02-14-2013 |
20130100756 | ELECTRICAL FUSE MEMORY ARRAYS - A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resisivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses. | 04-25-2013 |
20130107603 | CIRCUIT AND METHOD FOR GENERATING A READ SIGNAL | 05-02-2013 |
20130155799 | ELECTRICAL FUSE MEMORY - A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on. | 06-20-2013 |
20130221995 | SENSE AMPLIFIER - An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device. | 08-29-2013 |
20130256801 | INTEGRATED CIRCUIT STRUCTURE TO RESOLVE DEEP-WELL PLASMA CHARGING PROBLEM AND METHOD OF FORMING THE SAME - During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW. | 10-03-2013 |
20130262962 | MEMORY ERROR CORRECTION - In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word. | 10-03-2013 |
20130272080 | METHOD AND APPARATUS FOR BIT CELL REPAIR - A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell. | 10-17-2013 |
20130301374 | WORD LINE DRIVER HAVING A CONTROL SWITCH - A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse. | 11-14-2013 |
20140061851 | METAL-VIA FUSE - The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window. | 03-06-2014 |
20140369105 | GENERATING OUTPUT SIGNAL DURING READ OPERATION - A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell. | 12-18-2014 |
Tung-Sheng Lin, Zhubei City TW
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20140075263 | ERROR CORRECTION APPARATUS AND ASSOCIATED METHOD - An error correction apparatus for a digital signal received by a signal reception terminal includes two error correction modules. The first error correction module performs first error correction on an input signal to generate an intermediate signal satisfying a termination condition. The second error correction module receives and selectively performs second error correction on the intermediate signal to generate a corrected signal. The termination condition is associated with a maximum error correction capability of the second error correction. | 03-13-2014 |
Tzu-Chen Lin, Zhubei City TW
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20120306459 | Power Factor Correction Circuit, Control circuit Therefor and Method for Driving Load Circuit through Power Factor Correction - The present invention discloses a power factor correction circuit, a control circuit therefor and a method for driving a power factor correction circuit. The power factor correction circuit receives rectified power obtained by rectifying AC power, and corrects the power factor thereof. The power factor correction circuit includes an inductor, and it generates a reference signal as a limit for the inductor current. The reference signal is proportional to Comp/Vin, wherein Comp is a signal relating to a feedback signal, and Vin is a voltage signal relating to the AC power or the rectified power. | 12-06-2012 |
Tzu-Han Lin, Zhubei City TW
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20120205695 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode device is provided, including a submount, a light-emitting diode (LED) chip mounted on the submount, a first transparent insulating layer formed on the submount and the LED chip, a transparent conductive layer formed on the first transparent insulating layer, a phosphor layer formed on the first transparent conductive layer covering the LED chip, and a transparent passivation layer formed on the phosphor layer and over the transparent conductive layer. | 08-16-2012 |
Tzu-Hung Lin, Zhubei City TW
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20120126368 | Semiconductor Package - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer | 05-24-2012 |
20120267779 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3. | 10-25-2012 |
20130087911 | INTEGRATED CIRCUIT PACKAGE STRUCTURE - An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip. | 04-11-2013 |
20130161810 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace. | 06-27-2013 |
20130168857 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs. | 07-04-2013 |
20130256878 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view. | 10-03-2013 |
20140035095 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 02-06-2014 |
20140091481 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die. | 04-03-2014 |
20140127865 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed. | 05-08-2014 |
20140151867 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 06-05-2014 |
20140191396 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. | 07-10-2014 |
20140377913 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed. | 12-25-2014 |
20150035131 | CHIP PACKAGE - According to an embodiment of the present invention, a chip package is provided. The chip package includes a substrate. A chip is disposed on the substrate. A stiffener is disposed on the substrate. The thermal conductivity of the stiffener is higher than the thermal conductivity of the substrate. | 02-05-2015 |
Wei-Chi Lin, Zhubei City TW
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20110248943 | Touch Panel - A touch panel is provided. The touch panel having a pixel area and a sensing area includes a first substrate and an opposite second substrate. A press sensing spacer is disposed on the sensing area of the first substrate. A press sensing stage is disposed on the sensing area of the second substrate, corresponding to the press sensing spacer. An alignment layer is disposed over the second substrate, covering the press sensing stage and the pixel area of the second substrate. In an embodiment, the height of the press sensing stage is greater than the height from the surface of the second substrate at the pixel area to the bottom of the alignment layer by at least 0.05 μm. | 10-13-2011 |
Wei Fen Lin, Zhubei City TW
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20120176326 | CONTROL DEVICE FOR TOUCH PANEL AND SIGNAL PROCESSING METHOD THEREOF - The present invention discloses a control device for a touch panel. The touch panel comprises a plurality of X-directional sensing lines and a plurality of Y-directional sensing lines arranged in a staggered manner. The control device comprises a clock generation circuit, a selection module, an analog to digital conversion circuit, and a control unit. The selection module selects sensing lines to be measured from the X-directional sensing lines and Y-directional sensing lines. The control unit controls the operation mode of the analog to digital conversion circuit. The analog to digital conversion circuit outputs an n-bit digital signal when it operates in a normal mode, and outputs an m-bit digital signal when it operates in a detecting mode, wherein n>m. According to the control device of the present invention, valid data is output in the presence of noise. | 07-12-2012 |
Wei-Hsun Lin, Zhubei City TW
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20140253162 | INTEGRATED CIRCUIT TEST SYSTEM AND METHOD - A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module. | 09-11-2014 |
20140266273 | TEST-YIELD IMPROVEMENT DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENTING THE SAME - A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head. | 09-18-2014 |
Wen Chi Lin, Zhubei City TW
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20130057484 | LIQUID CRYSTAL DISPLAY WITH DETACHABLE TOUCH SENSOR - A liquid crystal display according to the present disclosure is provided. The liquid crystal display includes a frame, a backlight module, a plurality of hooking members, an LCD panel, and a touch sensor. According to the liquid crystal display of the present disclosure, wherein the hooking members on the frame may secure the touch sensor or the LCD panel on the backlight module without need of using double-sided tapes or optical adhesive. | 03-07-2013 |
Wen-Hsiane Lin, Zhubei City TW
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20120311250 | ARCHITECTURE AND ACCESS METHOD OF HETEROGENEOUS MEMORIES - A heterogeneous memory architecture includes a first memory, a second memory and a memory controller. The first memory has a first memory space. The second memory has a second memory space larger than the first memory space. The memory controller is used for accessing common address space of the first memory and the second memory in a 2X-bit bandwidth, and for disabling the first memory and accessing non-common address space of the second memory in opposite to the first memory in a X-bit bandwidth, X being a positive integer. | 12-06-2012 |
Yan-Fu Lin, Zhubei City TW
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20110304042 | Copper Bump Structures Having Sidewall Protection Layers - A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer. | 12-15-2011 |
20120025368 | Semiconductor Device Cover Mark - A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate. | 02-02-2012 |
Yi-Hsin Lin, Zhubei City TW
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20120140128 | LIQUID CRYSTAL LENS STRUCTURE AND METHOD OF DRIVING SAME - A liquid crystal (LC) lens structure and a method of driving same are disclosed. The LC lens structure includes an upper substrate, a lower substrate, a liquid crystal and polymer composite film, and an LC layer. The upper substrate is provided with a first conducive layer and a first alignment layer; and the lower substrate is provided with a second conductive layer and a second alignment layer. The liquid crystal and polymer composite film is arranged at one side of the first alignment layer to form a first lens, and the LC layer is arranged between the liquid crystal and polymer composite film and the second alignment layer to form a second lens. By building the liquid crystal and polymer composite film in the LC lens structure, it is able to realize an LC lens with low operating voltage and large focusing range. | 06-07-2012 |
20140218674 | LIQUID CRYSTALLINE POLYMER LENS STRUCTURE - A liquid crystalline polymer lens structure includes a refractive index distribution film, a lens and a flexible substrate. The flexible substrate is laminated on the surface of the lens, and the refractive index distribution film is encapsulated inside the flexible substrate. The refractive index distribution film has a non-uniform refractive index distribution, and can design to make the liquid crystalline polymer lens structure have multi-segment or gradual variation of optical power, so as to improve the presbyopia's reading ability. | 08-07-2014 |
Ying-Shiou Lin, Zhubei City TW
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20110309443 | METHOD FOR CONTROLLING IMPURITY DENSITY DISTRIBUTION IN SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MADE THEREBY - The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern. | 12-22-2011 |
Yu-Jen Lin, Zhubei City TW
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20130241760 | OBJECT DETECTION DEVICE AND METHOD THEREOF - An object detection device includes a RF emitter composed of a RF emitting module and an emitter antenna for emitting an EM wave, a RF receiver composed of a RF receiving module and a RF antenna for receiving a reflected EM wave by a predetermined object and a processor connected to the RF emitter and the RF receiver to process the received reflected EM wave so as to obtain a received signal strength indicator (RSSI) such that existence of the object is determined based on fluctuation of the RSSI when compared with a predetermined threshold value. | 09-19-2013 |
Yung-Cheng Lin, Zhubei City TW
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20120038332 | LINEAR VOLTAGE REGULATOR AND CURRENT SENSING CIRCUIT THEREOF - A linear regulator and a current sensing circuit are provided. The linear regulator comprises a pass transistor, a compensation capacitor, a variable resistor, an error amplifier and a current sensing circuit comprising a sense transistor controlled by the error amplifier and a voltage follower coupled with the second terminal of the pass transistor and the second terminal of the sense transistor. The sense transistor receives an input voltage, and generates a sense current proportional to a pass current. The voltage follower controls the voltage at the second terminal of the sense transistor to be the same as that at the second terminal of the pass transistor, and adjusts the resistance of the variable resistor according to the voltages at the second terminal of the pass transistor, the voltage at the second terminal of the sense transistor, and the sense current flowing through the sense transistor. | 02-16-2012 |
Yu-Sheng Lin, Zhubei City TW
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20120123872 | COOPERATIVE PERSONALIZED PROMOTION METHOD ACCORDING TO CONSUMER-STORE INTERACTIVE TRANSACTION HISTORY AND SYSTEM USING THE SAME - A system performs cooperative personalized promotion based on consumer-store interactive transaction history at multiple stores of different categories. The system includes a cooperative personal promotion platform. The cooperative personal promotion platform is provided for multiple stores of different categories to register a number of promotion information and to display at least one preferential-combination-information constituted by the promotion information. The promotion platform includes a data exchange interface, a remote-end server and a consumer record unit. The data exchange interface is used for reading a consumer's basic information into the platform, and connecting to the remote-end server via a network. The remote-end server is used for checking the consumer's basic information and recording consumer's latest interactive transaction in the consumer record unit for updating a consumer-store interactive transaction history. The cooperative personal promotion platform matches at least one preferential combination information for the consumer's choice according to the consumer-store interactive transaction history. | 05-17-2012 |
Yu-Yen Lin, Zhubei City TW
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20140038421 | Deposition Chamber and Injector - A system and method are disclosed for processing semiconductors. An embodiment comprises a reaction chamber for processing wafers and having walls tapering at an angle that is greater than 0 degrees and less than about 35 degrees from a first end optionally having a diameter of 341 to 380 millimeters to a second end optionally having a diameter of 300 to 340 millimeters at a second end, with gas flow from the first end to the second end, and having at least one deposition injector near the first end of the reaction chamber and having a plurality of injector openings that disperse injection material across a cross section of the reaction chamber for forming a deposition layer. | 02-06-2014 |