Huang, Hsinchu
An-Bin Huang, Hsinchu TW
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20080317401 | Optic fiber bragg grating sensor - The optic fiber Bragg grating (FBG) sensor comprises of an elastic circular diaphragm and one or two FBG attached to the bottom surface of the elastic circular diaphragm. Two ends of the FBG are connected to an optic fiber for signal transmission. The FBG sensor readouts are independent of temperature fluctuation. The FBG sensor mechanism according to the present invention may be applied for various purposes such as a gauge pressure transducer, differential pressure transducer, load cell and displacement transducer with distributive capabilities. | 12-25-2008 |
20090297089 | Fiber grating sensor - A fiber grating sensor including an elastic circular plate and one or two FBG'ss attached to the bottom surface of the elastic circular plate. Two ends of the FBG are connected to an optic fiber for signal transmission. The fiber grating sensor readouts are independent of temperature variation. The fiber grating sensor mechanism according to the present invention may be applied in a variety of sensors such as gauge pressure transducer, differential pressure transducer, load cell and displacement transducer with a distributive design, and for various purposes. | 12-03-2009 |
An-Jye Huang, Hsinchu TW
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20100332995 | ADAPTIVE INFOTAINMENT DEVICE - The present invention provides an adaptive infotainment device, comprising a display unit, a processing module, and a network module. The processing module is coupled to the display unit to decrypt and process the multi-media content. The network module is coupled to the processing module to receive the multi-media content and selecting paths and accessing nodes. The network module collects the usage log to be processed by the processing module to generate an accumulated user profile to be fused with user default information in a user default unit coupled to the processing module to generate at least one threshold value so that the display unit is capable of displaying the processed multi-media content according to the threshold value. Hence, the user's network behavior can be learned by combining the pre-determined preferences and the past usage preferences so as to generate the most favorable displaying means to enhance the convenience for browsing information. | 12-30-2010 |
Bao-Hung Huang, Hsinchu TW
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20090123592 | Process for preparing vegetable casing and transferring apparatus used therein - The present invention discloses an extrusion process for preparing vegetable casing including preparing a continuous tubular extrudate by extrusion, and transferring the continuous tubular extrudate. The transferring includes repeatedly passing a plurality of separate horizontal posts below the continuous tubular extrudate, hanging the continuous tubular extrudate on the posts so that the continuous tubular extrudate is conveyed by the posts a distance, while a closed space is formed inside the tubular extrudate and between every two adjacent horizontal posts. | 05-14-2009 |
Bo-Cheng Huang, Hsinchu TW
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20080252854 | ILLUMINATION SYSTEM - An illumination system includes a light source module, a chromaticity-adjusting light source and a light-combining element. The light source module provides a first color light beam, a second color light beam and a third color light beam. The chromaticity-adjusting light source provides a chromaticity-adjusting light beam. The light-combining element is disposed on the transmission paths of the chromaticity-adjusting light beam and the color light beams provided by the light source module to combine the color light beams with the chromaticity-adjusting light beam into an illumination beam. | 10-16-2008 |
20100128227 | ILLUMINATION SYSTEM AND PROJECTION APPARATUS - An illumination system including a first light emitting chip, a chip package, a first dichroic film, and a second dichroic film is provided. The first light emitting chip emits a first light beam. The chip package includes a second light emitting chip and a third light emitting chip. The second light emitting chip emits a second light beam. The third light emitting chip emits a third light beam. The colors of the first, second, and third light beams are different from each other. The first dichroic film is disposed in the transmission paths of the first and second light beams. The second dichroic film is disposed in the transmission paths of the first, second, and third light beams. The first and second dichroic films are not parallel to and do not intersect each other. Besides, a projection apparatus employing the illumination system and another projection apparatus are provided. | 05-27-2010 |
20100290012 | PROJECTION MODULE AND ELECTRONIC DEVICE - A projection module adapted to be disposed in an electronic device is provided. The electronic device includes a main body and the projection module disposed in the main body. The projection module includes a chassis, a light source, a light valve, a first lens group, and a second lens group. The light source and the light valve are disposed on the chassis. The first lens group is fixed on the chassis. The second lens group is slidably assembled on the chassis and is disposed between the light valve and the first lens group. The light source is capable of providing a light beam, and the light beam is capable of emitting through the light valve, the second lens group, and the first lens group in sequence. | 11-18-2010 |
Chao-Shun Huang, Hsinchu TW
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20100314991 | LIGHT-EMITTING DEVICE HAVING A PATTERNED SUBSTRATE AND THE METHOD THEREOF - This disclosure provides a light-emitting device including a patterned substrate and the manufacturing method thereof. The patterned substrate has a plurality of depressions and/or extrusions for scattering light emitted from a light-emitting layer. Each of the plurality of depressions and/or extrusions comprises a top portion, a bottom portion, and a sidewall portion enclosing the top portion and the bottom portion, and at least part of the sidewall portion comprises a curve. In a preferred embodiment, the light-emitting device further comprises a rough surface formed on at least one of the top portion, the bottom portion, and the sidewall portion. | 12-16-2010 |
20130009188 | LIGHT-EMITTING DEVICE HAVING A PATTERNED SUBSTRATE AND THE METHOD THEREOF - This disclosure provides a light-emitting device including a patterned substrate and the manufacturing method thereof. The patterned substrate has a plurality of depressions and/or extrusions for scattering light emitted from a light-emitting layer. Each of the plurality of depressions and/or extrusions comprises a top portion, a bottom portion, and a sidewall portion enclosing the top portion and the bottom portion, and at least part of the sidewall portion comprises a curve. Ina preferred embodiment, the light-emitting device further comprises a rough surface formed on at least one of the top portion, the bottom portion, and the sidewall portion. | 01-10-2013 |
Chao Yu Huang, Hsinchu TW
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20110050355 | EMI SUPPRESSOR HAVING BANDPASS FILTERING FUNCTION - An electromagnetic interference (EMI) suppressor having a bandpass filtering function is provided. The EMI suppressor is disposed on a substrate, and includes a signal line, a ground line, an open-circuit line, a first line group, and a second line group. The signal line has an input terminal and an output terminal for feeding in and feeding out electromagnetic wave signals respectively. One terminal of the ground line is connected to the signal line and the other terminal is a ground terminal. One terminal of the open-circuit line is connected to the signal line and the other terminal is an open-circuit terminal. The first line group is formed by a first open-circuit line and a second open-circuit line, and is connected to the signal line. The second line group is formed by a third open-circuit line and a fourth open-circuit line, and is connected to the signal line. | 03-03-2011 |
Charles Huang, Hsinchu TW
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20080219148 | SYSTEM AND METHOD FOR TRANSMITTING DATAIN A MULTIPLE-BRANCH TRANSMITTER-DIVERSITY ORTHOGONAL FREQUENCY-DIVISION MULTIPLEXING (OFDM) SYSTEM - A system and method for transmitting data in multiple-branch transmitter-diversity OFDM systems is presented. In one embodiment, an approach is taken where an inverse Fourier transform (IFT) is performed on data prior to encoding the data for transmission in the multiple-branch transmitter-diversity system. In another embodiment an IFT is performed on data prior to encoding the data using a space-time block code (STBC) algorithm. | 09-11-2008 |
Chih Chuan Huang, Hsinchu TW
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20090303646 | CONTROLLING APPRATUS AND CONTROLLING METHOD FOR SIGNAL OUTPUTING CIRCUIT AND VIDEO SYSTEM - The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state. | 12-10-2009 |
Chih Tsun Huang, Hsinchu TW
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20080209293 | PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICES - A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing. | 08-28-2008 |
Chiu-Tsung Huang, Hsinchu TW
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20090161406 | NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME - A non-volatile memory including a diode and a memory cell is described. The diode includes a doped region, a metal silicide layer, and a patterned doped semiconductor layer. The doped region of a first conductive type is formed in a substrate. The metal silicide layer is formed on the substrate. The patterned doped semiconductor layer of a second conductive type is formed on the metal silicide layer. The memory cell is formed on the substrate and coupled with the diode. | 06-25-2009 |
Chris Ing-Yi Huang, Hsinchu TW
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20090112266 | SPINAL DYNAMIC STABILIZATION DEVICE - A spinal dynamic stabilization device for maintaining an anatomical height between two adjacent vertebras is provided. Each vertebra includes a spinous process and two symmetric pedicles. The spinal dynamic stabilization device includes a supporting member, at least one anchoring member, and at least one connecting member. The supporting member is disposed between the spinous processes. The anchoring member is fixed in one of the vertebra via one of the pedicles. The connecting member connects the supporting member to the anchoring member, fixing a relative position between the supporting member and the anchoring member, further fixing a relative position between the vertebras. | 04-30-2009 |
Chun-Kan Huang, Hsinchu TW
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20100306563 | COMPUTER SYSTEM FOR SAVING POWER CONSUMPTION OF A STAND-BY/POWER-OFF STATE AND METHOD THEREOF - A computer system consists of a plurality of electronic elements and a switch control circuit. The switch control circuit controls the computer system to enter a stand-by/power off state from a normal state when the computer system receives a stand-by/power off command under the normal state, and stops outputting a stand-by power having at least one stand-by voltage level to at least one part of electronic elements among the plurality of electronic elements. At this time, the computer system has entered a simulated mechanical off state from the stand-by/power off state. A number of electronic elements supplied by the stand-by power when the computer system lies under the simulated mechanical off state is smaller than a number of electronic elements supplied by the stand-by power when the computer system lies under the stand-by/power off state. | 12-02-2010 |
Hong-En Huang, Hsinchu TW
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20090089496 | Dual-interface data storage apparatus - The present invention discloses a dual interface data storage apparatus, including: a memory module, a first interface and a second interface connected with the memory module, a housing, and a movable carriage for carrying the memory module, the first interface, and the second interface. The housing accommodates the memory module, the first interface and the second interface, and has a first opening at one end and a second opening at the other end for either allowing the first interface or the second interface to pass through the first opening or the second opening. | 04-02-2009 |
Hong Ji Huang, Hsinchu TW
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20100277418 | Patterned resistive touch panel - A touch panel having a first panel and a second panel, wherein the first panel has a voltage providing area connected to a power source and the second panel has a patterned resistive element facing the voltage providing area so that when a touch event on the touch panel occurs, the first panel is caused to make contact with and provide a voltage to the second panel at one or more contact points on the resistive element. By measuring the voltage on one or both ends of the resistive element, it is possible to determine the two-dimensional coordinates of each contact point. The touch panel can have one or more resistive elements located at different touch areas for sensing one or more touch points in a touch event. | 11-04-2010 |
20120299875 | Patterned Resistive Touch Panel - A touch panel having a first panel and a second panel, wherein the first panel has a voltage providing area connected to a power source and the second panel has a patterned resistive element facing the voltage providing area so that when a touch event on the touch panel occurs, the first panel is caused to make contact with and provide a voltage to the second panel at one or more contact points on the resistive element. By measuring the voltage on one or both ends of the resistive element, it is possible to determine the two-dimensional coordinates of each contact point. The touch panel can have one or more resistive elements located at different touch areas for sensing one or more touch points in a touch event. | 11-29-2012 |
Hon-Lin Huang, Hsinchu TW
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20080303154 | Through-silicon via interconnection formed with a cap layer - An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask. | 12-11-2008 |
Hsiang-Jung Huang, Hsinchu TW
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20090131670 | BIS-TRIPHENYLSILYL COMPOUNDS AND THEIR APPLICATION ON ORGANIC ELECTRONIC DEVICE - The present invention discloses a bis-triphenylsilyl compound and its applications as a host material, electron transport material, or hole transport material in an organic electronic device. The general structure of the bis-triphenylsilyl compound is as follows: | 05-21-2009 |
Hsiang Lin Huang, Hsinchu TW
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20090167274 | PWM CONTROLLER AND THE CHIP THEREOF - A PWM controller applied to a switching voltage regulator comprises a disabling circuit, a power-sensing circuit, an over-current protection circuit and a PWM logic circuit. The disabling circuit is connected to an external frequency compensation circuit for detecting a voltage used to stop the operation of the PWM controller. The power-sensing circuit is configured to stop the operation of the PWM controller if the input voltage of the high side switch is lower than a threshold. The over-current protection circuit is configured to monitor current flowing through the output circuit, and the over-current protection circuit generates an over-current protection signal when the current exceeds a threshold. The PWM logic circuit is connected to the outputs of the disabling circuit, power-sensing circuit and over-current protection circuit. | 07-02-2009 |
20090189585 | PULSE WIDTH MODULATION CONTROLLER AND THE CONTROLLING METHOD THEREOF - A PWM controller for controlling a switching voltage regulator comprises a first comparator, a second comparator and a third comparator. The first comparator is configured to detect voltages of a first node and a second node so as to determine whether to stop the PWM controller. The PWM controller is stopped if a first potential is lower than a threshold, and the first potential derives from the voltage of the first node by a level shift of a first voltage difference. The second comparator is configured to detect the voltage of the first node and then to compare the voltage with a power reference voltage so as to determine whether the PWM controller receives necessary power. The third comparator is configured to compare the voltage of the second node with an enable reference voltage so as to determine whether to disable the PWN controller. | 07-30-2009 |
20090189661 | PULSE WIDTH MODULATION CONTROLLER AND THE CONTROLLING METHOD THEREOF - A pulse width modulation controller comprises a disabling unit, a level sensor and an over current protector. These three devices are all coupled to a multi-function node for accomplishing a disable function, input level sensing, and over-current protection, respectively. | 07-30-2009 |
Hsiang-Ming Huang, Hsinchu TW
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20100007001 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other. | 01-14-2010 |
20110291268 | Semiconductor wafer structure and multi-chip stack structure - A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps. | 12-01-2011 |
20130069228 | FLIP-CHIP PACKAGE STRUCTURE AND FORMING METHOD THEREOF - A flip-chip package structure comprising a substrate, a chip, a bump structure and a solder resist is provided. The substrate has a circuit layer disposed on the surface thereof. The chip comprises a central region and two edge regions disposed on the two sides of the central region. The bump structure is disposed on the central region of the chip and faces the substrate. The solder resist is disposed on the substrate to partially cover the circuit layer. The chip is electrically connected to the substrate by the bump structure, and the solder resist is adapted to come into contact with the two edge regions of the chip to support the chip with the bump structure when the chip is disposed on the substrate. | 03-21-2013 |
20130119530 | THERMALLY ENHANCED PACKAGING STRUCTURE - A thermally enhanced packaging structure includes a chip carrier; a high power chip disposed on the chip carrier; a molding compound covering the high power chip; a heat dissipating layer disposed on the molding compound, wherein the heat dissipating layer comprises a plurality of carbon nanocapsules (CNCs); and a non-fin type heat dissipating device, disposed either on the heat dissipating layer or between the molding compound and the heat dissipating layer. The molding compound can also comprise a plurality of CNCs. | 05-16-2013 |
Hsien-Sheng Huang, Hsinchu TW
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20090021284 | Low voltage differential signal receiver - The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer. | 01-22-2009 |
Hsing-Chien Huang, Hsinchu TW
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20090019409 | Method for Reducing Timing Libraries for Intra-Die Model in Statistical Static Timing Analysis - A method for performing statistical static timing analysis on an integrated circuit (IC) is disclosed, which comprises identifying a plurality of turned-on devices in the IC during a predetermined operation of the IC, choosing only the libraries of the plurality of turned-on devices, and calculating a time delay of the IC using only the chosen libraries, wherein the number of libraries used for the time delay calculation is reduced. | 01-15-2009 |
Hsin Jen Huang, Hsinchu TW
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20090249140 | METHOD FOR MANAGING DEFECT BLOCKS IN NON-VOLATILE MEMORY - A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only. | 10-01-2009 |
20090254729 | METHOD OF WEAR LEVELING FOR A NON-VOLATILE MEMORY - According to the method of wear leveling for a non-volatile memory of the present invention, the non-volatile memory is divided into a plurality of windows, and a mapping table is built in which the logical block addresses having frequently accessed data are allocated equally to the plurality of windows. The logical block addresses may store a File Allocation Table (FAT) or a directory table; therefore the windows they locate will be written or erased more frequently. In an embodiment, the logical block addresses having frequently accessed data are allocated on a one-to-one basis to the plurality of windows. For example, the plurality of windows may comprise Windows | 10-08-2009 |
Hsiu-Wu Huang, Hsinchu TW
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20080213588 | Synthesis of composite nanofibers for applications in lithium batteries - A uniform composite nanofiber includes a tubular first nanofiber, and a second nanofiber formed inside or outside the first nanofiber. The first nanofiber is first formed within a plurality of nano-scale pores of a template placed on a current collector, and then the second nanofiber is formed on inner or outer surface of the first nanofiber, and the template is removed afterwards for obtaining the composite nanofiber. | 09-04-2008 |
Hsuan-Kuan Huang, Hsinchu TW
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20100235451 | INSTANT MESSAGING INTERACTION SYSTEM AND METHOD THEREOF - An instant messaging interaction system and method work by: analyzing communicative information sent by a remote user to create emotional messages and analyzing information about the remote user's identity; storage in a storage module behavior weight value preset and corresponding to the information about the remote user's identity; determining, by a learning module, interactive responses according to the emotional messages and the behavior weight values; outputting, by an output module, the interactive responses; detecting if receiving a feedback signal from an local user; if the feedback signal is not received, the learning module stores the behavior weight value in the storage module; if the feedback signal is received, the feedback module generates a modification value corresponding to different levels of the feedback signal; generating, by the learning module and according to a detection result, modification values for modifying the behavior weight values. As a result, the messaging interaction system is capable of presenting rated interactive responses in a personalized, artificial intelligence-based manner that meets the local user's expectation. | 09-16-2010 |
Hsueh-I Huang, Hsinchu TW
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20080315308 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE AND METHOD OF FABRICATING THE SAME - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 12-25-2008 |
20110204441 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 08-25-2011 |
Huai-Yi Huang, Hsinchu TW
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20090067064 | FIXED-FOCUS LENS - A fixed-focus lens including a first lens group and a second lens group is provided. The first lens group has a negative refractive power, and consists essentially of a first lens, a second lens, a third lens, and a fourth lens arranged in sequence from an object side to an image side. Refractive powers of the first, second, third, and fourth lenses are negative, negative, positive, and negative respectively. The second lens group is disposed between the first lens group and the image side, and has a positive refractive power. The second lens group includes a fifth lens and a sixth lens arranged in sequence from the object side to the image side. Refractive powers of the fifth lens and the sixth lens are both positive. | 03-12-2009 |
Jen-Hsien Huang, Hsinchu TW
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20090027919 | BACKLIGHT MODULE - A backlight module including a back plate, a reflection sheet, a light guiding plate, a reflector, and a first light source and a second light source is provided. The reflection sheet is disposed on the back plate, and one end of the reflection sheet is bent to form a lamp reflector. The light guiding plate is disposed on the reflection sheet, and has a first side and a corresponding second side. A first containing space is formed between the first side of the light guiding plate and the lamp reflector. The reflector is disposed at the second side of the light guide plate, and a second containing space is formed between the second side of the light guiding plate and the reflector. The first light source and the second light source are disposed within the first and the second containing space, respectively. | 01-29-2009 |
Jen-Sheng Huang, Hsinchu TW
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20100214961 | FAST AND AUTOMATIC SELF-FORMING MESHING TOPOLOGY TO INTEGRATE WITH WIRED NETWORKS - The present invention applies management frame defined in IEEE 802.11 standard to a wireless distribution system (WDS) mode by adding an information element (IE) into the management frame, which enables any access point (AP) in WDS to maintain IE based on its own setting and state, then send IE via the management frame for providing state of the AP under WDS mode, determine whether a physical link (i.e., a wireless link between APs) should be established therewith based on received IE, and maintain the established physical link through the wireless management frame in a real time manner. Thus, the existence and necessity of the physical link between different APs in WDS can be determined correctly. | 08-26-2010 |
Jen-Shiun Huang, Hsinchu TW
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20100261012 | Flexible Display Panel and Method of Manufacturing the same - A flexible display panel includes a flexible display module and a cured protection layer. The flexible display module includes a flexible substrate, a first circuit layer, a display layer and a second circuit layer. The flexible substrate has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface and has a view area. The display layer is disposed on the first circuit layer and corresponding to the view area. The second circuit layer is disposed on the display layer. The cured protection layer is disposed on the second surface. The inner circuit of the flexible display panel is protected by the cured protection layer. In addition, a method of manufacturing the flexible display panel is also provided. | 10-14-2010 |
20110128608 | ELECTRO-PHORETIC DISPLAY DEVICE AND FABRICATING METHOD THEREOF - An electro-phoretic display device includes a first substrate, an active elements array, a driving circuit, a conductive flexible board, an electro-phoretic layer, a second substrate and a sealant layer. The first substrate has a first surface defining a display area and a circuit area, and a second surface. The active elements array is disposed within the display area and the driving circuit is disposed within the circuit area and electrically connected to the active elements array. The conductive flexible board is partially disposed at the first substrate and electrically connected to the driving circuit. The electro-phoretic layer and the second substrate are sequentially disposed on the active elements array and the driving circuit. The sealant layer is interposed between the second substrate and the conductive flexible board to seal the electro-phoretic layer between the first substrate and the second substrate. A fabricating method of electro-phoretic display device is also disclosed. | 06-02-2011 |
20120026577 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes an active element array substrate, a display layer and a transparent shock absorption layer. The display layer is disposed on the active element array substrate. The transparent shock absorption layer is disposed on the display layer. The transparent shock absorption layer is formed by curing liquid adhesive material. A manufacturing method of display device is also provided. | 02-02-2012 |
20120212888 | DISPLAY APPARATUS - A display apparatus includes a display panel, at least one anisotropic conductive adhesive and at least one chip. The display panel has a peripheral circuit region, and the anisotropic conductive adhesive is adhered in the peripheral circuit region. The chip is disposed on the anisotropic conductive adhesive, and the chip has an electric coupling region on a surface facing the anisotropic conductive adhesive. The electric coupling region is equipped with a plurality of electric coupling parts, and the electric coupling parts are electrically coupled to the peripheral circuit region by the anisotropic conductive adhesive. An interval is existed between a boundary of the electric coupling region and a boundary of the chip, and the electric coupling region is located in a bonding region of the anisotropic conductive adhesive. The bonding region of the anisotropic conductive adhesive is located in the boundary of the chip. The display apparatus has better reliability. | 08-23-2012 |
20120229390 | MOBILE DEVICE - A mobile device is disclosed. The mobile device includes a display, a touch panel, and a buffer structure. The touch panel is disposed on one side of the display. The buffer structure has a gas fluid layer and is disposed between the display and the touch panel. | 09-13-2012 |
20120236522 | Method for forming an EMI shielding layer on an Electronic System - The present invention provides a method for forming a shielding layer on a sensor board. The sensor board includes an antenna array element. The sensor board is integrated into an electronic system. The method includes using a physical vapor deposition process to form the shielding layer on the sensor board to shield the sensor board from an electromagnetic signal generated by the electronic system, wherein the shielding layer and the antenna array element are respectively formed on two opposite surfaces of the sensor board. | 09-20-2012 |
20130057464 | ELECTRO-PHORETIC DISPLAY DEVICE AND FABRICATING METHOD THEREOF - An electro-phoretic display device includes a first substrate, an active elements array, a driving circuit, a conductive flexible board, an electro-phoretic layer and a second substrate. The first substrate has a first surface defining a display area and a circuit area, and a second surface. The active elements array is disposed within the display area and the driving circuit is disposed within the circuit area and electrically connected to the active elements array. The conductive flexible board is partially disposed at the first substrate and electrically connected to the driving circuit. The electro-phoretic layer and the second substrate are sequentially disposed on the active elements array and the driving circuit. A fabricating method of electro-phoretic display device is also disclosed. | 03-07-2013 |
20140320137 | INSPECTION METHOD AND INSPECTION APPARATUS - An inspection method including following steps is provided. A pixel array substrate including a plurality of pixel units is in contact with a photoelectric inspection device. A plurality of electrical signals is inputted to the pixel units of the pixel array substrate and the photoelectric inspection device. Based on an optical property of the photoelectric inspection device, the pixel units of the pixel array substrate are being examined on whether they are normal or not. Moreover, an inspection apparatus realizing the inspection method is also provided. | 10-30-2014 |
Jia-Hung Huang, Hsinchu TW
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20110134377 | LIQUID CRYSTAL DISPLAY PANEL AND ACTIVE DEVICE ARRAY SUBSTRATE THEREOF - An active device array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units, each of the pixel units formed between every neighboring two of the scan lines and data lines is provided. Each of the pixel units includes a first active device, a first pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device, a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device and a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the second active device. The first pixel electrode has a surface area different from that of the second pixel electrode. | 06-09-2011 |
20120038865 | LIQUID CRYSTAL DISPLAY PANEL AND ACTIVE DEVICE ARRAY SUBSTRATE THEREOF - An active device array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units, each of the pixel units formed between every neighboring two of the scan lines and data lines is provided. Each of the pixel units includes a first active device, a first pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device, a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device and a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the second active device. The first pixel electrode has a surface area different from that of the second pixel electrode. | 02-16-2012 |
Jiann-Tseng Huang, Hsinchu TW
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20090243705 | High Voltage Tolerative Driver Circuit - A high voltage tolerative inverter circuit is disclosed, which comprises a PMOS transistor with a source and drain being connected to a first high voltage power supply (VDDQ) and an output terminal, respectively, a gate of the PMOS transistor being controlled by a first signal having a voltage swing between the VDDQ and a low voltage power supply (VSS), and a NMOS transistor with a source and drain being connected to the VSS and the output terminal, a gate of the NMOS transistor being controlled by a second signal having a voltage swing between a second high voltage power supply (VDD) and the VSS, wherein the VDD is lower than the VDDQ, and the voltage swings between the VDDQ and the VSS by the first signal and between the VDD and the VSS by the second signal are always in the same direction. | 10-01-2009 |
20100329055 | MEASURING ELECTRICAL RESISTANCE - A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device. | 12-30-2010 |
20110026354 | CURRENT LEAKAGE REDUCTION - An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks. | 02-03-2011 |
20120020177 | ELECTRICAL FUSE MEMORY - Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row. | 01-26-2012 |
20120081165 | HIGH VOLTAGE TOLERATIVE DRIVER - A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS. | 04-05-2012 |
20120320700 | CURRENT LEAKAGE REDUCTION - This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell. | 12-20-2012 |
20130107603 | CIRCUIT AND METHOD FOR GENERATING A READ SIGNAL | 05-02-2013 |
20130155799 | ELECTRICAL FUSE MEMORY - A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on. | 06-20-2013 |
20130223129 | MEASURING ELECTRICAL RESISTANCE - In at least one embodiment, a method includes applying an input voltage external to a semiconductor chip to a first circuit of the semiconductor chip to generate an output voltage external to the semiconductor chip. The first circuit is electrically coupled to a resistive device. A logic state of the resistive device is determined based on a logic state of the external output voltage | 08-29-2013 |
Jian-Rong Huang, Hsinchu TW
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20090200998 | Buck switching regulator with improved mode transition and control method thereof - The present invention discloses a buck switching regulator with improved mode transition, and a method for controlling a buck switching regulator. The method comprises: providing a switching regulator including: an output power stage for converting an input voltage to an output voltage, the output power stage being controlled by a first PWM signal during a fixed-frequency PWM mode (FPWM mode), and being controlled by a first voltage signal during a pulse skipping mode (PSK mode), wherein the first PWM signal is generated according to the first voltage signal; and in a transition from the PSK mode to the FPWM mode, proving a second voltage signal as a starting point of the first voltage signal, the second voltage signal being substantially close to a target of the first voltage signal in the FPWM mode. | 08-13-2009 |
20140021929 | MULTI-PHASE SWITCHING REGULATOR AND DROOP CIRCUIT THEREFOR - The present invention provides a multi-phase switching regulator and a droop circuit for use in the multi-phase switching regulator. The multi-phase switching regulator generates pulse width modulation (PWM) signals according to an output voltage and a droop signal, to drive a plurality of switching sets to convert an input voltage to the output voltage. The droop circuit detects the sum of the currents generated by the plurality of switching sets and provides the droop signal which is related to the sum of the currents to the multi-phase switching regulator. The droop signal can be used for over current protection (OCP) or for the droop control. | 01-23-2014 |
Jih-Jenn Huang, Hsinchu TW
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20080259106 | METHOD FOR MANUFACTURING PATTERNED LAYER ON SUBSTRATE - A method for manufacturing a patterned layer ( | 10-23-2008 |
Jung-Y. Huang, Hsinchu TW
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20100213440 | Silicon-Quantum-Dot Semiconductor Near-Infrared Photodetector - A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response. | 08-26-2010 |
20100215065 | Coherent multiple-stage optical rectification terahertz wave generator - The present invention coherent multiple-stage optical rectification terahertz wave generator discloses the generation of single-cycle terahertz radiation with two-stage optical rectification in GaSe crystals. By adjusting the time delay between the pump pulses employed to excite the two stages, the terahertz radiation from the second GaSe crystal can constructively superpose with the seeding terahertz field from the first stage. The high mutual coherence between the two terahertz radiation fields is ensured with the coherent optical rectification process and can be further used to synthesize a desired spectral profile of output coherent THz radiation. The technique is also useful for generating high amplitude single-cycle terahertz pulses, not limited by the pulse walk-off effect from group velocity mismatch in the nonlinear optical crystal used. | 08-26-2010 |
20120256181 | POWER-GENERATING MODULE WITH SOLAR CELL AND METHOD FOR FABRICATING THE SAME - The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation. | 10-11-2012 |
20140065754 | METHOD FOR FABRICATING POWER-GENERATING MODULE WITH SOLAR CELL - The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit. | 03-06-2014 |
Jyh-Haur Huang, Hsinchu TW
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20090116232 | COLOR CONTROL OF MULTI-ZONE LED BACKLIGHT - The present invention relates to a light emitting diode (LED) backlight having a plurality of LED strips, in which driving current supplied to each of the plurality of LED strips is adjusted according to measured differences in chromaticity coordinates between the actual light chromaticity and brightness output by each LED strip and a desired light chromaticity and brightness of each LED so that the LED backlight generates light of a desired color with a uniform brightness, and methods of operating the same. | 05-07-2009 |
Jyun-Siang Huang, Hsinchu TW
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20090116284 | MEMORY APPARATUS AND METHOD THEREOF FOR OPERATING MEMORY - A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced. | 05-07-2009 |
20100176437 | MEMORY ARRAY AND METHOD FOR MANUFACTURING AND OPERATING THE SAME - The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines. | 07-15-2010 |
20110079840 | MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE - A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region. | 04-07-2011 |
20120018790 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions. | 01-26-2012 |
20120287724 | METHOD OF PROGRAMMING MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD - A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection. | 11-15-2012 |
20120326222 | MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer. | 12-27-2012 |
20120327721 | METHOD FOR ERASING MEMORY ARRAY - A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines. The method for erasing the memory array includes the following steps. A first voltage is applied to a substrate of the memory array. A second voltage is applied to a word line of a selected memory cell, and a plurality of passing voltages are applied to other word lines. And, a third voltage and a fourth voltage are respectively applied to a first source/drain region and a second source/drain region of the selected memory cell, so that a band to band (BTB) hot hole injecting method is induced to erase the specific memory cell, wherein the third voltage is not equal to the fourth voltage. | 12-27-2012 |
20130099303 | MEMORY AND MANUFACTURING METHOD THEREOF - A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures. | 04-25-2013 |
20130105882 | MEMORY STRUCTURE AND FABRICATING METHOD THEREOF | 05-02-2013 |
20130176789 | MEMORY ARRAY AND METHOD FOR PROGRAMMING MEMORY ARRAY - A method for programming a memory array is provided. The memory array includes a memory cell string composed of a first transistor, a plurality of memory cells and a second transistor connected in series, and the method for programming the memory array includes following steps. In a setup phase, a switching memory cell in the memory cells is turned off, and a first voltage and a second voltage are applied to a first source/drain and a second source/drain of the switching memory cell. In a programming phase, a bit line connected to the memory cell string is floating, and a ramp signal is provided to a word line electrically connected to the switching memory cell. | 07-11-2013 |
20140306282 | MULTI LEVEL PROGRAMMABLE MEMORY STRUCTURE - A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer. | 10-16-2014 |
Kung Chieh Huang, Hsinchu TW
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20100277418 | Patterned resistive touch panel - A touch panel having a first panel and a second panel, wherein the first panel has a voltage providing area connected to a power source and the second panel has a patterned resistive element facing the voltage providing area so that when a touch event on the touch panel occurs, the first panel is caused to make contact with and provide a voltage to the second panel at one or more contact points on the resistive element. By measuring the voltage on one or both ends of the resistive element, it is possible to determine the two-dimensional coordinates of each contact point. The touch panel can have one or more resistive elements located at different touch areas for sensing one or more touch points in a touch event. | 11-04-2010 |
20120019450 | TOUCH SENSING DEVICE - The present invention relates to a touch sensing device. In one embodiment, the touch sensing device includes a plurality of first touch electrodes and a plurality of second touch electrodes, alternately arranged along a first direction and a second direction substantially perpendicular to the first direction to form a sensing matrix, such that each first touch electrode and a corresponding second touch electrode are entangled each other along with at least one of the first and second directions. | 01-26-2012 |
20120299875 | Patterned Resistive Touch Panel - A touch panel having a first panel and a second panel, wherein the first panel has a voltage providing area connected to a power source and the second panel has a patterned resistive element facing the voltage providing area so that when a touch event on the touch panel occurs, the first panel is caused to make contact with and provide a voltage to the second panel at one or more contact points on the resistive element. By measuring the voltage on one or both ends of the resistive element, it is possible to determine the two-dimensional coordinates of each contact point. The touch panel can have one or more resistive elements located at different touch areas for sensing one or more touch points in a touch event. | 11-29-2012 |
Kuo-Fang Huang, Hsinchu TW
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20090235894 | Lubrication apparatus for engines - A lubrication apparatus for an engine includes a crankshaft chamber, a camshaft chamber, and an oil reservoir chamber, wherein an oil-suction piping path is provided in the oil reservoir chamber, and is communicated between the crankshaft chamber and the oil reservoir chamber. The oil-suction piping path includes, among others, a rotatable pipe including a plurality of oil-suction orifices located at wall of the rotatable pipe. No matter the engine is situated at any state of declination, at least one of the oil-suction orifices and an air-suction vent is kept under the surface of the lubricant, so that the engine can be appropriately lubricated. Further, a one-way valve is arranged between the crankshaft chamber and the oil reservoir chamber, where most of the lubricant can flow back to the oil reservoir chamber during the descending stroke of a piston, so that a lubricant supply can be reduced. | 09-24-2009 |
Kuo-Hsiu Huang, Hsinchu TW
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20080256176 | Internet radio system and the broadcasting method thereof - An Internet radio system includes: several network radio receivers connecting to the Internet, and they transmitting service requests and user's information, then receiving audio data corresponding the service requests, wherein each network radio receivers has its own identification; and a server connecting to the Internet to identify the identification of network radio receiver. The server may store some advertisement information for users to select and display them on the radio receivers. | 10-16-2008 |
Liang-Yin Huang, Hsinchu TW
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20090075437 | THIN FILM TRANSISTOR MANUFACTURING METHOD AND SUBSTRATE STRUCTURE - A method of TFT (Thin Film Transistor) manufacturing and a substrate structure are provided. The structure includes a substrate and a self-alignment mask. A self-alignment mask on a substrate is first manufactured and then the self-alignment mask may synchronously extend with the substrate during the thermal process. When an exposure light source is provided on the side without a TFT formed, the self-alignment mask can overcome the problem that when a plastic substrate extends, the positions of the source and drain to be formed on the plastic substrate are incorrect, which has a great effect on the accuracy of alignment. As the result, the positions of the source and drain can be defined accurately. | 03-19-2009 |
Min-Jie Huang, Hsinchu TW
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20080217606 | Organic light emitting diode containing a Ir complex having a novel ligand as a phosphorescent emitter - An organic light emitting diode with Ir complex is disclosed in this specification, wherein the Ir complex is used as the phosphorous emitter. The chemical containing pyridyl triazole or pyridyl imidazole functional group is used as the auxiliary monoanionic bidentate ligand in the mentioned Ir complex, so that the CIE coordinate of the mentioned Ir complex is adjustable and the light emitting performance of the Ir complex is improved. | 09-11-2008 |
Min-San Huang, Hsinchu TW
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20100003796 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACT - A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings. | 01-07-2010 |
Pin-Chun Huang, Hsinchu TW
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20080297053 | METHOD FOR CONTROLLING DUAL LAMP MODULE - A method for controlling a dual lamp module applied to a projection apparatus is provided. The dual lamp module includes a first lamp and a second lamp. The method for controlling a dual lamp module includes providing a first operating power to the first lamp, and then determining whether the first lamp is turned on or not. If the first lamp fails to be turned on, stopping providing the first operating power to the first lamp, and providing a second operating power to the second lamp. The second operating power is greater than the first operating power. | 12-04-2008 |
20080304021 | LIGHT-SHIELDING MODULE AND PROJECTION APPARATUS USING THE SAME - A light-shielding module including a bracket, a pendulous member, a shielding member, a first magnet, a second magnet and a first coil is provided. The pendulous member has a first end and a second end opposite to each other and is pivoted on the bracket. The first end extends along a direction from a pivoting place of the pendulous member to a top of the bracket. The shielding member is connected to the first end. The first magnet is disposed at the pendulous member and located between the pivoting place and the first end. The second magnet is disposed at the pendulous member and adjacent to the second end. A mass-of-center of the second magnet is located beside a center line passing a center-of-mass of the first magnet and the pivoting center. The first coil is disposed on one of the first side wall and the second side wall. | 12-11-2008 |
Pin-Hsun Huang, Hsinchu TW
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20110137380 | FLEXIBLE ANTENNA MODULE FOR WIRELESS ENERGY TRANSMISSION - This invention provides a flexible antenna module for wireless energy transmission, which uses an antenna size controlling device to adjust the antenna's size to conform a living body's outer portion wearing the flexible annular antenna. An antenna energy transmission control module is provided to adjust the power for driving the flexible annular antenna according to the deformation of the flexible annular antenna. This invention can adjust both the antenna size to fit the individual and the power for driving the antenna. The individual can use the present antenna module under a comfortable, safe and reliable circumstance. | 06-09-2011 |
Po Chao Huang, Hsinchu TW
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20110176213 | Multi-Coated Hybrid Optical Film Structure - An optical film has multi-coated layers. Diffusion layers are used to scatter light. Each diffusion layer has an interface microstructure. A condensing optical layer is used to concentrating light. A design of a multi-coating technology is thus used for scattering and concentrating light. By integrating scattering and concentrating materials in a single optical film, cost is effectively reduced. By using diffusion layers having interface microstructures, interface-dominating mechanism, not only hybrid optical performance with luminance and haze is effectively enhanced; but also quality variations owing to particles added or film warp and scoring on the beneath optical film owing to particles coated are reduced. | 07-21-2011 |
Po-Chia Huang, Hsinchu TW
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20100324814 | GPS TRACKING SYSTEM - The present invention relates a GPS tracking system, comprising a tracking and positioning device, a server, a positioning display unit, and a database. Since the tracking and positioning device only sends an Internet protocol (IP) data and a verification data once when it is connected to the Internet, and sends a positioning data only when a position of the tracking and positioning device is to be shown on the positioning display unit, the bandwidth can be saved. | 12-23-2010 |
Po-Tsang Huang, Hsinchu TW
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20090161399 | Super leakage current cut-off device for ternary content addressable memory - A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells. | 06-25-2009 |
20090161400 | Leakage current cut-off device for ternary content addressable memory - A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode. | 06-25-2009 |
20100172194 | Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus - The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation. | 07-08-2010 |
Rong-Yuan Huang, Hsinchu TW
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20100291540 | CARBOHYDRATE BINDING MODULE AND USE THEREOF - The present invention relates to an antibody mimetic of carbohydrate binding module (CBM) which specifically binds to an epitope on HIV glycoprotein. The present invention also relates to a method of detecting HIV glycoprotein. | 11-18-2010 |
20100291601 | CARBOHYDRATE BINDING MODULE AND USE THEREOF - The present invention relates to an antibody mimetic of carbohydrate binding module (CBM) which specifically binds to an epitope on HIV glycoprotein. The present invention also relates to a method of detecting HIV glycoprotein. | 11-18-2010 |
Shang-I Huang, Hsinchu TW
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20100214961 | FAST AND AUTOMATIC SELF-FORMING MESHING TOPOLOGY TO INTEGRATE WITH WIRED NETWORKS - The present invention applies management frame defined in IEEE 802.11 standard to a wireless distribution system (WDS) mode by adding an information element (IE) into the management frame, which enables any access point (AP) in WDS to maintain IE based on its own setting and state, then send IE via the management frame for providing state of the AP under WDS mode, determine whether a physical link (i.e., a wireless link between APs) should be established therewith based on received IE, and maintain the established physical link through the wireless management frame in a real time manner. Thus, the existence and necessity of the physical link between different APs in WDS can be determined correctly. | 08-26-2010 |
Shaw Wen Huang, Hsinchu TW
Patent application number | Description | Published |
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20110016047 | FINANCIAL TRANSACTION SYSTEM, AUTOMATED TELLER MACHINE (ATM), AND METHOD FOR OPERATING AN ATM - A financial transaction system is provided. The financial transaction system includes a server and at least one automated teller machine (ATM). In response to a request from a user, the server issues a one-time password (OTP) to the user's mobile device. The ATM receives an OTP from the user and sends the received OTP to the server for verification, in order to perform a financial transaction operation. | 01-20-2011 |
20120292395 | INTEGRATED CIRCUIT FILM FOR SMART CARD AND MOBILE COMMUNICATION DEVICE - An integrated circuit film for a smart card, such as a Micro SIM card or a Mini UICC card, is provided. The integrated circuit film includes a flexible print circuit board (FPC) and an integrated circuit chip, and the integrated circuit chip has an ATR (Answer to Reset) signal generating device. When a terminal issues a Reset signal, this Reset signal is sent to the smart card and the ATR signal generating device, respectively via circuits of the FPC, whereby the ATR signal generating device generates ATR signal and send back to the terminal. | 11-22-2012 |
Sheng-Pan Huang, Hsinchu TW
Patent application number | Description | Published |
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20090250717 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting element having at least two electrodes disposed at the side of the light output surface thereof, and a base member having a recess and lead portions corresponding to the electrodes, the light emitting element being mounted on the base member and received in the recess, wherein the light output surface faces toward opening of the recess that becomes smaller while approaching the light output surface, and the electrodes are respectively in electrical connection with the lead portions that extend from the connection positions to outer edge of the base member for power connection, and a light reflecting portion is disposed in the recess adjacent to the light output surface such that the light emitted from the light emitting element can be reflected to walls of the recess to form a substantially collimated light beam so as to improve light efficiency. | 10-08-2009 |
20110186881 | AC_LED SYSTEM IN SINGLE CHIP WITH THREE METAL CONTACTS - A plurality of AC_LED units are coupled and disposed on a single chip to form an AC_LED system in single chip. Alternatively, an AC LED system in single chip with four metal contacts is also disclosed. | 08-04-2011 |
Sheng-Yang Huang, Hsinchu TW
Patent application number | Description | Published |
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20110163300 | ORGANIC LIGHT-EMITTING MATERIAL, ORGANIC LIGHT-EMITTING ELEMENT USING THE SAME AND METHOD OF FORMING THE SAME - The present invention provides compound of formula (I) | 07-07-2011 |
20130137206 | ORGANIC LIGHT-EMITTING MATERIAL, ORGANIC LIGHT-EMITTING ELEMENT USING THE SAME AND METHOD OF FORMING THE SAME - The present invention provides compound of formula (I) | 05-30-2013 |
Shih-Cheng Huang, Hsinchu TW
Patent application number | Description | Published |
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20110186856 | LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting element includes providing a substrate, forming a buffer layer on the substrate, forming a GaN layer on the buffer layer, forming a rough layer on the GaN layer at low temperature, and forming an epitaxial layer on the rough layer, wherein a refraction index of the epitaxial layer exceeds a refraction index of the rough layer. Thus, most light scatters at the rough layer, and then emits upwardly to a light emitting surface, enhancing light extraction efficiency thereof. An epitaxial process of the method is processed in situ in an MOCVD reactor. | 08-04-2011 |
20110210312 | III-NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device includes a substrate, a buffer layer, an n-type semiconductor layer, a conformational active layer and a p-type semiconductor layer. The n-type semiconductor layer includes a first surface and a second surface, and the first surface directly contacts the buffer layer. The second surface includes a plurality of recesses, and a conformational active layer formed on the second surface and within the plurality of recesses. Widths of upper portions of the recesses are larger than widths of lower portions of the recesses. Therefore, the stress between the n-type semiconductor layer and the conformational active layer can be released with the recesses. | 09-01-2011 |
20110256643 | METHOD FOR DETACHING LAYERS WITH LOW MAGNETIC PERMEABILITY - A method for detaching a first material layer from a second material layer includes following steps: forming a high-magnetic-permeability material layer on a first material layer comprised of low-magnetic-permeability material; removing a portion of the high-magnetic-permeability material layer to expose a portion of the first material layer; epitaxially growing a second material layer comprised of low-magnetic-permeability material on the exposed portion of the first material layer and the high-magnetic-permeability material layer; cooling the first and second material layers; heating the high-magnetic-permeability material layer, thus detaching the first material layer from the second material layer. | 10-20-2011 |
20120043523 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode comprises a substrate, a buffer layer, a semiconductor layer and a semiconductor light emitting layer. The buffer layer is disposed on the substrate. The semiconductor layer is disposed on the buffer layer. The semiconductor light emitting layer is disposed on the semiconductor layer. A plurality of voids is defined within the semiconductor layer. Each void encloses air therein. A method for manufacturing the light emitting diode is also provided. Light generated by the semiconductor light emitting layer toward the substrate is reflected by the voids to emit out of the light emitting diode. | 02-23-2012 |
20120080715 | SEMICONDUCTOR DEVICE - A structure of semiconductor device includes a first semiconductor layer; an intermediate layer on a surface of said first semiconductor layer; a second semiconductor layer on said intermediate layer, wherein said intermediate layer and said second semiconductor layer are integrated to a set of sub-structures; and a semiconductor light emitting device on said second semiconductor layer. | 04-05-2012 |
20120256162 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a substrate, an N-type semiconductor layer arranged on the substrate, an active layer, and a P-type semiconductor layer. The active layer includes a first barrier layer, a second barrier layer, and a quantum well structure layer arranged between the first and second barrier layers. The quantum well structure layer includes an InN layer, a GaN layer and an InGaN layer arranged on the first barrier layer in sequence. The InN layer has an upper surface connected to the GaN layer. The upper surface is rough. The InGaN layer has a concentration of In atoms in some regions of the InGaN layer which is higher that that in other regions thereof. The P-type semiconductor layer is arranged on the second barrier layer. | 10-11-2012 |
20130092951 | GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. | 04-18-2013 |
20130248922 | FLIP-CHIP SEMICONDUCTOR OPTOELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating flip-chip semiconductor optoelectronic devices initially flip-chip bonds a semiconductor optoelectronic chip attached to an epitaxial substrate to a packaging substrate. The epitaxial substrate is then separated using lift-off technology. | 09-26-2013 |
20130285216 | SEMICONDUCTOR STRUCTURE HAVING LOW THERMAL STRESS - A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer. | 10-31-2013 |
20130313515 | LIGHT EMITTING DIODE WITH MULTIPLE QUANTUM WELL STRUCTURE - An exemplary light emitting diode includes a first type semiconductor layer, a second type semiconductor layer, and a multi quantum well layer sandwiched between the first and second type semiconductor layers. The multi quantum well layer includes a first barrier layer, a second barrier layer, two well layers sandwiched between the first and second barrier layers, and a third barrier layer sandwiched between the two well layers. The first and second barrier layers each have an energy level of conduction band higher than that of the third barrier layer. The first and second barrier layers each have an energy level of valence band higher than that of the third barrier layer. | 11-28-2013 |
20140014899 | MULTI-QUANTUM WELL STRUCTURE AND LIGHT EMITTING DIODE HAVING THE SAME - A multi-quantum well structure includes two first barrier layers, two well layers sandwiched between the two first barrier layers, and a doped second barrier layer sandwiched between the two well layers. The second barrier layer has its conduction band and forbidden band gradually transiting to those of one of the well layers, and a dopant concentration of the second barrier layer gradually changes along a direction from one well layer to the other. The invention also relates to a light emitting diode structure having the multi-quantum well structure. | 01-16-2014 |
20140021486 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate and an eputaxial layer on the substrate. The epitaxial layer includes a N-type GaN-based layer, a light emitting layer, and a P-type GaN-based layer. The LED further includes a first electrode on the N-type GaN-based layer and a second electrode on the P-type GaN-based layer. The P-type GaN-based layer has a inactive portion, and the second electrode is located and covers the inactive portion. | 01-23-2014 |
20140065743 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE DIE - An exemplary method of manufacturing a light emitting diode (LED) die includes steps: providing a preformed LED structure, the LED structure including a first substrate, and a nucleation layer, a buffer layer, an N-type layer, a muti-quantum well layer and an P-type layer formed successively on the first substrate; forming at least one insulation block on the P-type layer; forming a mirror layer on the on the P-type layer and covering the insulation block; forming a conductive second substrate on the mirror layer; removing the first substrate, the nucleation layer and the buffer layer and exposing a bottom surface of the N-type layer; and disposing one N-electrode on the exposed surface of the N-type layer. The N-electrode is located corresponding to the insulation block. | 03-06-2014 |
20140073077 | METHOD FOR EPITAXIAL GROWTH OF LIGHT EMITTING DIODE - A method for epitaxial growth of a light emitting diode, includes following steps: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer in a first temperature; forming a second epitaxial layer on the first epitaxial layer in a second temperature lower than the first temperature, thereby forming a first rough surface on the second epitaxial layer; etching the second epitaxial layer and the first epitaxial layer until a second rough surface is formed on the first epitaxial layer; forming a mask layer on the rough surface of the first epitaxial layer; partly etching the mask layer to form a plurality of protrusions with the first epitaxial layer exposed thereamong; and forming an N-type epitaxial layer, an active layer and a P-type epitaxial layer on the first epitaxial layer in sequence. | 03-13-2014 |
20140131727 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer having an upper part covering top ends of the protrusions; forming a distributed bragg reflective layer on the un-doped GaN layer until the distributed bragg reflective layer totally covering the protrusions and the un-doped GaN layer; etching the distributed bragg reflective layer and the upper part of the un-doped GaN layer to expose the top ends of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the distributed bragg reflective layer. An LED chip formed by the method described above is also provided. | 05-15-2014 |
20140134774 | METHOD FOR MAKING LIGHT EMITTING DIODE CHIP - A method for making a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer partly covering the protrusions to expose a part of each of the protrusions; etching the un-doped GaN layer to expose a top end of each of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the un-doped GaN layer. | 05-15-2014 |
20140141553 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP - A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer totally covering the protrusions; forming a plurality of semiconductor islands on an upper surface of the un-doped GaN layer by self-organized growth, gaps being formed between two adjacent semiconductor islands to expose a part of the upper surface of the un-doped GaN layer; forming an n-type GaN layer on the exposed part of the upper surface of the un-doped GaN layer, the n-type GaN layer being laterally grown to totally cover the semiconductor islands; forming an active layer on an upper surface of the n-type GaN layer; and forming a p-type GaN layer on the active layer. | 05-22-2014 |
20140183445 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - An LED package includes a substrate, a buffer layer formed on the substrate, an epitaxial structure formed on the buffer layer, and a plurality of carbon nanotube bundles formed in the epitaxial structure. | 07-03-2014 |
20150034965 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING SAME - An LED includes a substrate and a semiconductor structure mounted on the substrate. A plurality of first holes and a plurality of second holes are defined in the semiconductor structure. The second holes are located above the first holes and communicate with the first holes. A method for manufacturing the LED is also provided. | 02-05-2015 |
Shin-Hui Huang, Hsinchu TW
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20090243099 | WINDOW TYPE BGA SEMICONDUCTOR PACKAGE AND ITS SUBSTRATE - A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections. | 10-01-2009 |
Shou-Wei Huang, Hsinchu TW
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20090212353 | NON-VOLATILE MEMORY - A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer. | 08-27-2009 |
20110198698 | BIT LINE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures. | 08-18-2011 |
Shui Huang, Hsinchu TW
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20080252807 | Liquid Crystal Display Panel - A liquid crystal display panel is provided. The panel comprises a first substrate and a second substrate which have a display area and a non-display area, which is located around the display area. The panel comprises a plurality of dummy pixel structures in the non-display area to provide a voltage for aligning the liquid crystal materials in the non-display area. | 10-16-2008 |
Te-Hsun Huang, Hsinchu TW
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20090184755 | CURRENT CONTROL APPARATUS APPLIED TO TRANSISTOR - The present invention provides a current control apparatus applied to a transistor. The transistor has a control terminal, a first terminal, and a second terminal. The current control apparatus includes a current control module, a first current mirror module, a second current mirror module, a current subtractor, and a current adjusting module. The current control apparatus provided by the present invention can be applied to a bipolar junction transistor (BJT) to prevent temperature measurement errors from occurring when using a dual current mode temperature measurement method to measure the temperature of the BJT. | 07-23-2009 |
Tzu-Tse Huang, Hsinchu TW
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20090009728 | Projector with an external air filtration device - A projector includes a housing, an internal projection mechanism, and an external air filtration device. The housing has a ventilation window portion. The internal projection mechanism is disposed in the housing, and includes an imaging system, a light source system for providing a light beam to the imaging system, and a ventilating fan. The external air filtration device includes a frame, a filter member, and an engaging unit. The engaging unit engages removably the frame to the ventilation window portion of the housing for securing the filter member on the exterior of the housing between the frame and the ventilation window portion. | 01-08-2009 |
20090213560 | OPTICAL PROJECTOR - An optical projector includes a casing, a partition element, an optical projection module and a main board. The casing includes a main body, a first cover and a second cover. The partition element is disposed at the main body, and the first cover is detachably disposed on the main body. The first cover, the partition element and the main body together define a first accommodating space. The second cover is detachably disposed on the main body. The second cover, the partition element and the main body together define a second accommodating space. The optical projection module is disposed in the first accommodating space and the main board is disposed in the second accommodating space. | 08-27-2009 |
Tzu-Wei Huang, Hsinchu TW
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20110154657 | MANUFACTURING METHOD OF PACKAGE CARRIER - A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer. | 06-30-2011 |
20110154658 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer. | 06-30-2011 |
20110253439 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates. | 10-20-2011 |
20120279630 | MANUFACTURING METHOD OF CIRCUIT SUBSTRATE - A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer. | 11-08-2012 |
20120280022 | MANUFACTURING METHOD OF CIRCUIT SUBSTRATE - A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates. | 11-08-2012 |
Victor Huang, Hsinchu TW
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20100255427 | CONFORMAL PHOTO-SENSITIVE LAYER AND PROCESS - The present disclosure provides a method for etching a substrate. The method includes forming a patterned photo-sensitive layer on the substrate; applying an etching chemical fluid to the substrate, wherein the patterned photo-sensitive layer includes an adhesion promoter and/or hydrophobic additive; removing the etching chemical fluid; and removing the resist pattern. | 10-07-2010 |
Wan-Hua Huang, Hsinchu TW
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20090020826 | Integrated Schottky Diode and Power MOSFET - A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer. | 01-22-2009 |
Wen-Ken Huang, Hsinchu TW
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20110193210 | IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF - The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad. | 08-11-2011 |
Wen-Tso Huang, Hsinchu TW
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20110026578 | METHOD FOR RECEPTION OF LONG RANGE SIGNALS IN BLUETOOTH - The invention of a method for reception of long transmission range Bluetooth signals impaired by multipath are disclosed. The new reception method proposed allows to increase the transmission range for data transmission in Bluetooth. The invention proposes the use of a new FDE adapted to SC transmission without a GI or CP. The proposed FDE very successfully mitigates ISI while being very implemention-friendly. | 02-03-2011 |
Wu-Chen Huang, Hsinchu TW
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20080259542 | PLASMA DISPLAY - A plasma display including a shielding cover, a plasma display panel (PDP) and a circuit board is provided. The shielding cover includes a back plate and a frame, and the frame is connected to the back plate. The PDP is disposed inside the shielding cover and a gap is maintained between the PDP and the shielding cover. The circuit board is disposed between the PDP and the back plate. The shielding cover is grounded through the circuit board. The PDP is grounded via a single point grounding system through the circuit board. | 10-23-2008 |
Yan-Kai Huang, Hsinchu TW
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20090303095 | DISPLAY PANEL DRIVER - A display panel driver including a binary-weighted current-type D/A converter and a source follower with current mirror is provided. The binary-weighted current-type D/A converter receives n input signals and sends a D/A output voltage signal based on 2 | 12-10-2009 |
Yan-Wun Huang, Hsinchu TW
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20110055659 | Method and System of Dynamic Data Storage for Error Correction in a Memory Device - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined. | 03-03-2011 |
20110131459 | Memory Device with Protection Capability and Method of Accessing Data Therein - The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password. | 06-02-2011 |
20130179749 | METHOD AND SYSTEM OF DYNAMIC DATA STORAGE FOR ERROR CORRECTION IN A MEMORY DEVICE - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page. | 07-11-2013 |
Yi Hsiang Huang, Hsinchu TW
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20100149781 | WATERPROOF COMMUNICATION APPARATUS - An electromagnetic interference shielding apparatus for a signal transceiver comprises a metal cover, a chassis, adhesive, and a waveguide output hole. A first combination portion having a first curved section is disposed on the edge of the metal cover. The first curved section of the first combination portion includes at least one opening The edge of the chassis includes a second combination portion having a groove corresponding to the first combination portion. A lateral slot is at the location of the second combination portion corresponding to the opening The adhesive combines the first combination portion and the second combination portion. A waveguide is disposed in the chassis, and extends to the exterior of the chassis through the waveguide output hole. A flat tool can be inserted into a space between one of the openings and a corresponding lateral slot to separate the metal cover from the chassis. | 06-17-2010 |
Yi-Lii Huang, Hsinchu TW
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20080227249 | CMOS Image Sensor White Pixel Performance - Methods and systems for forming a photodiode in a substrate, forming a source/drain region in the substrate and extending over at least a portion of the photodiode, and growing a thermal oxide layer over the photodiode by performing a rapid thermal anneal (RTA) process utilizing an oxidizing environment. | 09-18-2008 |
Yue-Hao Huang, Hsinchu TW
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20080213588 | Synthesis of composite nanofibers for applications in lithium batteries - A uniform composite nanofiber includes a tubular first nanofiber, and a second nanofiber formed inside or outside the first nanofiber. The first nanofiber is first formed within a plurality of nano-scale pores of a template placed on a current collector, and then the second nanofiber is formed on inner or outer surface of the first nanofiber, and the template is removed afterwards for obtaining the composite nanofiber. | 09-04-2008 |
Yu-Fong Huang, Hsinchu TW
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20110180864 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions. | 07-28-2011 |
20110220986 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types. | 09-15-2011 |
20130020624 | MEMORY STRUCTURE - A memory structure having a memory cell region and a non-memory cell region is provided. The memory structure includes a plurality of memory cells and a conductive material. The plurality of memory cells are disposed in the memory cell region, wherein a plurality of first concave portions are present in the plurality of memory cells. The conductive material extends across the memory cell region and the non-memory cell region, covers the plurality of memory cells, and extends into the plurality of first concave portions. | 01-24-2013 |
Yuh-Jeen Huang, Hsinchu TW
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20100080753 | SELF-STARTED PROCESS FOR HYDROGEN PRODUCTION - A self-started process for hydrogen production, which comprises following steps: providing a gas mixture having a methanol/oxygen molar ratio less than or equal to 0.6; and conducting the gas mixture to flow through a Cu/ZnO-based catalyst bed. The Cu/ZnO-based catalyst contains copper, zinc oxide, aluminum oxide, manganese oxide and/or cerium oxide. The Cu/ZnO-based catalyst can initiate the POM reaction; then, the gas mixture will rise to a temperature of over 120° C., and the POM reaction generates a HRG at a reaction temperature of less than or equal to 180° C. The HRG contains less than 4 vol. % CO, and the POM reaction generates 1.8 moles hydrogen or more per 1 mole methanol consumed. | 04-01-2010 |
20100092380 | PROCESS FOR INITIATION OF OXIDATIVE STEAM REFORMING OF METHANOL AT ROOM TEMPERATURE - A self-started OSRM (oxidative steam reforming of methanol) process at room temperature for hydrogen production is disclosed. In the process, an aqueous methanol and oxygen are pre-mixed. The mixture is then fed to a Cu/ZnO-based catalyst to initiate an OSRM process at room temperature. The temperature of the catalyst bed, with suitable thermal isolation, may be raised automatically by the exothermic OSRM to enhance the conversion of methanol. A hydrogen yield of 2.4 moles per mole methanol from the process may be obtained. | 04-15-2010 |
20100179056 | PROCESS FOR INITIATION OF OXIDATIVE STEAM REFORMING OF METHANOL AT ROOM TEMPERATURE - A self-started OSRM (oxidative steam reforming of methanol) process at room temperature for hydrogen production. In the process, an aqueous methanol and oxygen are pre-mixed. The mixture is then fed to a Cu/ZnO-based catalyst to initiate an OSRM process at room temperature. The temperature of the catalyst bed, with suitable thermal isolation, may be raised automatically by the exothermic OSRM to enhance the conversion of methanol. A hydrogen yield of 2.4 moles per mole methanol from the process may be obtained. | 07-15-2010 |
20110212019 | PROCESS FOR INITIATION OF OXIDATIVE STEAM REFORMING OF METHANOL AT EVAPORATION TEMPERATURE OF AQUEOUS METHANOL - A self-started OSRM (oxidative steam reforming of methanol) process at evaporation temperature of aqueous methanol for hydrogen production is disclosed. In the process, an aqueous methanol steam and oxygen are pre-mixed. The mixture is then fed to a Cu/ZnO-based catalyst to initiate an OSRM process at evaporation temperature of aqueous methanol. The temperature of the catalyst bed, with suitable thermal isolation, may be raised automatically by the exothermic OSRM to enhance the conversion of methanol. | 09-01-2011 |
20110295030 | SURFACE MODIFIED NANOPARTICLE AND PREPARATION METHOD THEREOF - A surface modified nanoparticle includes a nanoparticle and a phenol compound used for modifying the nanoparticle. The phenol compound has a formula of (a) or (b), wherein n=1˜9, X is selected from the group consisted of NH | 12-01-2011 |
20110305628 | PROCESS FOR PRODUCING HYDROGEN AT LOW TEMPERATURE - An oxidative steam reforming of methanol (OSRM) process at low temperature includes providing a gas mixture comprising methanol, steam and oxygen and conducting the gas mixture to flow through an AuCu/ZnO-based catalyst for undergoing OSRM process to generate hydrogen, wherein an initiation temperature of OSRM is less than 175° C. The AuCu/ZnO catalyst of the present invention may lower the initiation temperature of the OSRM process and remains to have good catalytic efficiency without undergoing pre-reduction. A steam reforming of methanol (SRM) process is also herein provided. | 12-15-2011 |
20110311440 | PROCESS FOR HYDROGEN PRODUCTION - A process for hydrogen production at lower temperature by using Mn/ZnO, Cu/MnO, Cu/CeO | 12-22-2011 |
Yu Lun Huang, Hsinchu TW
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20090310865 | Video Surveillance System, Annotation And De-Annotation Modules Thereof - A video surveillance system gets a first image from at least a video source, and extracts its image features. It embeds annotation information with at least the image features into the first image, and converts the embedded image into a second image without changing the image format. After having compressed and decompressed the second image, the system extracts the embedded information from the decompressed embedded stream to separate the image and the annotation information, thereby obtaining completely recovered annotation information after a recovery process and an image processing. Because the image format is not changed, the operations on the second image at the rear end of the system, such as compression and decompression, are not affected. | 12-17-2009 |
Yung-Ta Huang, Hsinchu TW
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20110051398 | Backlight Module - A backlight module includes a light guide plate and a flexible illuminating bar. The light guide plate has a light emitting top surface and a plurality of light incident side surfaces. Each of the light incident side surfaces is connected to the light emitting top surface. The flexible illuminating bar includes a circuit board module and a plurality of point light sources. The circuit board module includes a plurality of circuit boards and at least one flexible electrical connection member. The circuit boards are disposed at the light incident side surfaces, respectively. The flexible electrical connection member electrically connects two of the circuit boards and is bendingly disposed between the corresponding two of the circuit boards. The point light sources are electrically disposed on the circuit boards and suitable for emitting light towards the light incident side surfaces. In addition, another backlight module is also provided. | 03-03-2011 |
Zhi-Xian Huang, Hsinchu TW
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20080252664 | Device and Method for Driving Light-Emitting Diodes - A light-emitting diode (LED) driver is provided to drive an LED. The LED driver includes a clock supply to periodically output a modulation period. A brightness controller is provided to receive brightness data corresponding to the desired brightness of the LED. The brightness controller generates a pulse-width-modulated (PWM) duty pulse within the modulation period, a width of the PWM duty pulse being based on the brightness data. The LED driver also includes a detection controller to receive detection data indicating whether the LED is to be detected during the modulation period. When the detection data indicate that the LED is to be detected during the modulation period, the detection controller generates a detection pulse within the modulation period. A driver output is provided to output the PWM duty pulse and the detection pulse to the LED within the modulation period. | 10-16-2008 |