Bonaccio
Anthony R. Bonaccio, Essex Jct., VT US
Patent application number | Description | Published |
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20100277210 | THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION - a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews. | 11-04-2010 |
Anthony R. Bonaccio, Essex Junction, VT US
Patent application number | Description | Published |
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20090254781 | DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY - A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts. | 10-08-2009 |
20090261882 | Skewed Double Differential Pair Circuit for Offset Cancelllation - A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system. | 10-22-2009 |
Anthony Richard Bonaccio, Shelburne, VT US
Patent application number | Description | Published |
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20090058703 | DIGITAL-TO-ANALOG CONVERTER USING DUAL-GATE TRANSISTORS - A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2 | 03-05-2009 |
20090058704 | DESIGN STRUCTURE FOR A DIGITAL-TO-ANALOG CONVERTER USING DUAL-GATE TRANSISTORS - A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2 | 03-05-2009 |
20100228861 | ENVIRONMENTAL AND COMPUTING COST REDUCTION WITH IMPROVED RELIABILITY IN WORKLOAD ASSIGNMENT TO DISTRIBUTED COMPUTING NODES - A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms. | 09-09-2010 |
John M. Bonaccio, Dewitt, NY US
Patent application number | Description | Published |
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20150338315 | ENCLOSURE DIAGNOSTIC AND CONTROL SYSTEMS - An enclosure diagnostic and control system is described herein. The system can include a controller having a storage repository, where the storage repository includes at least one threshold value and at least one algorithm. The system can also include an enclosure communicably coupled to the controller and electrically coupled to a field device. The system can further include a number of sensors communicably coupled to the controller, where the sensors measure a number of field values of a number of parameters associated with the field device. The controller can evaluate the field values using the at least one algorithm to generate an evaluated value. The controller can output a control signal based on the evaluated value. | 11-26-2015 |