Patent application number | Description | Published |
20100277151 | Systems and methods for intelligently optimizing operating efficiency using variable gate drive voltage - Systems and methods for intelligently optimizing voltage regulation efficiency for information handling systems by varying gate drive voltage value based on measured operating efficiency and/or other voltage regulation operating parameters. Different voltage regulation operating parameters may be dynamically monitored and recorded during a power conversion process, and these operating parameters may then be used to dynamically and variably control gate drive voltage level to improve/optimize voltage regulation operating efficiency performance. | 11-04-2010 |
20120098511 | SYSTEMS AND METHODS FOR INTELLIGENTLY OPTIMIZING OPERATING EFFICIENCY USING VARIABLE GATE DRIVE VOLTAGE - Systems and methods for intelligently optimizing voltage regulation efficiency for information handling systems by varying gate drive voltage value based on measured operating efficiency and/or other voltage regulation operating parameters. Different voltage regulation operating parameters may be dynamically monitored and recorded during a power conversion process, and these operating parameters may then be used to dynamically and variably control gate drive voltage level to improve/optimize voltage regulation operating efficiency performance. | 04-26-2012 |
20120290852 | SYSTEM AND METHOD FOR VOLTAGE REGULATOR OPTIMIZATION THROUGH PREDICTIVE TRANSIENT WARNING - In accordance with the present disclosure, a system and method for voltage regulator optimization though predictive transient warning is described. The system may include a transient load, a controller and a voltage regulator. The controller may manage a control state of the transient load and generate a transient notification signal in response to an upcoming transient event at the transient load. The voltage regulator may provide power to the transient load and may change its mode of operation to prepare for the upcoming transient event in response to the transient notification signal. | 11-15-2012 |
20120324246 | SHARED NON-VOLATILE STORAGE FOR DIGITAL POWER CONTROL - Systems and methods may be implemented in a power device subsystem topology to provide an arbitration and communication scheme between a single consolidated non-volatile random access (NVRAM) memory device and multiple discrete digital power controller devices in a manner that provides data protection and the ability to update the full NVRAM content when needed. | 12-20-2012 |
20130207630 | SYSTEMS AND METHODS FOR DYNAMIC MANAGEMENT OF SWITCHING FREQUENCY FOR VOLTAGE REGULATION - Systems and methods are provided that may be implemented to dynamically manage voltage regulator switching frequency. In one embodiment, the disclosed systems and methods may be implemented to dynamically find the optimal voltage regulator switching frequency based on the load current (I | 08-15-2013 |
20140108827 | System and Method for Power Flow Mapping in a Datacenter - A method of power flow mapping in a datacenter includes encoding, by a power supply unit of the datacenter, identification information that uniquely identifies the power supply unit, and modulating the encoded identification information onto a power cable, wherein the power supply unit receives operating power via the power cable. Modulating the encoded information onto the power cable further includes changing a voltage internal to the power supply unit to create a current change in the power cable. | 04-17-2014 |
20140344600 | Multiphase Voltage Regulator Using Coupled Inductors - In response to a condition not being met, asserting a control input of a driver to close a low side switch in a phase leg of a multiphase voltage regulator using coupled inductors, de-asserting the control input in response to a signal to close a high side switch of the phase leg, and asserting the control input in response to a signal to open the high side switch; and in response to the condition not being met, de-asserting the control input, asserting the control input in response to a signal to close a high side switch of another phase leg, and de-asserting the control input in response to a signal to open the high side switch of the other phase leg and to the current in the phase leg being less than a threshold. | 11-20-2014 |
Patent application number | Description | Published |
20090017178 | Method for Reducing the Oil Content of Potato Chips - A method is disclosed which reduces the oil content of a potato chip. The method teaches that a steeper, faster temperature drop upon initial introduction of the potato slice to the fryer, followed by a longer period of exposure to lower temperatures before increasing to standard frying temperatures, reduces oil content of a potato chip. The invention further discloses a pre-treatment method which involves submerging the potatoes in a hot water bath which results in decreased oil content. Additionally, the invention discloses a post-treatment method involving subjecting the potato chip to superheated steam that further reduces oil content. The two pre and post-treatment methods, combined with the primary temperature scheme method for reducing oil content, yield a potato chip with significantly reduced oil content. | 01-15-2009 |
20110281005 | METHOD FOR REDUCING THE OIL CONTENT OF POTATO CHIPS - A method is disclosed which reduces the oil content of a potato chip. The method teaches that a steeper, faster temperature drop upon initial introduction of the potato slice to the fryer, followed by a longer period of exposure to lower temperatures before increasing to standard frying temperatures, reduces oil content of a potato chip. The invention further discloses a pre-treatment method which involves submerging the potatoes in a hot water bath which results in decreased oil content. Additionally, the invention discloses a post-treatment method involving subjecting the potato chip to superheated steam that further reduces oil content. The two pre and post-treatment methods, combined with the primary temperature scheme method for reducing oil content, yield a potato chip with significantly reduced oil content. | 11-17-2011 |
20140037789 | Continuous Process and Apparatus for Making a Pita Chip - A continuous process and the accompanying equipment for making a chip product, such as pita chips. The process involves cutting sheeted dough into continuous longitudinal strips, and cooking them to form hollow tubes. In some embodiments, these tubes are split longitudinally. Also disclosed is a vacuum-assisted splitter. These bread tubes or strips are cured in an accelerated process. The bread tube is trimmed into chip-sized pieces. In one embodiment, the pita bread strips are cut into chip-sized pieces using a continuous, low-pressure water jet cutting system. The resulting chip-sized pieces are nearly uniform in size, shape, and texture. | 02-06-2014 |
Patent application number | Description | Published |
20080197497 | BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS - A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad. | 08-21-2008 |
20080299759 | Method to form a via - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 12-04-2008 |
20080299762 | Method for forming interconnects for 3-D applications - A method for forming an interconnect, comprising (a) providing a substrate ( | 12-04-2008 |
20090170246 | FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FORMATION - A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer. | 07-02-2009 |
20090176366 | MICROPAD FORMATION FOR A SEMICONDUCTOR - A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips. | 07-09-2009 |
20090218567 | CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MAKING THE SAME - A method for making a semiconductor device ( | 09-03-2009 |
20110151663 | METHOD TO FORM A VIA - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 06-23-2011 |
20110198751 | BOND PAD WITH MULTIPLE LAYER OVER PAD METALLIZATION AND METHOD OF FORMATION - A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad. | 08-18-2011 |
20130193576 | ENCAPSULANT WITH COROSION INHIBITOR - A packaged electronic device including an electronic device, a conductive structure, and an encapsulant. The encapsulant has chlorides and a negatively-charged corrosion inhibitor for preventing corrosion of the conductive structure. | 08-01-2013 |
20130319129 | MOLD COMPOUND COMPATIBILITY TEST SYSTEM AND METHODS THEREOF - A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined. | 12-05-2013 |
20140061894 | HEAT SPREADER FOR USE WITHIN A PACKAGED SEMICONDUCTOR DEVICE - A packaged semiconductor device, comprising a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die. | 03-06-2014 |
20140145339 | ENCAPSULANT FOR A SEMICONDUCTOR DEVICE - A mold compound is provided for encapsulating a semiconductor device ( | 05-29-2014 |
20140242777 | Method for Bonding Semiconductor Devices - A method of attaching first and second semiconductor devices to one another includes applying plating gel over a surface of a first semiconductor device, positioning bonding regions of a second semiconductor device in contact with the plating gel on corresponding bonding regions on the first semiconductor device, and reacting at least some the plating gel to bond the second semiconductor device to the first semiconductor device. | 08-28-2014 |
20140346663 | SEMICONDUCTOR STRUCTURE WITH SACRIFICIAL ANODE AND METHOD FOR FORMING - A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode. | 11-27-2014 |
20140367859 | TIN-BASED WIREBOND STRUCTURES - Tin-based wirebond structures and wirebonds formed thereon. In some embodiments, an electronic package includes a semiconductor die located over a substrate and a wire configured to couple a terminal of the semiconductor die to a bond pad on the substrate. A wire bond between the wire and the bond pad may include an amount of tin originated from a layer of tin alloy formed on the bond pad. In other embodiments, a wirebond structure may include a conductive layer and a layer of tin alloy located over a portion of the conductive layer. The layer of tin alloy may provide a wirebonding contact surface configured to receive a bond wire. | 12-18-2014 |
20150027767 | SYSTEM AND METHOD FOR LEAD FRAME PACKAGE DEGATING - A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide. | 01-29-2015 |
20150118791 | METHOD FOR TREATING A BOND PAD OF A PACKAGE SUBSTRATE - A method of making a package substrate having a copper bond pad and a location for receiving a semiconductor die having a remnant of one of a group consisting of HEDP and an HEDP derivative on a top surface of the copper bond pad. The semiconductor die is attached to the substrate. A wirebond connection is attached between the remnant and the semiconductor die. | 04-30-2015 |