Patent application number | Description | Published |
20140164132 | Client-Side Advertising Decisions - In one embodiment, a method includes a client computing device receiving one or more advertisements for presentation to a user associated with the client computing device. The client computing device selects from among the received advertisements for presentation to the user based on information stored locally on the client computing device and associated with a value of the advertisements with respect to the user. The client computing device then presents to the user one or more of the selected advertisements to the user. | 06-12-2014 |
20140164141 | Software Application Notifications - In one embodiment, a method includes a server computing system receiving a notification from a software application on a client computing device associated with a first user. The notification indicates a user interaction with the application has occurred. At least one of the application's functionalities related to the notification complies with one or more specifications of a software development kit. The server system generates a content object associated with the event and the first user for presentation to one or more second users, with the content object promoting the software application or a provider of the software application to the second user. The server system them provides the content object for presentation to the second users. | 06-12-2014 |
20140164481 | Organizing Application-Reported Information - In one embodiment, a method includes a server computing device receiving several notifications from several different software applications on a client computing device associated with a user. A notification is sent by a software application on a client computing, indicates a user interaction with a software application has occurred, and identifies the application sending the notification. The server correlates each received notification with the appropriate user and stores information associated with the correlated notification. | 06-12-2014 |
20140365311 | Associating Advertisements with Events - In one embodiment, a method includes receiving a notification identifying the occurrence of a user-initiated event associated with a software application that complies with the specifications of a software development kit. The user is identified based at least in part on the information included the notification. The method includes determining whether the event is attributable to an electronic advertisement, and when the event is attributable to the advertisement, the method include determining whether the electronic advertisement is associated with information identifying the advertisement or an advertising campaign that the advertisement is a part of When the electronic advertisement is associated with the information, the method includes notifying an advertiser associated with the electronic advertisement or a developer associated with the software application that the information identifying the advertisement is associated with the event. | 12-11-2014 |
20140365358 | METHODS AND SYSTEMS FOR CONTEXT-BASED CHECK-OUT FLOWS USING A PASS-THROUGH PAYMENT GATEWAY - Methods and systems for context-based check-out flows using a pass-through payment gateway (PTPG) are described. One method in a user computing device includes transmitting a probability request for a user to a network application seeking an indication of whether the user would likely utilize payment information stored by the network application while placing an order using a commerce application. Upon receiving a response, the commerce application presents a UI element indicating that the user may utilize the stored payment information to complete the order. Another method in a PTPG includes receiving a request from a commerce application to charge a user for an order. In response, the gateway transmits a charge request to an identified payment gateway system for the commerce application on behalf of the commerce application such that a monetary amount is credited to an account of the commerce application directly by the payment gateway system. | 12-11-2014 |
20150052036 | DYNAMICALLY PROVIDING A THIRD-PARTY CHECKOUT OPTION - Methods for facilitating financial transactions include facilitating or otherwise increasing the ease and speed of checkout processes. In particular, one or more implementations comprise an e-commerce payment facilitator that acts as an intermediary between a commerce application and a payment gateway. The e-commerce payment facilitator can provide stored payment information to a commerce application based on a few simple selections by a user. This allows a user to easily and securely complete commerce transactions, which simplifies the user's checkout experience and reduces barriers to purchase. Furthermore, the e-commerce payment facilitator can pass payment details to the commerce application's payment gateway. In addition to the foregoing, methods involve dynamically and intelligently providing a user the option of using payment information stored by the network application. | 02-19-2015 |
20150052061 | METHODS AND SYSTEMS FOR FACILITATING E-COMMERCE PAYMENTS - Methods for facilitating financial transactions include facilitating or otherwise increasing the ease and speed of checkout processes. In particular, one or more implementations comprise an e-commerce payment facilitator that acts as an intermediary between a commerce application and a payment gateway. The e-commerce payment facilitator can provide stored payment information to a commerce application based on a few simple selections by a user. This allows a user to easily and securely complete commerce transactions, which simplifies the user's checkout experience and reduces barriers to purchase. Furthermore, the e-commerce payment facilitator can pass payment details to the commerce application's payment gateway. In addition to the foregoing, methods involve dynamically and intelligently providing a user the option of using payment information stored by the network application. | 02-19-2015 |
20150100458 | SYSTEMS AND METHODS FOR USING A SOCIAL NETWORKING SYSTEM TO PURCHASE PRODUCTS - Embodiments of the present invention relate generally to marketing products through a social networking system. More specifically, one or more embodiments of the present invention relate to allowing social networking users to purchase products through the social networking system and to add products to shopping carts associated with third-party merchants. | 04-09-2015 |
Patent application number | Description | Published |
20080231308 | Sub-Sampling of Weakly-Driven Nodes - A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing. | 09-25-2008 |
20090013214 | ON-CHIP SAMPLERS FOR ASYNCHRONOUSLY TRIGGERED EVENTS - Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base. | 01-08-2009 |
20110135315 | OPTICAL RECEIVER WITH A CALIBRATION MODE - An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit. | 06-09-2011 |
20110135320 | TECHNIQUE FOR CALIBRATING AND CENTERING AN OPTICAL RECEIVER - A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver. | 06-09-2011 |
20120315052 | INPUT ISOLATION OF A TRANSIMPEDANCE AMPLIFIER IN OPTICAL RECEIVERS - An optical receiver is described. This optical receiver has two operating modes: a calibration mode and a normal mode. During the normal mode, switches are used to electrically couple an input of a transimpedance amplifier (TIA) to an optical-to-electrical (OE) converter that receives an optical signal and provides a corresponding analog electrical signal. Moreover, during the calibration mode, the switches are used to electrically isolate the input of the TIA from the OE converter while maintaining a feedback path from an output of the TIA to the input of the TIA, thereby ensuring proper bias of the TIA during calibration. Furthermore, a frequency response of the TIA during the normal mode is substantially unchanged over an operating bandwidth of the TIA by the capability to electrically isolate the input of the TIA from the OE converter during the calibration mode. | 12-13-2012 |
20130038920 | PULSE-WIDTH-MODULATED THERMAL TUNING OF OPTICAL DEVICES - An optical device that includes a wavelength-sensitive optical component, which has an associated thermal time constant, is described. Note that an operating wavelength of the wavelength-sensitive optical component is a function of several physical parameters including temperature. Moreover, the optical device includes a heating mechanism that provides heat to the wavelength-sensitive optical component. Furthermore, the optical device includes a driver circuit that provides a pulse-width modulated signal to the heating mechanism. Note that an average pulse-width modulated heat provided by the heating mechanism, and which corresponds to the pulse-width modulated signal, thermally tunes the wavelength-sensitive optical component to a target operating wavelength. Additionally, note that the target operating wavelength corresponds to a target operating temperature of the wavelength-sensitive optical component. | 02-14-2013 |
20140269956 | EFFICIENT NOISE CANCELING CIRCUIT FOR RECEIVERS - The disclosed embodiments provide a system that tracks and compensates for input signal noise at a receiver of a data communication channel. In particular embodiments, the receiver of the data communication link receives an input signal which comprises two signal levels. Next, for each of the two signal levels, the system generates an error signal by comparing the input signal value of the signal level with an expected signal value for the signal level. The system then updates a threshold signal value based on at least one of the two error signals associated with the two signal levels. Finally, the system compensates for input signal noise in the received input signal using the updated threshold signal value. | 09-18-2014 |
20140312982 | CONTINUOUS PHASE ADJUSTMENT BASED ON INJECTION LOCKING - A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter. | 10-23-2014 |
20140314191 | DISTRIBUTED PHASE-CORRECTION CIRCUIT - A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line. | 10-23-2014 |
20140321803 | HYBRID-INTEGRATED PHOTONIC CHIP PACKAGE WITH AN INTERPOSER - A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects. | 10-30-2014 |
20150160482 | WAVELENGTH-LOCKING A RING-RESONATOR MODULATOR - In the optical device, a ring-resonator modulator, having an adjustable resonance (center) wavelength, optically couples an optical signal that includes the carrier wavelength from an input optical waveguide to an output optical waveguide. A monitoring mechanism in the optical device, which is optically coupled to the output optical waveguide, monitors a performance metric of an output optical signal from the output waveguide. For example, the monitoring mechanism may monitor: an average optical power associated with the output optical signal, and/or an amplitude of the output optical signal. Moreover, control logic in the optical device adjusts the resonance wavelength based on the monitored performance metric so that the performance metric is optimized. | 06-11-2015 |
20160112142 | OPTICAL RECEIVER WITH ADJUSTABLE PULSE-WIDTH FEEDBACK - An optical receiver includes a feedback circuit that applies a feedback signal to a front-end circuit prior to the front-end circuit converting an optical signal into an analog electrical signal. In particular, the optical receiver includes a digital slicer that determines a digital electrical signal from the analog electrical signal based on a reference voltage that specifies a decision threshold and a clock that specifies sampling times. The feedback circuit determines the feedback signal at least one previous bit preceding a current bit in the analog electrical signal that is provided by the digital slicer and an impulse response of a communication channel. Moreover, the feedback signal has a pulse width that is less than a bit time of the clock. In this way, the optical receiver can cancel post-cursors of the current bit, even when the communication channel includes a low-pass filter. | 04-21-2016 |
Patent application number | Description | Published |
20080248100 | MAGNESIUM COMPOSITIONS AND USES THEREOF - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 10-09-2008 |
20080248137 | Magnesium-Containing Food Compositions - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 10-09-2008 |
20080249169 | MAGNESIUM COMPOSITIONS AND USES THEREOF FOR METABOLIC DISORDERS - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 10-09-2008 |
20080249170 | MAGNESIUM COMPOSITIONS AND USES THEREOF FOR NEUROLOGICAL DISORDERS - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 10-09-2008 |
20080249178 | MAGNESIUM COMPOSITIONS AND USES THEREOF FOR INCREASING LIFESPAN - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 10-09-2008 |
20080269327 | MAGNESIUM COMPOSITIONS AND USES THEREOF FOR COGNITIVE FUNCTION - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 10-30-2008 |
20110020443 | SLOW RELEASE MAGNESIUM COMPOSITION AND USES THEREOF - The present invention provides compositions that contain magnesium and threonate, or a threonate precursor molecule, formulated for extended or modified release to provide physiological concentrations over a desired time period. The extended release or modified release form is particularly useful in providing Mg to a subject while avoiding adverse side effects such as diarrhea. | 01-27-2011 |
20120157533 | Magnesium Compositions and Uses Thereof for Metabolic Disorders - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 06-21-2012 |
20120171307 | Magnesium Compositions and Uses Thereof for Neurological Disorders - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 07-05-2012 |
20130236542 | SLOW RELEASE MAGNESIUM COMPOSITION AND USES THEREOF - The present invention provides compositions that contain magnesium and threonate, or a threonate precursor molecule, formulated for extended or modified release to provide physiological concentrations over a desired time period. The extended release or modified release form is particularly useful in providing Mg to a subject while avoiding adverse side effects such as diarrhea. | 09-12-2013 |
20140342021 | MAGNESIUM COMPOSITIONS AND USES THEREOF FOR NEUROLOGICAL DISORDERS - A composition for administration to a subject, such as oral administration to a subject, for example, has been provided. Such a composition may comprise at least one magnesium-counter ion compound. A magnesium-counter ion composition described herein may be useful for any of a variety of applications provided herein, such as maintaining, enhancing, and/or improving health, nutrition, and/or another condition of a subject, and/or cognitive, learning, and/or memory function. A magnesium-counter ion composition provided herein may be useful for administration to a subject presenting magnesium deficiency, mild cognitive impairment, Alzheimer's disease, attention deficit hyperactivity disorder, ALS, Parkinson's disease, diabetes, migraine, anxiety disorder, mood disorder, and/or hypertension. A kit, method, and other associated technology are also provided. | 11-20-2014 |
Patent application number | Description | Published |
20100229147 | SYSTEM AND METHOD FOR CREATING A FOCUS-EXPOSURE MODEL OF A LITHOGRAPHY PROCESS - A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window. | 09-09-2010 |
20110099526 | Pattern Selection for Full-Chip Source and Mask Optimization - The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result. | 04-28-2011 |
20110107280 | Selection of Optimum Patterns in a Design Layout Based on Diffraction Signature Analysis - The present invention relates generally to selecting optimum patterns based on diffraction signature analysis, and more particularly to, using the optimum patterns for mask-optimization for lithographic imaging. A respective diffraction map is generated for each of a plurality of target patterns from an initial larger set of target patterns from the design layout. Diffraction signatures are identified from the various diffraction maps. The plurality of target patterns is grouped into various diffraction-signature groups, the target patterns in a specific diffraction-signature group having similar diffraction signature. A subset of target patterns is selected to cover all possible diffraction-signature groups, such that the subset of target patterns represents at least a part of the design layout for the lithographic process. The grouping of the plurality of target patterns may be governed by predefined rules based on similarity of diffraction signature. The predefined rules comprise coverage relationships existing between the various diffraction-signature groups. | 05-05-2011 |
20120017183 | System and Method for Creating a Focus-Exposure Model of a Lithography Process - A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window. | 01-19-2012 |
20120216156 | Method of Pattern Selection for Source and Mask Optimization - The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns. | 08-23-2012 |
20130185681 | CORRECTION FOR FLARE EFFECTS IN LITHOGRAPHY SYSTEM - A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields. | 07-18-2013 |
20130212543 | LENS HEATING AWARE SOURCE MASK OPTIMIZATION FOR ADVANCED LITHOGRAPHY - A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied. | 08-15-2013 |
20130311958 | PATTERN SELECTION FOR FULL-CHIP SOURCE AND MASK OPTIMIZATION - The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result. | 11-21-2013 |
20150058815 | CORRECTION FOR FLARE EFFECTS IN LITHOGRAPHY SYSTEM - A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. | 02-26-2015 |
20160026750 | PATTERN SELECTION FOR FULL-CHIP SOURCE AND MASK OPTIMIZATION - The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result. | 01-28-2016 |
Patent application number | Description | Published |
20090327535 | ADJUSTABLE READ LATENCY FOR MEMORY DEVICE IN PAGE-MODE ACCESS - A read process in a memory device is optimized. Sub-pages of a page of data are read from storage elements by an internal controller of the memory device at a read speed of the internal controller. At a specific time, the controller sets a READY signal to inform an external host to start reading out data from the buffer in a continuous burst, at the associated read speed of the host, which can differ from the controller's read speed, and asynchronous to the internal controller. The READY signal is set so that the host can complete its burst before the buffer runs out of data, while overall read time is minimized. The controller can also be configured for use with hosts having different read speeds. A host may communicate an identifier to the controller for use in determining an optimum time to set the READY signal. | 12-31-2009 |
20110141788 | PAGE REGISTER OUTSIDE ARRAY AND SENSE AMPLIFIER INTERFACE - A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits. | 06-16-2011 |
20110141832 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 06-16-2011 |
20120154022 | Charge Pump System that Dynamically Selects Number of Active Stages - A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used drive the external load, while the slave section drives an adjustable internal load. The adjustable load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly. | 06-21-2012 |
20120224408 | THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE - A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed. | 09-06-2012 |
20120236624 | Balanced Method for Programming Multi-Layer Cell Memories - Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm. | 09-20-2012 |
20120236663 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 09-20-2012 |
20120243349 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 09-27-2012 |
20120275210 | NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING - A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits. | 11-01-2012 |
20140185351 | NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING - A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits. | 07-03-2014 |
20140269106 | Program Cycle Skip Evaluation Before Write Operations In Non-Volatile Memory - A non-volatile memory system is disclosed that evaluates during a read before write operation whether to skip programming of portions of group of memory cells during a subsequent write operation. By evaluating skip information during a read before write operation, the write operation can be expedited. The additional overhead for evaluating skip information is consumed during the read before write operation. By performing a skip evaluation during the read before write operation, a full analysis of the availability of skipping programming for memory cells can be performed. Skip evaluations in different embodiments may be performed for entire bay address cycles, column address cycles, and/or sense amplifier address cycles. In some embodiments, some skip evaluations are performed during read before write operations while others are deferred to the write operation. In this manner, the number of data latches for storing skip information can be decreased. | 09-18-2014 |
20140281135 | Dynamic Address Grouping For Parallel Programming In Non-Volatile Memory - A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses. | 09-18-2014 |
20150036414 | SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY - A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated. | 02-05-2015 |
20150179254 | MITIGATING DISTURB EFFECTS FOR NON-VOLATILE MEMORY - A method includes adjusting a counter value to indicate an access operation to a first portion of a non-volatile memory. The access operation is an erase operation or a write operation. The adjusted counter value indicates that a number of access operations to the first portion have been performed since an access operation to a second portion of the non-volatile memory has been performed. The method also includes selectively initiating a remedial action to the second portion in response to a comparison of the number of access operations to a threshold. | 06-25-2015 |
20150179260 | SYSTEMS AND METHODS OF SHAPING DATA - A method of shaping data includes receiving data represented as a first set of bits, where each bit of the first set of bits corresponds to a logical value. A first write current to write a first logical value to a storage element is less than a second write current to write a second logical value to the storage element. The method also includes applying a shaping operation to generate a second set of bits, where a proportion of bits having the first logical value is larger for the second set of bits than for the first set of bits. The method also includes writing the second set of bits to the memory. | 06-25-2015 |
20150287459 | Methods For Programming ReRAM Devices - A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed. | 10-08-2015 |
20160093372 | READING RESISTIVE RANDOM ACCESS MEMORY BASED ON LEAKAGE CURRENT - A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current. | 03-31-2016 |
20160093373 | APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS - A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times. | 03-31-2016 |
20160109926 | MODIFIED WRITE PROCESS BASED ON A POWER CHARACTERISTIC FOR A DATA STORAGE DEVICE - A data storage device includes a memory die. The memory die includes a resistive memory. A method includes determining a power characteristic associated with performing a write process to write data to the resistive memory. The method further includes initiating a modified write process in response to detecting that the power characteristic satisfies a threshold. | 04-21-2016 |
20160111150 | DUAL POLARITY READ OPERATION - A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory. | 04-21-2016 |