Patent application number | Description | Published |
20100264988 | Low noise cascode amplifier - The present invention relates to a low noise cascode amplifier comprising a first transistor, a second transistor, a third transistor, a first inductor, and a second inductor. Furthermore, the first transistor can connect with the second transistor via the first inductor, and the second transistor can connect with the third transistor via the second inductor; thereby, a cascode device can be formed. The inductor and the parasitic capacitances can resonate at high frequency, so that the noise figure of the cascode amplifier can be reduced. | 10-21-2010 |
20100277840 | V-Band Radio Frequency Electrostatic Discharge Protection Circuit - A V-band radio frequency (RF) electrostatic discharge (ESD) protection circuit uses meander inductors and diodes connecting in series to provide ESD protection. When operated in low frequency, the static electricity input from a RF pad may discharge to ground or to a voltage VDD through the meander inductor and the diode, so that a core circuit does not be damaged by ESD. When operated in high frequency, the high frequency stray effect of the core circuit is substantially reduced due to impedance isolation generated by the meander inductors. Therefore, a low-noised amplifier (LNA) can receive an accurate high frequency input signal. | 11-04-2010 |
20110181990 | BAND-PASS STRUCTURE ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a band-pass structure electrostatic discharge protection circuit. An ESD protection circuit is disposed at the input of a radio frequency (RF) core circuit. The ESD protection circuit comprises a plurality of diodes and inductors constructing a plurality of discharging paths, wherein the diodes and inductors forms a band-pass filter structure. Such that, the RF core circuit with the ESD protection circuit of the present invention feature much higher ESD robustness and better RF performance than the conventional design. | 07-28-2011 |
20110211285 | LOW PARASITIC CAPACITANCE ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a low parasitic capacitance electrostatic discharge protection circuit. An ESD protection circuit is established with the structure in accordance with the present invention comprising a plurality of discharging paths. The ESD protection circuit is connected to the input/output pad of a radio frequency (RF) core circuit. Such that, the RF core circuit with the ESD protection circuit of the present invention feature much higher ESD robustness. And the parasitic capacitance of the ESD protection is reduced because of the structure of the present invention. | 09-01-2011 |
Patent application number | Description | Published |
20130257564 | POWER LINE FILTER FOR MULTIDIMENSIONAL INTEGRATED CIRCUITS - An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer. | 10-03-2013 |
20140239427 | Integrated Antenna on Interposer Substrate - Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane. | 08-28-2014 |
20150153407 | Contactless Signal Testing - A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within an electron beam, converting an electrical current created by the e-beam to a voltage with a number of diodes connected to a positive voltage supply, extracting a digital test signal from the voltage signal with a digital inverter, and passing the test signal to digital circuitry within the integrated circuit. | 06-04-2015 |
20150214288 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and methods of forming the same are described. A semiconductor arrangement includes a first tier including a first capacitor, a second tier over the first tier, the second tier including a second capacitor, and a first substrate between the first tier and the second tier. The first capacitor is connected to the second capacitor through the substrate. A plurality of tiers are contemplated, such that a total capacitance of the semiconductor arrangement increases based upon interconnection of metal layers of different tiers. Additionally, the semiconductor arrangement has a greater area efficiency as compared to multiple capacitors in parallel. | 07-30-2015 |