Patent application number | Description | Published |
20110149268 | DYNAMIC 3D WIND MAPPING SYSTEM AND METHOD - Systems for obtaining data regarding a volume of atmosphere can include a lidar transceiver. Some systems include scanning devices that are capable of directing laser beams produced by the lidar transceiver in a pattern that sweeps through the volume of atmosphere. Information regarding light that is backscattered from the laser beams can be used to construct a three-dimensional data set. In some methods, wind-field information can be extracted from the three-dimensional data set. | 06-23-2011 |
20120120230 | Apparatus and Method for Small Scale Wind Mapping - An apparatus and method for wind profiling using a lighter than air tracer balloon moving under the influence of air currents. A retroreflective target is attached to the tracer balloon to improve the intensity of a return signal reflected back to the rangefinder. After the balloon is released, the rangefinder and attitude sensor are used to measure the range and direction angles of the retroreflective target on the tracer balloon at periodic time intervals. The recorded trajectory data are processed by a computer program using data smoothing and filtering techniques to calculate the wind velocity components, horizontal wind speed and direction, and an estimate of wind shear, | 05-17-2012 |
20120250015 | High-Resolution Spectral Volume Sampling - For high-resolution spectral volume sampling, a band-pass filter spectrally filters electromagnetic radiation from a scene to wavelengths within a specified wavelength range. A slit array is located at an image of the scene and includes a plurality of slits arranged in parallel. Each slit has a specified width and a specified spacing between slits. Each slit further transmits the electromagnetic radiation. A dispersion device disperses the transmitted electromagnetic radiation from the slit array with a specified dispersion while focusing the transmitted electromagnetic radiation onto a detector array so that each wavelength of electromagnetic radiation from each slit is focused as a unique, non-overlapping line on the detector array. | 10-04-2012 |
20130027793 | Multiple Optical Beam Folding Apparatus and Method - A multiple optical beam folding apparatus for directing optical energy includes two or more radiation collectors configured to direct radiant energy through two or more independent optical paths to a shared focal plan array (FPA). The radiation collectors may include one or more gas cells or vacuum cells. One or more of the two or more optical paths may include a Galilean telescope. First and second reflecting surfaces are positioned in each of the two or more independent optical paths. The first reflecting surfaces are distinct reflecting surfaces from the second reflecting surfaces and the first and second reflecting surfaces are configured to direct the radiant energy of their respective independent optical paths to the FPA. The two or more second reflecting surfaces may be distinct surfaces of a pyramidal mirror. | 01-31-2013 |
20150022809 | Split Field Spectral Imager - An apparatus for spectroscopic Doppler imaging comprises collection and focusing optics, a field splitter configured to form a composite image from multiple fields of view, and a Fabry-Perot etalon configured to spatially modulate the incoming light in order to analyze the spectral content of the light from spatially resolved regions of a scene. Methods for Doppler imaging of a scene comprise split-field imagery and scene scanning techniques to create a spatially resolved spectral profile spectra of a scene, useful for measuring and profiling wind vectors and temperatures within the scene. | 01-22-2015 |
Patent application number | Description | Published |
20090230465 | Trench-Gate Field Effect Transistors and Methods of Forming the Same - A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region. | 09-17-2009 |
20100258862 | TRENCH-GATE FIELD EFFECT TRANSISTOR WITH CHANNEL ENHANCEMENT REGION AND METHODS OF FORMING THE SAME - A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region. | 10-14-2010 |
20100264490 | LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN - A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region. | 10-21-2010 |
20100317168 | LATERAL DRAIN MOSFET WITH IMPROVED CLAMPING VOLTAGE CONTROL - A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body. | 12-16-2010 |
20110014764 | METHOD OF FORMING A DUAL-TRENCH FIELD EFFECT TRANSISTOR - A method of forming a field effect transistor includes forming a well region in a semiconductor region of a first conductivity type. The well region may be of a second conductivity type and have an upper surface and a lower surface. The method also includes forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region, and forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below the plurality of gate trenches. The plurality of stripe trenches may be laterally spaced from the plurality of gate trenches. The method also includes at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type. The semiconductor material of the second conductivity type may form a PN junction with a portion of the semiconductor region. | 01-20-2011 |
20110171798 | LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN - A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region. | 07-14-2011 |
20110177662 | Method of Forming Trench-Gate Field Effect Transistors - A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region. | 07-21-2011 |
20120104490 | Trench-Gate Field Effect Transistors and Methods of Forming the Same - A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region. | 05-03-2012 |
20120220091 | METHODS OF MAKING POWER SEMICONDUCTOR DEVICES WITH THICK BOTTOM OXIDE LAYER - A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. | 08-30-2012 |
20130248991 | STRUCTURE AND METHOD FOR FORMING TRENCH-GATE FIELD EFFECT TRANSISTOR - A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric. | 09-26-2013 |
Patent application number | Description | Published |
20090020810 | Method of Forming Power Device Utilizing Chemical Mechanical Planarization - A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench. | 01-22-2009 |
20090035900 | Method of Forming High Density Trench FET with Integrated Schottky Diode - A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween. | 02-05-2009 |
20100311216 | Method for Forming Active and Gate Runner Trenches - A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region. | 12-09-2010 |
20120058615 | Method of Forming Shielded Gate Power Transistor Utilizing Chemical Mechanical Planarization - A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches. | 03-08-2012 |