Patent application number | Description | Published |
20110302544 | POST-PLACEMENT CELL SHIFTING - A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells. | 12-08-2011 |
20110302545 | DETAILED ROUTABILITY BY CELL PLACEMENT - A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing. | 12-08-2011 |
20120124539 | Clock Optimization with Local Clock Buffer Control Optimization - A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers. | 05-17-2012 |
20120144358 | Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs - A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated. | 06-07-2012 |
20120266124 | Placement of Structured Nets - Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells. | 10-18-2012 |
20120324409 | ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION - The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration. | 12-20-2012 |
20130086537 | Design Routability Using Multiplexer Structures - Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation. | 04-04-2013 |
20130086544 | CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL ROUTING - Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge. | 04-04-2013 |
20130086545 | EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTION HISTOGRAMS - Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools. | 04-04-2013 |
20130283225 | DATAPATH PLACEMENT USING TIERED ASSIGNMENT - Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information. | 10-24-2013 |
20130326455 | ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION - An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints. | 12-05-2013 |
20130346938 | POST-PLACEMENT CELL SHIFTING - A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells. | 12-26-2013 |
20140007036 | SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN INTERMEDIATE PLACEMENT OF AN INTEGRATED CIRCUIT DESIGN | 01-02-2014 |
20140149957 | STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS - A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design. | 05-29-2014 |
20140195998 | Automatic Generation of Wire Tag Lists for a Metal Stack - Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design. | 07-10-2014 |
20140223397 | Automatic Generation of Wire Tag Lists for a Metal Stack - Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design. | 08-07-2014 |
20150113491 | COMPUTER-BASED MODELING OF INTEGRATED CIRCUIT CONGESTION AND WIRE DISTRIBUTION FOR PRODUCTS AND SERVICES - A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion. | 04-23-2015 |
20150143326 | EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNTHESIS - A slew-based effective capacitance (C | 05-21-2015 |
20150199465 | BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS - Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO. | 07-16-2015 |
Patent application number | Description | Published |
20100262944 | OBJECT PLACEMENT IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement. | 10-14-2010 |
20120110532 | LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS - A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one. | 05-03-2012 |
20120240093 | ROUTING AND TIMING USING LAYER RANGES - A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an application executing in a data processing system, a score is computed for a net in a set of nets routed using a set of layers in the design. The set of nets is sorted according to scores associated with nets in the set of nets. A layer range from a set of layer ranges is assigned to a net in the sorted list such that a net with a higher than threshold score is assigned a high layer range. | 09-20-2012 |
20120284683 | TIMING DRIVEN ROUTING IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design. | 11-08-2012 |
20120297355 | WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN - A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved. | 11-22-2012 |
20130086543 | MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design. | 04-04-2013 |
20130096976 | COST-EFFECTIVE AND RELIABLE UTILITIES DISTRIBUTION NETWORK - A method, system, and computer program product for designing a cost-effective and reliable distribution network for a utility are provided in the illustrative embodiments. A graph connecting a set of consumers of the utility with a set of suppliers of the utility is reduced to form a plurality of clusters. A first network between a supplier and a subset of consumers in a first cluster in the plurality of clusters is improved, the improving adding a first connection in the first network to provide continuity of supply of the utility to the subset of consumers after a predetermined number of failures in the first network. A design is generated for a second network connecting the set of suppliers to the set of consumers, the second network including the first network after the improving, wherein the second network has a cost that is within a lower threshold and an upper threshold. | 04-18-2013 |
20130272126 | CONGESTION AWARE ROUTING USING RANDOM POINTS - In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin. | 10-17-2013 |
20130275934 | SOLVING CONGESTION USING NET GROUPING - A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected from a set of congested g-edges. A set of congesting nets is selected, wherein the set of congesting nets cause congestion in the selected congested g-edges by crossing the selected congested g-edge. A vacancy data structure corresponding to the selected congested g-edge is populated. A subset of the set of the congesting nets is selected. The subset of the set of the congesting nets is rerouted to a candidate g-edge identified in the vacancy data structure. | 10-17-2013 |
20130326450 | EARLY DESIGN CYCLE OPTIMZATION - Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component. | 12-05-2013 |
20130326456 | DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK - An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads. | 12-05-2013 |
20140071827 | SOLVING NETWORK TRAFFIC CONGESTION USING DEVICE GROUPING - A method, system, and computer program product for solving a network traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested network route section is selected from a set of congested network route sections. A set of congesting devices is selected, where the set of congesting devices causes congestion in the selected congested network route sections by using the selected congested network route section. A vacancy data structure corresponding to the selected congested network route section is populated. A subset of the set of the congesting devices is selected. The subset of the set of the congesting devices is rerouted to a candidate network route section identified in the vacancy data structure. | 03-13-2014 |
20140074389 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-13-2014 |
20140081478 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-20-2014 |
20140088791 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-27-2014 |
20140101629 | EARLY DESIGN CYCLE OPTIMZATION - Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component. | 04-10-2014 |
20140143746 | DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN - A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis. | 05-22-2014 |
20140181772 | DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN - A design tool with an initial sink locator unit determines a number of clock buffers for driving clock signals to loads in a clock distribution network. The design tool determines clusters of loads in the clock distribution network, wherein the number of clusters is equal to the number of clock buffers and the loads are uniformly distributed amongst the clusters. The design tool determines centers of the clusters as initial candidate sink locations for the clock buffers. The design tool iteratively determines new clusters and determines centers of the new clusters as optimized initial candidate sink locations. | 06-26-2014 |
Patent application number | Description | Published |
20080269572 | MULTIPURPOSE HOST SYSTEM FOR INVASIVE CARDIOVASCULAR DIAGNOSTIC MEASUREMENT ACQUISITION INCLUDING AN ENHANCED DYNAMICALLY CONFIGURED GRAPHICAL DISPLAY - The present invention provides a multipurpose host system for processing and displaying invasive cardiovascular diagnostic measurement data. The system includes a an external input signal bus interface. The bus interface receives data arising from cardiovascular diagnostic measurement sensors. Measurement processing components receive data from particular sensor types. Based on the received data, the processing components render diagnostic measurement parameter values. A multi-mode graphical user interface includes display components corresponding to data received from particular sensor types. The user interface provides recommended action prompts that guide a user through a series of actions. | 10-30-2008 |
20110319773 | Multipurpose Host System for Invasive Cardiovascular Diagnostic Measurement Acquisition Including an Enhanced Dynamically Configured Graphical Display - The present invention provides a multipurpose host system for processing and displaying invasive cardiovascular diagnostic measurement data. The system includes a an external input signal bus interface. The bus interface receives data arising from cardiovascular diagnostic measurement sensors. Measurement processing components receive data from particular sensor types. Based on the received data, the processing components render diagnostic measurement parameter values. A multi-mode graphical user interface includes display components corresponding to data received from particular sensor types. The user interface provides recommended action prompts that guide a user through a series of actions. | 12-29-2011 |
20120220836 | Multipurpose Host System for Invasive Cardiovascular Diagnostic Measurement Acquisition and Display - A multifunctional invasive cardiovascular diagnostic measurement host is disclosed that interfaces a variety of sensor devices, such as guide wire-mounted pressure sensors, flow sensors, temperature sensors, etc, and provides a multi-mode graphical user interface providing a plurality of displays in accordance with the various types of sensors and measurements rendered by the sensors. | 08-30-2012 |
20120220837 | Multipurpose Host System for Invasive Cardiovascular Diagnostic Measurement Acquisition and Display - A multifunctional invasive cardiovascular diagnostic measurement host is disclosed that interfaces a variety of sensor devices, such as guide wire-mounted pressure sensors, flow sensors, temperature sensors, etc, and provides a multi-mode graphical user interface providing a plurality of displays in accordance with the various types of sensors and measurements rendered by the sensors. | 08-30-2012 |
20130190633 | Interface Devices, Systems, and Methods for Use With Intravascular Pressure Monitoring Devices - Embodiments of the present disclosure are configured to assess the severity of a blockage in a vessel and, in particular, a stenosis in a blood vessel. In some particular embodiments, the devices, systems, and methods of the present disclosure are configured to provide FFR measurements in a small, compact device that integrates with existing proximal and distal pressure measurement systems and does not require a separate power source. | 07-25-2013 |
20140121475 | Multipurpose Host System for Invasive Cardiovascular Diagnostic Measurement Acquisition and Display - A multifunctional invasive cardiovascular diagnostic measurement host is disclosed that interfaces a variety of sensor devices, such as guide wire-mounted pressure sensors, flow sensors, temperature sensors, etc, and provides a multi-mode graphical user interface providing a plurality of displays in accordance with the various types of sensors and measurements rendered by the sensors. | 05-01-2014 |
20140135633 | Devices, Systems, and Methods for Assessing a Vessel - Embodiments of the present disclosure are configured to assess the severity of a blockage in a vessel and, in particular, a stenosis in a blood vessel. In some particular embodiments, the devices, systems, and methods of the present disclosure are configured to assess the severity of a stenosis in the coronary arteries without the administration of a hyperemic agent. Further, in some implementations devices, systems, and methods of the present disclosure are configured to normalize and/or temporally align pressure measurements from two different pressure sensing instruments. Further still, in some instances devices, systems, and methods of the present disclosure are configured to exclude outlier cardiac cycles from calculations utilized to evaluate a vessel, including providing visual indication to a user that the cardiac cycles have been excluded. | 05-15-2014 |
20140180140 | Wireless Interface Devices, Systems, And Methods For Use With Intravascular Pressure Monitoring Devices - Embodiments of the present disclosure are configured to assess the severity of a blockage in a vessel and, in particular, a stenosis in a blood vessel. In some particular embodiments, the devices, systems, and methods of the present disclosure are configured to collect and wirelessly distribute reliable pressure signals to other devices, and do so in a small, compact device that integrates with existing proximal and distal pressure measurement systems and does not require a separate power source. | 06-26-2014 |
Patent application number | Description | Published |
20100145311 | CATHETER SHAFT WITH IMPROVED MANIFOLD BOND - A catheter shaft with an improved manifold bond and methods for making and using the same. The catheter shaft may include a sleeve disposed, for example, near its proximal end. The sleeve may include a first layer that is attached to the catheter shaft and a second layer to which a hub or manifold may be attached. | 06-10-2010 |
20110172643 | Catheter with Composite Stiffener - A catheter comprising an elongate tubular member having a proximal end, a distal end, and a passageway defining a lumen extending between the proximal and distal ends. The elongate tubular member comprises a relatively stiff proximal section and a relatively flexible distal section. The proximal section includes an inner tubular liner, a first stiffener comprising a metal alloy, and a second stiffener comprising a non-metal alloy. The first and second stiffeners are coaxially wound exterior to the proximal inner liner. The distal section includes a distal inner tubular liner and the second stiffener coaxially wound exterior to the distal inner liner. The first stiffener terminates before reaching the distal section. | 07-14-2011 |
20120323189 | CATHETER SHAFT WITH IMPROVED MANIFOLD BOND - A catheter shaft with an improved manifold bond and methods for making and using the same. The catheter shaft may include a sleeve disposed, for example, near its proximal end. The sleeve may include a first layer that is attached to the catheter shaft and a second layer to which a hub or manifold may be attached. | 12-20-2012 |
20130072905 | CATHETER WITH COMPOSITE STIFFENER - A catheter comprising an elongate tubular member having a proximal end, a distal end, and a passageway defining a lumen extending between the proximal and distal ends. The elongate tubular member comprises a relatively stiff proximal section and a relatively flexible distal section. The proximal section includes an inner tubular liner, a first stiffener comprising a metal alloy, and a second stiffener comprising a non-metal alloy. The first and second stiffeners are coaxially wound exterior to the proximal inner liner. The distal section includes a distal inner tubular liner and the second stiffener coaxially wound exterior to the distal inner liner. The first stiffener terminates before reaching the distal section. | 03-21-2013 |
Patent application number | Description | Published |
20100012163 | DISHWASHER AND METHOD - A personal dishwasher washes and dries a dish that is manually or mechanically moved through a dishwasher chamber or is manually placed in and manually removed from the chamber. Pressurized water, possibly containing soap, wetting agent, etc., may be added to the wash water. Steam may be used to for cleaning and/or disinfecting. Ultraviolet light may be used for disinfecting. The dishwasher chamber may be enlarged to pass larger dishes, bowls, glassware, etc. for washing. A method of washing dishes, comprising inserting a dish manually into a dishwasher, passing the dish through the dishwasher, and withdrawing the dish. A method of washing a dish, comprising inserting a single dish into a dishwasher, directing fluid under pressure at the dish, directing air flow at the dish, and withdrawing the dish. | 01-21-2010 |
20100244740 | MULTI-CHIP LIGHT EMITTING DIODE LIGHT DEVICE - An electric lamp includes a first light source and a second light source and power circuitry configured to selectively energize the first light source and the second light source. The first light source is configured to produce light that is substantially free of wavelengths below about 530 nanometers, and the second light source is configured to product light having wavelengths of less than about 530 nanometers. The electric lamp is configured to produce white or near-white light in a variety of color temperatures, while retaining good color rendering index. | 09-30-2010 |
20110042988 | APPARATUS AND METHOD FOR RADIANT HEATING AND COOLING FOR VEHICLES - The passenger compartment of a vehicle, e.g., an automobile or other automotive vehicle, train, aircraft or watercraft, is heated or cooled using radiant heating or radiant cooling. As another option the automobile or other vehicle is heated using a low velocity blower. | 02-24-2011 |
20130233355 | WASHING APPARATUS AND METHOD WITH SPIRAL AIR FLOW FOR DRYING - An apparatus and method for washing and drying objects includes a rotating washing fluid sprayer having several nozzles to direct washing fluid, e.g., water, at an object being washed in a chamber. A drying fluid is directed at the object in the chamber to dry the object. The drying fluid, e.g., air, is directed in a spiral pattern against the object to urge washing liquid away from the object to dry the object and to push the drying liquid away from edges of the object. The air may be directed at the object simultaneously with the water to increase the energy with which the water impinges on the object and to urge dirt from the object being washed. | 09-12-2013 |
Patent application number | Description | Published |
20140233842 | CHARACTERISTIC VERIFICATION SYSTEM - Described is a characteristic verification system that includes security marks, devices, systems and methods that may be used to authenticate a material good and to provide strong brand protection. A device, such as a smartphone, that includes a software application, a camera and a light source, may be used to interrogate the security mark and connect to remote servers to authenticate the material good at varying levels of assurance. In addition to authenticating the good, the system may also authenticate the user and provide different information to different users and/or limit information that is provided unauthenticated users. | 08-21-2014 |
20140263658 | SYSTEM AND METHOD FOR PROVIDING TANGIBLE MEDIUM WITH ELECTROMAGNETIC SECURITY MARKER - Mediums that include features that work together to create a medium that can be tracked, identified and authenticated efficiently and accurately. In addition, these features may be concealed to prevent or hinder potential copiers from copying or passing off a copy as an original. Further, these features may allow organizations to determine the origin of a copy. | 09-18-2014 |
20140270334 | COVERT MARKING SYSTEM BASED ON MULTIPLE LATENT CHARACTERISTICS - Described are systems for combining multiple latent characteristics within a pigment such that with certain specialized knowledge and tools the specific pigment can be uniquely authenticated. The system takes advantage of the rapid proliferation of artificial light sources that are characterized by combinations of narrow band light sources that combine to simulate natural, or broadband light sources. With knowledge of the ambient lighting spectral emissions and the ability to illuminate the subject with an alternative light source with different spectral emissions, it is possible to determine the presence of the latent characteristics within the pigment. In some embodiments of the system, a smartphone including a CMOS or CCD sensor and a LED light source, could be combined with software to authenticate all of the latent characteristics. These characteristics can be combined with each other in different proportions to mass customize unique solutions for each customer or product line. | 09-18-2014 |
20150089635 | SYSTEM FOR CORRELATION OF INDEPENDENT AUTHENTICATION MECHANISMS - Described are devices, methods and non-transitory computer readable media for implementing an enhanced multi-factor authentication system. The system uses three user identifiers, and after a first user identifier is verified, the system receives a second user identifier from the user. As the second user identifier is being received, the system automatically detects a third user identifier and verifies simultaneously the second and third user identifiers. The second and third user identifiers are correlated with each other, and the correlation of these two identifiers (e.g., in addition to the identifiers themselves) is also verified. | 03-26-2015 |
Patent application number | Description | Published |
20130086277 | SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR CREATING A VIDEO CLIP - The present invention provides a system, method, and computer readable medium for creating a video clip. In one embodiment, a method, comprising creating a copy of a still image by a first module, the copy of the still image comprising reduced dimensions of the still image, creating a new still image from a selected area of the still image, automatically ordering the new still image and the copy of the still image, creating an audio file by at least one of a second module and a third module, creating a timeline, by the first module, related to the ordered images and the created audio file, and rendering the timeline into a video clip by a fourth module, wherein the timeline includes a length of the audio file, a length of the video clip, the ordered images, a display time of each of the ordered images, transition identifiers, transition lengths. | 04-04-2013 |
20130091300 | SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR CREATING A VIDEO CLIP - A system, method, and computer readable medium for creating a video clip comprises receiving still image files by a first module, creating a copy of a still image from the still image files with reduced dimensions by the first module, creating a new still image from a selected area of the still image, storing the new still image and the copy of the still image with a unified file name, ordering the stored images, creating an audio file by at least one of a second module and a third module, creating a timeline, by the first module, related to the ordered images and the created audio, and rendering the timeline into the video clip by a fourth module. | 04-11-2013 |
20140201624 | SENTIMENTAL CARD SELECTION, CREATION AND PROCESSING APPLICATION - Certain embodiments of the present application allow a user to preview a plurality of cards on a portable computing device, select a card from the plurality of cards, and modify the selected card. One example method of operation may include accessing a customizable data input templates stored in memory, selecting one of the customizable data input templates, inputting data to incorporate into the selected customizable data input template and transmitting the data to the remote server to be saved. The changes may be presented to the user in a preview with the inputted data overlaid on the predefined area of the customizable data input template, the preview may permit an acceptance option to finalize or reject the customizable data input template. The finalized customizable data input template may be saved as an acceptance message is received. | 07-17-2014 |
Patent application number | Description | Published |
20110093608 | SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR CREATING A VIDEO CLIP - A system, method, and computer readable medium for creating a video clip comprises receiving still image files by a first module, creating a copy of a still image from the still image files with reduced dimensions by the first module, creating a new still image from a selected area of the still image, storing the new still image and the copy of the still image with a unified file name, ordering the stored images, creating an audio file by at least one of a second module and a third module, creating a timeline, by the first module, related to the ordered images and the created audio, and rendering the timeline into the video clip by a fourth module. | 04-21-2011 |
20110214045 | SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR CREATING A VIDEO CLIP - The present invention provides a system, method, and computer readable medium for creating a video clip. In one embodiment, a method, comprising creating a copy of a still image by a first module, the copy of the still image comprising reduced dimensions of the still image, creating a new still image from a selected area of the still image, automatically ordering the new still image and the copy of the still image, creating an audio file by at least one of a second module and a third module, creating a timeline, by the first module, related to the ordered images and the created audio file, and rendering the timeline into a video clip by a fourth module, wherein the timeline includes a length of the audio file, a length of the video clip, the ordered images, a display time of each of the ordered images, transition identifiers, transition lengths. The present invention further discloses a system for assembling and distributing multi-media output, comprising: a rendering server; a web server; and storage, wherein the servers and the storage are operably coupled; the storage adapted to receive digital media and properties of the media, store the media and the properties, and transmit the media and the properties; the web server adapted to perform at least one of a following action: retrieve the media and properties of the media; manipulate the media and the properties; assemble the properties; and transmit at least one of a following element from a group consisting of: the properties; and the assembled properties; and the rendering server adapted to receive commands from the web server. | 09-01-2011 |
20120254711 | SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR CREATING A VIDEO CLIP - The present invention provides a system, method, and computer readable medium for creating a video clip. In one embodiment, a method, comprising creating a copy of a still image by a first module, the copy of the still image comprising reduced dimensions of the still image, creating a new still image from a selected area of the still image, automatically ordering the new still image and the copy of the still image, creating an audio file by at least one of a second module and a third module, creating a timeline, by the first module, related to the ordered images and the created audio file, and rendering the timeline into a video clip by a fourth module, wherein the timeline includes a length of the audio file, a length of the video clip, the ordered images, a display time of each of the ordered images, transition identifiers, transition lengths. | 10-04-2012 |