Patent application number | Description | Published |
20090050716 | High-pressure spray gun - The invention relates to a high-pressure spray gun for a high-pressure cleaning appliance, comprising a housing having arranged therein a valve with an inlet channel and an outlet channel and a closing body, which is adapted to rest in a sealing manner on a sealing surface arranged between the inlet channel and the outlet channel, and which interacts with a hand lever, an insert nipple being insertable into the inlet channel and fixable in an axially immovable manner for connection of a liquid supply line. To further develop the high-pressure spray gun in such a way that a liquid supply line can be connected to and separated from the valve in a simple way, it is proposed in accordance with the invention that the high-pressure spray gun comprise an immovable securing clip with two securing parts, which are insertable into diametrically opposed lateral openings of the inlet channel in order to engage behind the insert nipple, and which are spreadable apart in a spring-elastic manner by an actuating element which is displaceably arranged in the housing. | 02-26-2009 |
20130019911 | SURFACE CLEANING HEAD - A surface cleaning head is provided comprising a dome-shaped, downwardly open housing, in which at least one spray arm is mounted for rotation about an axis of rotation, wherein the spray arm bears at a distance from the axis of rotation a nozzle which can be acted upon with cleaning fluid subject to pressure and revolves around the axis of rotation together with the spray arm, and comprising a protective disk which covers the at least one spray arm towards the open underside of the housing and defines a ring-shaped fluid passage for a stream of fluid to pass through, said fluid passage being penetrated by retaining bars, wherein the at least one spray arm is rotatable relative to the protective disk. The retaining bars are arranged so as to be distributed unevenly in circumferential direction. | 01-24-2013 |
Patent application number | Description | Published |
20130028502 | SYSTEMS AND METHODS FOR MOBILE IMAGE CAPTURE AND PROCESSING OF CHECKS - Techniques for processing an image of a check captured using a mobile device are provided. The check image is processed to determine whether the check can be deposited at a bank via a mobile deposit process. The system can identify regions of the check—such as the endorsement area—to determine if the check has been properly endorsed. The system can be implemented on a mobile device and/or a server, where the mobile device routes the check image to the server for processing. If the check cannot be deposited, a rejection is forwarded in real time to the mobile device for possible correction. | 01-31-2013 |
20130287284 | SYSTEMS AND METHODS FOR CLASSIFYING PAYMENT DOCUMENTS DURING MOBILE IMAGE PROCESSING - Systems and methods are provided for processing an image of a financial payment document captured using a mobile device and classifying the type of payment document in order to extract the content therein. These methods may be implemented on a mobile device or a central server, and can be used to identify content on the payment document and determine whether the payment document is ready to be processed by a business or financial institution. The system can identify the type of payment document by identifying features on the payment document and performing a series of steps to determine probabilities that the payment document belongs to a specific document type. The identification steps are arranged starting with the fastest step in order to attempt to quickly determine the payment document type without requiring lengthy, extensive analysis. | 10-31-2013 |
20130294697 | SYSTEMS AND METHODS FOR PROCESSING MOBILE IMAGES TO IDENTIFY AND EXTRACT CONTENT FROM FORMS - Systems and methods for matching a received image with a template image are disclosed herein. Such systems and methods can advantageously enable an image captured by a mobile device (such as a smartphone or digital camera) to be correctly identified by the processing application. In some embodiments, the received image is first resized in one or both dimensions in order to match or approximately match the dimensions of a given template. The received image and template image can then be superimposed. Next, an optimal translative transformation value can be calculated in order to generate a confidence level for the current possible match. After confidence levels for each template are generated and recorded, the template with the highest confidence level can be selected as the best match for the received image. | 11-07-2013 |
20140247998 | SYSTEMS AND METHODS FOR PROCESSING MOBILE IMAGES TO IDENTIFY AND EXTRACT CONTENT FROM FORMS - Systems and methods for matching a received image with a template image are disclosed herein. Such systems and methods can advantageously enable an image captured by a mobile device (such as a smartphone or digital camera) to be correctly identified by the processing application. In some embodiments, the received image is first resized in one or both dimensions in order to match or approximately match the dimensions of a given template. The received image and template image can then be superimposed. Next, an optimal translative transformation value can be calculated in order to generate a confidence level for the current possible match. After confidence levels for each template are generated and recorded, the template with the highest confidence level can be selected as the best match for the received image. | 09-04-2014 |
20140279323 | SYSTEMS AND METHODS FOR CAPTURING CRITICAL FIELDS FROM A MOBILE IMAGE OF A CREDIT CARD BILL - The embodiments herein focus on improving recognition accuracy of these fields on credit card bills by detecting and identifying critical fields on a credit card, extracting the data from the critical fields and comparing the data with known data on a payor, payee and biller. | 09-18-2014 |
Patent application number | Description | Published |
20140031260 | Molecular Diagnostic Test for Cancer - Methods and compositions are provided for the identification of a molecular diagnostic test for cancer. The test defines a novel DNA damage repair deficient molecular subtype and enables classification of a patient within this subtype. The present invention can be used to determine whether patients with cancer are clinically responsive or non-responsive to a therapeutic regimen prior to administration of any chemotherapy. This test may be used in different cancer types and with different drugs that directly or indirectly affect DNA damage or repair, such as many of the standard cytotoxic chemotherapeutic drugs currently in use. In particular, the present invention is directed to the use of certain combinations of predictive markers, wherein the expression of the predictive markers correlates with responsiveness or non-responsiveness to a therapeutic regimen. | 01-30-2014 |
20140051591 | MOLECULAR DIAGNOSTIC TEST FOR CANCER - Methods and compositions are provided for the identification of a molecular diagnostic test for cancer. The test defines a novel DNA damage repair deficient molecular subtype and enables classification of a patient within this subtype. The present invention can be used to determine whether patients with cancer are clinically responsive or non-responsive to a therapeutic regimen prior to administration of any chemotherapy. This test may be used in different cancer types and with different drugs that directly or indirectly affect DNA damage or repair, such as many of the standard cytotoxic chemotherapeutic drugs currently in use. In particular, the present invention is directed to the use of certain combinations of predictive markers, wherein the expression of the predictive markers correlates with responsiveness or non-responsiveness to a therapeutic regimen. | 02-20-2014 |
20140094379 | Colon Cancer Gene Expression Signatures and Methods of Use - A gene expression signature of colon cancer, microarrays including them and methods of using the colon gene expression signature are provided. The gene expression signature is especially useful for determining the prognosis of a patient diagnosed with colon cancer, such as stage II colon cancer. The gene signature described herein is also useful for determining effectiveness of surgical resection with or without adjuvant chemotherapy, and determining possibility of cancer recurrence in patients with colon cancer. | 04-03-2014 |
20160060705 | MOLECULAR DIAGNOSTIC TEST FOR CANCER - Methods and compositions are provided for the identification of a molecular diagnostic test for cancer. The test defines a novel DNA damage repair deficient molecular subtype and enables classification of a patient within this subtype. The present invention can be used to determine whether patients with cancer are clinically responsive or non-responsive to a therapeutic regimen prior to administration of any chemotherapy. This test may be used in different cancer types and with different drugs that directly or indirectly affect DNA damage or repair, such as many of the standard cytotoxic chemotherapeutic drugs currently in use. In particular, the present invention is directed to the use of certain combinations of predictive markers, wherein the expression of the predictive markers correlates with responsiveness or non-responsiveness to a therapeutic regimen. | 03-03-2016 |
Patent application number | Description | Published |
20130182477 | Method for Stabilizing an Electric Grid - A method for grid support by means of an inverter is disclosed, wherein the grid is supported by feeding in compensation currents. The method includes measuring a prevailing grid state, and breaking down voltages measured for measuring the prevailing grid state into symmetrical components of the grid state including positive sequence system components and negative sequence system components. The method further includes determining symmetrical components of a compensation current including positive sequence system components and negative sequence system components of the compensation current as functions of deviations of the positive sequence system components and negative sequence system components of the grid state from reference values, and feeding-in a compensation current as the vector sum of the determined symmetrical components of the compensation current | 07-18-2013 |
20150115722 | Control of a Plurality of Inverters Connected to a Common Grid Connection Point - In order to control a plurality of inverters, which are connected on their input side to a current source each and on their output side to a common grid connection point, electrical variables are measured at the individual inverters and are used for controlling the individual inverters, currents being output by the individual inverters depending on the electrical variables measured at the location of the individual inverters Effects of the connection equipment between the individual inverters and the common grid connection point on currents are determined, electrical variables being measured at the grid connection point and are set in relation to the electrical variables measured at the same time at the individual inverters. The connection equipment between the individual inverters and the common grid connection point is taken into consideration in controlling the individual inverters. | 04-30-2015 |
20160006366 | INVERTER AND OPERATING METHOD FOR AN INVERTER - A method for operating an inverter which is connected to an energy supply grid via a transformer for feeding in electrical energy into the energy supply grid, includes measuring output currents and output voltages of the inverter, and actuating power switches of the inverter using actuation signals that are generated as a function of the measured output currents and the measured output voltages at a fundamental frequency of the energy supply grid. The actuation signals are further generated as a function of a harmonic component of the measured output voltages of the inverter at a multiple of the fundamental frequency using a control loop with positive feedback. | 01-07-2016 |
Patent application number | Description | Published |
20100129002 | Adaptive configuration of windows-of-interest for accurate and robust focusing in multispot autofocus cameras - In accordance with the exemplary embodiments of the invention there is at least a method, executable computer program, and apparatus to provide operations including logically separating into a plurality of parts at least one sub-window of interest of a plurality of sub-windows of interest arranged in a grid formation in an autofocus window of interest, assigning a focus value mask to each of the plurality of parts of the at least one sub-window, and executing an autofocus algorithm using the assigned focus value masks. | 05-27-2010 |
20110286199 | Apparatus For An Electronic Device - An apparatus for an electronic device, the apparatus comprising a light-output region and a movable part, the movable part comprising an optical element and being movable between an open configuration and a closed configuration with respect to the light-output region; wherein the apparatus is arranged such that, in the closed configuration, the optical element at least partially overlies the light-output region and, in the open configuration, the optical element overlies the light-output region to a lesser extent than in the closed configuration, and wherein the optical element is arranged to alter a pattern of light emitted from the light-output region such that the light is emitted in a first light output pattern in the open configuration and in a second light output pattern in the closed configuration. | 11-24-2011 |
20150365584 | RELIABILITY MEASUREMENTS FOR PHASE BASED AUTOFOCUS - Techniques related to autofocus for imaging devices and, in particular, to generating reliability values associated with phase autofocus shifts are discussed. Such techniques may include performing a curve fitting based on accumulated phase difference values and phase shifts for phase autofocus images and generating a reliability value for a focus phase shift based on the curve fitting. | 12-17-2015 |
Patent application number | Description | Published |
20130013246 | METHOD AND APPARATUS FOR POST-SILICON TESTING - An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection. | 01-10-2013 |
20140032966 | Hardware verification using ACCELERATION platform - A method, apparatus and product for hardware verification using acceleration platform. The method comprising executing a first post-silicon testing program by a reference model, wherein during said executing the first post-silicon testing program one or more test-cases are generated; generating a second post-silicon testing program that is configured to execute the one or more test-cases; and executing the second post-silicon testing program on an acceleration platform. | 01-30-2014 |
20150186250 | ARCHITECTURAL FAILURE ANALYSIS - Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow. | 07-02-2015 |
20150186251 | CONTROL FLOW ERROR LOCALIZATION - Localizing errors by: (i) running a testcase on a hardware processor and saving results; (ii) running the testcase on a software model of the processor and saving results; (iii) recording control flow information during the software run; (iv) determining a set of miscompare data storage locations by comparing the results from the hardware run with those from the software run; (v) based on the set of miscompare data storage locations and/or the control flow information, generating and running a modified version of the testcase that takes a different execution path when run on the software model than did the original testcase when run on the software model; and (vii) comparing the results from the hardware run and the results obtained from the modified software run to provide an indication of similarity between execution paths taken in these respective runs. | 07-02-2015 |
Patent application number | Description | Published |
20100225628 | LIGHT SENSOR ARRANGEMENT - Ambient light is sensed for use in determining luminous flux. According to an example embodiment, ambient light is sensed using two light sensor arrangements that respectively respond differently to light of different relative wavelengths. The output of the sensors is nonlinearly combined to generate data indicative of the luminous flux. This luminous flux data is used to generate a control output for controlling an electronic display. | 09-09-2010 |
20100283998 | LIGHT SENSOR WITH INTENSITY AND DIRECTION DETECTION - A light sensor and light sensing system to detect an intensity of incident light and an angle of incidence of the incident light. The light sensor includes a dielectric layer, a plurality of photo detectors coupled relative to the dielectric layer, and a plurality of stacks of opaque slats embedded within the dielectric layer. The dielectric layer is substantially transparent to the incident light. The photo detectors detect the incident light through the dielectric layer. The stacks of opaque slats are approximately parallel to an interface between the dielectric layer and the photo detectors. The stacks of opaque slats define light apertures between adjacent stacks of opaque slats. At least some of the stacks of opaque slats are arranged at a non-zero angle relative to other stacks of the opaque slats. | 11-11-2010 |
20100302201 | Sensor Patterns for Mutual Capacitance Touchscreens - According to one embodiment, there is provided a mutual capacitance touchscreen comprising a first set of electrically conductive traces arranged in rows or columns and a second set of electrically conductive traces arranged in rows or columns arranged at right angles with respect to the rows or columns of the first set, where the first and second sets of traces are electrically insulated from and interdigitated respecting one another, and gaps between the first and second sets of traces form boundaries between the first and second sets of traces that undulate and that are not straight or linear. Other embodiments of a mutual capacitance touchscreen are also disclosed, such as “mini-diamond” sensor array patterns and sensor array patterns that may be manufactured at low cost. | 12-02-2010 |
20100309703 | COMPACT AND ACCURATE ANALOG MEMORY FOR CMOS IMAGING PIXEL DETECTORS - The present invention relates to an analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor ( | 12-09-2010 |
20110298744 | Capacitive Touchscreen System with Multiplexers - Disclosed herein are various embodiments of a capacitive touchscreen system that is capable of sensing simultaneous or near-simultaneous multiple finger touches made on a capacitive touchscreen. In one embodiment, drive and sense circuits operably connected to X and Y lines of the touchscreen may be interchangeably and selectably configured to drive and sense X and Y lines of the touchscreen, respectively, or drive and sense Y and X lines, respectively, of the touchscreen, through first and second multiplexers operating under the control of a drive/sense processor. | 12-08-2011 |
20110298745 | Capacitive Touchscreen System with Drive-Sense Circuits - Disclosed herein are various embodiments of a capacitive touchscreen system that is capable of sensing, simultaneous or near-simultaneous multiple finger touches made on a capacitive touchscreen. In one embodiment, drive-sense circuits operably connected to X and Y lines of the touchscreen may be interchangeably and selectably configured as either sense circuits or drive circuits by a drive/sense processor operably connected thereto. | 12-08-2011 |
20110310051 | Reduction of Electromagnetic Interference in a Capacitive Touchscreen System - Disclosed herein are various embodiments of circuits and methods for reducing electromagnetic interference in mutual capacitance measurement or sensing systems, devices, components and methods such as capacitive touchscreens. Charge integrator circuits and switched capacitance filtering circuits are disclosed that improve the signal-to-noise ratio (or the ratio of a desired sensed mutual capacitance signal to an undesired EMI signal) in a capacitive sensor readout circuit without the need to increase the amplitude of the drive signal. The various embodiments of the charge integrator and switched capacitance filtering circuits described herein permit an improvement in noise immunity without requiring the excessive power levels typically associated with high amplitude drive circuitry, and moreover result in boosting signal-to-noise ratios during early stages of signal processing. | 12-22-2011 |
20110310052 | Capacitive Touchscreen System with Switchable Charge Acquisition Circuit - Disclosed herein are various embodiments of a capacitive touchscreen system which includes switchable charge acquisition circuits and corresponding charge integrator circuits for sensing mutual capacitances associated with a touchscreen. Various embodiments of the switchable charge acquisition circuits and corresponding charge integrator circuits provide lower power consumption, increased operational stability, substantially reduced integrated circuit area, and increased temperature stability. | 12-22-2011 |
20110310054 | Capacitive Touchscreen Signal Acquisition without Panel Reset - Various embodiments of readout circuits are disclosed where no touchscreen or touch panel recharge is required, and the amount of time available for signal acquisition is twice that relative to prior art touchscreen or touch panel readout circuits. Voltage offsets of the integrating amplifiers may be compensated for by notch filtering signals stored in readout circuit capacitors. Some embodiments of readout circuits disclosed herein permit large dynamic range capacitive touchscreen or touch panel signals to be processed, and do not require panel reset. Readout circuits are disclosed that permit doubling of the signal acquisition rate and pre-filtering of acquired touch panel signals for improved immunity from harmonic EMI. Signal acquisition and temporary storage may be carried out using the same capacitors in such readout circuits. | 12-22-2011 |
20120104228 | PIXEL CIRCUIT, IMAGING INTEGRATED CIRCUIT, AND METHOD FOR IMAGE INFORMATION ACQUISITION - A pixel circuit uses two storage transistors to store two image signal samples, which include a reference signal produced by background noise of the pixel circuit and a signal produced by optical exposure of a photodetector and the background noise of the pixel circuit. An imaging integrated circuit uses a pixel circuit array, which may contain a number of such pixel circuits, and a charge acquisition circuit configured to read out image information obtained by the pixel circuit array. The charge acquisition circuit uses a first amplifier and a serially connected differential integrator that includes a second amplifier, a first differential integrator section and a second differential integrator section for the read out. A method for image information acquisition involves obtaining image information using the pixel circuit array and reading out the image information obtained by the pixel circuit array using the charge acquisition circuit. | 05-03-2012 |
20120105355 | Capacitive Touchscreen System with Touch Position Encoding during Analog-to-Digital Conversion - Disclosed herein are various embodiments of circuits and methods in a capacitive touchscreen system that eliminate the need to digitize an entire array of pixel signals obtained from a touchscreen. Instead, regions of interest, or projections of object or touch signal clusters, from touchscreen | 05-03-2012 |
20120306801 | Charge Pump Frequency Selection in Touch Screen Sensor Interface System - Various embodiments of charge pump circuitry configured to generate output signals having first distortion signals superimposed thereon are disclosed. Demodulator input signals are also disclosed that have second distortion signals superimposed thereon. A synchronization signal is delivered to demodulator circuitry through at least first and second integer divider circuits and to charge pump circuitry through at least the first integer divider circuitry such that the first and second distortion signals have frequencies that are integer divisions of the synchronization frequency. | 12-06-2012 |
20130016061 | Low Voltage Capacitive Touchscreen Charge Acquisition and Readout Systems, Circuits and Methods for High System Noise ImmunityAANM Souchkov; VitaliAACI Walnut CreekAAST CAAACO USAAGP Souchkov; Vitali Walnut Creek CA US - Various embodiments of capacitive touchscreen driving and sensing circuits are disclosed, where during a first phase the mutual capacitance between a given drive electrode and a given sense electrode is charged up to a first charge value corresponding substantially to a drive voltage times the mutual capacitance. During a second phase the charge storage capacitor is charged up to a value corresponding approximately to a difference in touchscreen capacitance network charges occurring during the first and second phases. The first and second phases do not overlap in time. Dark frame signals may also be acquired from the touchscreen to calibrate differences in touchscreen capacitance network charges. | 01-17-2013 |
20130038477 | Capacitor Mismatch Error Correction in Pipeline Analog-to-Digital Converters - Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed. A plurality of pipeline element circuits are provided, where each pipeline element circuit corresponds to a given bit of the pipeline ADC. A first pipeline element circuit is configured to digitize analog A and B capacitor mismatch error calibration voltages generated by all the pipeline element circuits of the ADC when the pipeline ADC is operating in a capacitor mismatch calibration phase. According to one embodiment, digital representations corresponding to A and B capacitor mismatch error calibration voltages for each of the pipeline element circuits are provided to an output shift register and summing circuit, which generates capacitor mismatch error correction codes corresponding to each bit and pipeline element circuit. The capacitor mismatch error correction codes are applied to each bit weight of the pipeline ADC after conversion of analog signals input to the pipeline ADC has been completed. | 02-14-2013 |
20130038478 | Systems, Devices and Methods for Capacitor Mismatch Error Averaging in Pipeline Analog-to-Digital Converters - Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed, where in a pipeline element circuit and during a first phase, an input voltage provided by a sample-and-hold circuit is presented to first and second capacitors arranged in parallel in the pipeline element circuit. During a second phase, a second voltage corresponding to a second charge associated with the second capacitance is amplified and stored in the pipeline element circuit. During a third phase, the same input voltage of the first phase is again presented to the first and second capacitors, which are arranged in parallel in the pipeline element circuit. During a fourth phase a first voltage corresponding to the first charge is amplified and stored in the pipeline element circuit. After the first, second, third and fourth phases have been completed, digital representations of the first and second voltages are sent though corresponding registers for subsequent averaging along with digital representations of first and second voltages provided by other pipeline element circuits to produce a digital capacitor mismatch error corrected output. | 02-14-2013 |
Patent application number | Description | Published |
20080257256 | BULK GaN AND AlGaN SINGLE CRYSTALS - Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity. | 10-23-2008 |
20090130781 | METHOD FOR SIMULTANEOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY - HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or multi-level substrate holder. The gas delivery blocks are independently controllable. Gas flows from the delivery blocks are mixed to provide a substantially uniform gas environment within the growth zone. The substrate holder can be controlled, e.g., rotated and/or tilted, for uniform material growth. Multiple Group III nitride semiconductor structures can be grown on each substrate during a single fabrication run of the HVPE reactor. Growth on different substrates is substantially uniform and can be performed on larger area substrates, such as 3-12″ substrates. | 05-21-2009 |
20090148984 | BULK GaN AND AlGaN SINGLE CRYSTALS - Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity. | 06-11-2009 |
20090286331 | METHOD FOR SIMULATENOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY - HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or multi-level substrate holder. The gas delivery blocks are independently controllable. Gas flows from the delivery blocks are mixed to provide a substantially uniform gas environment within the growth zone. The substrate holder can be controlled, e.g., rotated and/or tilted, for uniform material growth. Multiple Group III nitride semiconductor structures can be grown on each substrate during a single fabrication run of the HVPE reactor. Growth on different substrates is substantially uniform and can be performed on larger area substrates, such as 3-12″ substrates. | 11-19-2009 |
20110108954 | Growth of Planar Non-Polar M-Plane Gallium Nitride With Hydride Vapor Phase Epitaxy (HVPE) - A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE. Various alternative methods are disclosed. | 05-12-2011 |
20140353685 | Semi-Polar III-Nitride Films and Materials and Method for Making the Same - A method has been developed to overcome deficiencies in the prior art in the properties and fabrication of semi-polar group III-nitride templates, films, and materials. A novel variant of hydride vapor phase epitaxy has been developed that provides for controlled growth of nanometer-scale periodic structures. The growth method has been utilized to grow multi-period stacks of alternating AlGaN layers of distinct compositions. The application of such periodic structures to semi-polar III-nitrides yielded superior structural and morphological properties of the material, including reduced threading dislocation density and surface roughness at the free surface of the as-grown material. Such enhancements enable to fabrication of superior quality semi-polar III-nitride electronic and optoelectronic devices, including but not limited to transistors, light emitting diodes, and laser diodes. | 12-04-2014 |
Patent application number | Description | Published |
20110178915 | Trading Order Validation System and Method and High-Performance Trading Data Interface - A post-trade monitor receives feedback in the form of drop copy messages from an exchange server and validates orders placed with the exchange server by a sponsored access trading platform shortly after the orders have been placed. If a recently placed order is found to violate a rule or regulation, the monitor instructs the trading platform to change to a more restrictive trading mode, such as to cease placing all orders or certain types of orders, at least until certain parameters are met. A library provides an interface in a sponsored access trading platform between a client application program that generates proposed orders and an exchange server. The library provides pre-trade validation of the orders and sends only validated orders to the exchange server. A network enables monitors, trading platforms and libraries to share information about customers' trading activities and locally recalculate customer trading limits resulting from these trading activities. A low-latency interface between a customer server, such as a server that employs algorithmic trading methods to generate buy and sell orders for securities, and a brokerage server that validates such securities trading orders is optimized for handling the securities trading orders. The interface supports a trading command set specifically designed for orders from customer trading application programs, and the interface formats received trading commands into compact messages that are sent over a high-speed communication link to the brokerage server. The interface receives order acknowledgement messages and the like from the brokerage server and invokes callback routines in the customer trading application program to report status information. | 07-21-2011 |
20110196778 | High Performance Trading Data Interface and Trading Data Distribution Protocol - A network enables monitors, trading platforms and libraries to share information about customers' trading activities and locally recalculate customer trading limits resulting from these trading activities. A low-latency interface between a customer server, such as a server that employs algorithmic trading methods to generate buy and sell orders for securities, and a brokerage server that validates such securities trading orders is optimized for handling the securities trading orders. The interface supports a trading command set specifically designed for orders from customer trading application programs, and the interface formats received trading commands into compact messages that are sent over a high-speed communication link to the brokerage server. The interface receives order acknowledgement messages and the like from the brokerage server and invokes callback routines in the customer trading application program to report status information. | 08-11-2011 |
20130216236 | MANAGED OPTICAL COMPUTER NETWORK DEVICE - A managed optical communication network device selectively passes or blocks an optical signal from an input port to an output port, based on state of the device. The device state may be managed remotely by sending management commands, according to a communication protocol, to the device. The device may be remotely controlled to selectively cut off all optical communications between two nodes, such as between two computers, between a local area network and a router, or between a router and a wide area network. | 08-22-2013 |
20140025558 | Trading Control System that Shares Customer Trading Activity Data Among Plural Servers - A network enables a plurality of servers to share information about customers' trading activities and locally recalculate customer trading limits resulting from these trading activities. If a trading limit is exceeded, a server may automatically change to a less permissive trading mode, prevent an order being placed with the at least one exchange server and/or enter a trading mode in which orders that decrease account exposure are allowed and orders that increase account exposure are prevented. | 01-23-2014 |
20140108228 | Trading Order Validation System and Method and High-Performance Trading Data Interface - A post-trade monitor receives feedback in the form of drop copy messages from an exchange server and validates orders placed with the exchange server by a sponsored access trading platform shortly after the orders have been placed. If a recently placed order is found to violate a rule or regulation, the monitor instructs the trading platform to change to a more restrictive trading mode, such as to cease placing all orders or certain types of orders, at least until certain parameters are met. | 04-17-2014 |
Patent application number | Description | Published |
20090141717 | DYNAMIC BUILDING OF VLAN INTERFACES BASED ON SUBSCRIBER INFORMATION STRINGS - Techniques are described that allow a network device, such as a router, to dynamically build VLAN interfaces based on subscriber information strings included within packets. In particular, the network device comprises an interface controller and a forwarding controller, where the forwarding controller receives the packet over an Ethernet port and forwards the received packet to the interface controller. The packet includes both Ethernet tagging information and a subscriber information string. The interface controller comprises an Ethernet module that dynamically builds a primary virtual local area network (VLAN) sub-interface (PVS) based on the Ethernet tagging information. The Ethernet module also dynamically builds a subscriber VLAN sub-interface (SVS) based on the subscriber information string. The SVS allows the network device to distinguish between subscribers residing on the same VLAN, and, therefore, to provide subscriber specific services. | 06-04-2009 |
20090210522 | Dynamic Host Configuration Protocol (DHCP) Initialization Responsive to a Loss of Network Layer Connectivity - Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with loss of network layer connectivity triggering Dynamic Host Configuration Protocol (DHCP) initialization. According to one embodiment, a network device connected to a network initializes one or more network communication values of the network device using DHCP. The network device monitors Network Layer (Layer 3) connectivity with a remote network device; and in response to detecting a loss of said monitored Network Layer connectivity, DHCP initialization of the network device is performed. | 08-20-2009 |
20100208588 | SHARED SHAPING OF NETWORK TRAFFIC - A method for sharing an aggregate bandwidth among a group of traffic classes may include allocating a portion of the aggregate bandwidth to one of the group of traffic classes having a first priority associated therewith, where the allocated portion is referred to as a first bandwidth. The method may include allocating an unused portion of the aggregate bandwidth to a second one of the group of traffic classes having a second priority associated therewith in conjunction with a parameter associated with a downstream device. | 08-19-2010 |
20110066735 | SYSTEMS AND METHODS FOR IP SESSION KEEPALIVE USING BFD PROTOCOLS - A network device may include logic to establish an IP session, establish a BFD session within the established IP session, transmit BFD packets within the established BFD session, and determine that the established IP session is active based upon reception of the BFD packets. In another embodiment, the logic may also determine that an IP session is active using an inactivity timer that may also trigger transmission of BFD packets. | 03-17-2011 |
20120290721 | SYSTEMS AND METHODS FOR IP SESSION KEEPALIVE USING BFD PROTOCOLS - A network device may include logic to establish an IP session, establish a BFD session within the established IP session, transmit BFD packets within the established BFD session, and determine that the established IP session is active based upon reception of the BFD packets. In another embodiment, the logic may also determine that an IP session is active using an inactivity timer that may also trigger transmission of BFD packets. | 11-15-2012 |