Patent application number | Description | Published |
20100255148 | METHOD OF MAKING BREAD - A method of making bread is provided. The method includes a warm dough making process in which a warm dough is formed by heating a mixture of milk and salt, adding wheat flour to the heated mixture, aerating the resulting mixture, and ripening the resulting mixture at low temperature, a dough mixing process in which a dough is formed by mixing the resulting dough of the warm dough making process with wheat flour, dried yeast, refined sugar, refined salt, whole milk powder, bread improver, processed butter, milk, egg, and water, and stirring the mixture, a deep-freezing process in which the resulting dough is divided into equal-sized pieces and the divided dough pieces are deep-frozen, a thawing process in which the deep-frozen dough is thawed, a fermentation process in which the thawed dough is placed in a bread pan to be fermented, and a baking process in which the fermented dough is heated. | 10-07-2010 |
20100255149 | METHOD OF MAKING BREAD - A method of making bread is provided. The method includes a warm dough making process in which a warm dough is formed by heating a mixture of milk and salt, adding wheat flour to the heated mixture, aerating the resulting mixture, and ripening the resulting mixture at low-temperature, a sponge making process in which a sponge is formed by mixing wheat flour, dried yeast, yeast food, bread improver, salt, and water and fermenting the mixture, a dough mixing process in which a dough is formed by mixing the warm dough and the sponge with wheat flour, salt, butter, dried yeast, dried milk, sugar, egg, and water and stirring the mixture, a division process in which the dough is divided into equal-sized pieces, a ripening process in which the divided dough is rolled out and ripened for a predetermined period of time, a molding process in which the resulting dough is molded to fit a bread pan, a fermentation process in which the molded dough is placed in the bread pan to be fermented, and a baking process in which the fermented dough is heated. | 10-07-2010 |
Patent application number | Description | Published |
20140267592 | METHOD FOR CAPTURING IMAGE AND ELECTRONIC DEVICE THEREOF - A method for processing an image using an electronic device is provided. The method includes displaying at least one first object and a first image associated with the at least one first object at a first position on a display unit connected to the electronic device, the at least one first object including information representing a direction of the electronic device, displaying at least one second object and a second image associated with the at least one second object at a second position on the display unit, and capturing at least a portion of the second image when the at least one first object is located within a distance from the at least one second object. | 09-18-2014 |
20140321446 | CONNECTION INFORMATION CONTROL METHOD AND ELECTRONIC DEVICE THEREFOR - A method and an apparatus for controlling connection information stored in an electronic device is provided. The method includes determining connection information, for at least one local-area wireless communication device, stored in the electronic device, selecting the connection information, for the at least one local-area wireless communication device, to be transmitted to a counterpart electronic device, and transmitting the connection information to the counterpart electronic device. | 10-30-2014 |
20140359751 | USER DEVICE AND OPERATING METHOD THEREOF - A security method in an electronic device is provided. The method includes pairing the electronic device with an Access Point (AP), obtaining at least one item of information about the AP, and setting a security level of the electronic device according to the at least one item of information. | 12-04-2014 |
20150301097 | ELECTRONIC DEVICE AND A METHOD FOR DETECTING A SHIELD STATE IN AN ELECTRONIC DEVICE - An electronic device and a method for determining a shield state in an electronic device are provided. The method includes at a detecting pad, detecting an electrical signal corresponding to a contact state of a shielding that contacts a ground or the detecting pad, and determining a shield state by the shielding based on the detected electrical signal. | 10-22-2015 |
20150356749 | METHOD OF UTILIZING IMAGE BASED ON LOCATION INFORMATION OF THE IMAGE IN ELECTRONIC DEVICE AND THE ELECTRONIC DEVICE THEREOF - An image utilizing method based on location information of an image is provided. The method includes displaying an image, setting a Region Of Interest (ROI) on the image, obtaining location information associated with the ROI, and storing the obtained location information together with an image of the ROI. The location information is stored together when the ROI is designated and thus, it is possible to provide various services based on the location information. | 12-10-2015 |
20160048664 | USER DEVICE AND OPERATING METHOD THEREOF - An apparatus and security method are provided. The apparatus includes at least one communication interface and a controller. The controller is configured to discover, using the at least one communication interface, an external electronic device available for a communication connection with the apparatus, the discovering including receiving information from the external electronic device, adjust a security level for the apparatus based at least in part on the information, and control at least part of the apparatus using the adjusted security level. | 02-18-2016 |
Patent application number | Description | Published |
20120170564 | FRAME FORMATION METHOD HAVING IMPROVED COMMUNICATION EFFICIENCY IN WIRELESS COMMUNICATION NETWORK FOR IN-BODY MEDICAL DEVICE - Disclosed herein is a method of forming communication frames. The communication frames each include a PHY header, a MAC header and a payload. The method includes forming the PHY header so that the PHY header includes information configured to support synchronization with a reception unit and information indicative of the start and overall size of the frame; forming the MAC header so that the MAC header includes information indicative of the type of frame, information configured to be used to check for the sequence of the frame and perform flow control, flag information, information indicative of the size of the data block, source and destination information, and information configured to be used to check the header of the frame for an error and correct the error; and forming the payload so that each of a plurality of data blocks includes information configured to perform error check and correction. | 07-05-2012 |
20120170589 | METHOD FOR PROVIDING SELECTIVE SERVICE BY SELECTIVE SERVICE MODULE AND HOME GATEWAY USING THE SAME - A selective service providing method using a selective service module, and a home gateway using the same are provided. A home gateway includes a module port for mounting a service module which provides a particular service; a communication interface for receiving a function result of the service module mounted to the module port; a display interface connected with a display; and a processor for sending the function result received from the service module through the communication interface, to the display through the display interface. Thus, the user's intended service can be selectively provided using the selective service module. | 07-05-2012 |
20120173763 | METHOD FOR PROVIDING SERVICE EXECUTED IN VARIOUS SERVICE MODULES AND HOME GATEWAY USING THE SAME - A method for providing a service executed in various service modules, and a home gateway using the same are provided. The service providing method displays a function result of a service module mounted to a module port to which a variety of service modules are selectively mountable, in a display connected. Hence, various services executed in various service modules can be provided reasonably and effectively. | 07-05-2012 |
20120195327 | FRAME FORMATION METHOD IN WIRELESS COMMUNICATION NETWORK FOR MEDICAL PROSTHETIC DEVICE - Disclosed herein is a method of forming communication frames. The communication frames each include a PHY header, a MAC header and a payload. The method includes forming the PHY header so that the PHY header includes information configured to support synchronization with a reception unit and information indicative of the start and overall size of the frame; forming the MAC header so that the MAC header includes information indicative of the type of frame, information configured to be used to check for the sequence of the frame, flag information, information indicative of the size of the data block, source and destination information, and information configured to be used to check the header of the frame for an error and correct the error; and forming the payload so that each of a plurality of data blocks includes information configured to perform error check and correction. | 08-02-2012 |
20130225116 | METHOD FOR NOTIFYING EMERGENCY BY MOBILE DEVICE AND HEALTH CARE MODULE AND HEALTH CARE SYSTEM USING THE SAME - A method for notifying an emergency and a health care system using the same are provided. The method includes receiving, at a mobile device, user health information from a module mounted to the mobile device; storing, at the mobile device, the received user health information; and when receiving an emergency signal from the mounted module, sending, at the mobile device, user location information and the stored user health information. Since the present invention can be implemented using a user's mobile device and a small module of low price, the user can avoid the financial burden and does not have to carry along a separate health care device. | 08-29-2013 |
Patent application number | Description | Published |
20100033418 | LIQUID CRYSTAL DISPLAY - The present invention provides a liquid crystal display (LCD). The LCD includes: a liquid crystal panel that includes a plurality of gate lines; and a gate driver that includes a plurality of stages, which are connected to the gate lines, respectively, and sequentially provide a plurality of gate signals to the gate lines, respectively, and a first dummy stage and a second dummy stage that are separated from each other, wherein the first dummy stage is enabled by a carry signal of one of the stages, and the second dummy stage is enabled by a carry signal of the first dummy stage and initializes each of the stages. | 02-11-2010 |
20100148176 | THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present invention relates to a thin film transistor array panel that includes an organic layer formed on a data line and a drain electrode disposed on a color filter. A thickness of a portion of the organic layer around a contact hole exposing a portion of the drain electrode is similar to a thickness of a portion of the organic layer around a contact hole exposing a portion of the data line. Having approximately the same thickness can prevent non-uniform etching of the organic layer around contact holes and deterioration of the thin film transistor array panel. | 06-17-2010 |
20100157186 | LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME - A liquid crystal display includes a first substrate and a second substrate facing the first substrate, a gate line and a data line disposed on the first substrate, and a pixel electrode disposed on the first substrate. The pixel electrode is connected to the gate line and the data line, and includes subregions. The liquid crystal display further includes a storage electrode disposed on the first substrate overlapping the pixel electrode to form a storage capacitor, a common electrode disposed on the second substrate, and a liquid crystal layer interposed between the pixel electrode and the common electrode and including liquid crystal molecules disposed therein. The pixel electrode includes a stem defining boundaries between the subregions, and a width of the stem changes from a center portion of the pixel electrode to a peripheral portion of the pixel electrode. | 06-24-2010 |
20100195026 | DISPLAY PANEL, THIN FILM TRANSISTOR ARRAY PANEL, AND METHOD FOR REPAIRING DISPLAY PANEL - An exemplary embodiment of the present invention relates to a display panel having a plurality of pixels, the display panel including a first substrate, and a color filter including a plurality of first color filters disposed on the first substrate and a second color filter having a black color and disposed in the same layer as the first color filters. | 08-05-2010 |
20110216261 | METHOD OF MANUFACTURING A LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL DISPLAY THEREOF - A liquid crystal display (“LCD”) includes a first insulation substrate, a thin film transistor (“TFT”) disposed on the first insulation substrate, and a pixel electrode disposed on the first insulation substrate and connected to a drain electrode of the TFT, wherein the pixel electrode includes an edge connection and a drain electrode connection, a portion of the edge connection pattern near a position where the drain electrode connection and the edge connection intersect is removed in the LCD, the pixel electrode further includes a stem and a plurality of minute branches, and a laser is irradiated to one intersection point between the stem and the minute branches among the stem near the light blocking layer to cut the portion of the pixel electrode. | 09-08-2011 |
Patent application number | Description | Published |
20130127459 | MAGNETIC RESONANCE IMAGING METHOD AND APPARATUS - A magnetic resonance imaging (MRI) method includes applying a radio-frequency (RF) pulse to a subject including different tissues all including a same type of atomic nuclei to rotate magnetization directions of the atomic nuclei of the different tissues; applying an RF pulse sequence to the subject based on the magnetization directions of the atomic nuclei of the different tissues; and obtaining magnetic resonance signals from the different tissues in response to the RF pulse sequence. | 05-23-2013 |
20140066746 | METHOD AND APPARATUS FOR CAPTURING MAGNETIC RESONANCE IMAGE - A method and apparatus for capturing a magnetic resonance image in which processes of generating T1 contrast for different regions of an object overlap with each other, thereby obtaining a magnetic resonance image having an improved contrast between different tissues within a short time. Therefore, a time required for obtaining a magnetic resonance image may be reduced, and a magnetic resonance image enabling improved diagnosis of a disease or other abnormal condition may be provided. | 03-06-2014 |
20140097839 | MAGNETIC RESONANCE IMAGE (MRI) APPARATUS AND METHOD FOR OBTAINING MRI IMAGE BY MODIFYING MOTION OF SUBJECT - Provided are a method and apparatus for obtaining a magnetic resonance imaging (MRI) image of a subject. Typically, MRI image processing that incorporates fat suppression takes a large amount of time to complete. According to various aspects, image processing that incorporates fat suppression may be postponed until MRI data is repeatedly obtained. By doing so, for example, more MRI data may be obtained during a time period of a heartbeat. | 04-10-2014 |
20140111201 | MAGNETIC RESONANCE IMAGING SYSTEM AND MAGNETIC RESONANCE IMAGING METHOD - A method of magnetic resonance imaging (MRI) includes applying radio frequency (RF) pulses including a plurality of frequency components and a selection gradient to a target to simultaneously excite a plurality of sub-volumes included in each of a plurality of groups, wherein neighboring sub-volumes of all sub-volumes constituting a volume of the target belong to different groups; acquiring magnetic resonance signals from the plurality of sub-volumes by performing 3D encoding on each of the excited sub-volumes; and reconstructing the acquired magnetic resonance signals into image data corresponding to each of the plurality of sub-volumes. | 04-24-2014 |
20140152305 | MAGNETIC RESONANCE IMAGING METHOD AND APPARATUS - A magnetic resonance imaging (MRI) method and apparatus are provided including a signal acquirer, a resonance frequency acquirer, and an RF driver. The signal acquirer is configured to acquire a free induction decay (FID) signal or an echo signal to generate a magnetic resonance image of a portion of an area of a subject. The resonance frequency acquirer is configured to acquire a resonance frequency of the portion of the area from the acquired FID signal. The RF driver is configured to generate a refocusing RF pulse having the acquired resonance frequency. The signal acquirer, the resonance frequency acquirer and the RF driver are configured to acquire and generate in each of sections of an RF pulse sequence. | 06-05-2014 |
20140184221 | HIGH-SPEED MAGNETIC RESONANCE IMAGING METHOD AND APPARATUS - Provided are high-speed magnetic resonance imaging methods and apparatuses that enable simultaneously obtaining magnetic resonance images with different resolutions. The present embodiments may produce magnetic resonance images with different resolutions more quickly by decreasing time taken to complete scan operations that are performed for producing the magnetic resonance images. | 07-03-2014 |
Patent application number | Description | Published |
20120120733 | SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME - Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit. | 05-17-2012 |
20120230139 | SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME - A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell. | 09-13-2012 |
20130003477 | SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells. | 01-03-2013 |
20130051133 | ANTI-FUSE CIRCUIT USING MTJ BREAKDWON AND SEMICONDUCTOR DEVICE INCLUDING SAME - An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided by the anti-fuses. | 02-28-2013 |
20130055048 | BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM - A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information. | 02-28-2013 |
20130083612 | MEMORY DEVICE INCLUDING REPAIR CIRCUIT AND REPAIR METHOD THEREOF - A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array. The repair circuit also includes a row address comparison unit configured to compare the row address of the defective cell with a row address of a first access cell received from the outside, and to output a first row match signal when the defective cell's row address matches the row address of the first access cell, and a column address comparison unit configured to compare the column address of the defective cell with a column address of the first access cell received from the outside, and to output a first column address replacement signal if the column address of the defective cell is the same as the column address of the first access cell. | 04-04-2013 |
20130088912 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first bit line to which a first memory cell is connected, and a second bit line to which a second memory cell is connected, the second bit line being complementary to the first bit line, a sense amplifier that includes a first transistor and a second transistor connected in series between the first bit line and the second bit line, the sense amplifier including a first node between the first transistor and the second transistor, a gate of the first transistor being connected to the second bit line, and a gate of the second transistor being connected to the first bit line, and a voltage providing unit that provides a first voltage to the first node during presensing, and provides a second voltage, different from the first voltage, to the first node during main sensing. | 04-11-2013 |
20130163355 | MEMORY DEVICE - A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal. | 06-27-2013 |
20130282973 | VOLATILE MEMORY DEVICE AND A MEMORY CONTROLLER - A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows. | 10-24-2013 |
20130286759 | METHOD OF SELECTING ANTI-FUSES AND METHOD OF MONITORING ANTI-FUSES - For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled. | 10-31-2013 |
20140013183 | MEMORY DEVICES WITH SELECTIVE ERROR CORRECTION CODE - An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells. | 01-09-2014 |
20140140153 | REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not. | 05-22-2014 |
20140146624 | MEMORY MODULES AND MEMORY SYSTEMS - In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit. | 05-29-2014 |
20140189215 | MEMORY MODULES AND MEMORY SYSTEMS - A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively. | 07-03-2014 |
20140241098 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values. | 08-28-2014 |
20140247677 | METHOD OF ACCESSING SEMICONDUCTOR MEMORY AND SEMICONDUCTOR CIRCUIT - A method of accessing a semiconductor memory is disclosed which includes outputting a row address and an active command to the semiconductor memory; outputting a column address and a read or write command to the semiconductor memory; and outputting a spare access command to the semiconductor memory to access data from a spare memory cell at a timing based on an additive latency of the semiconductor memory. Related devices and systems are also disclosed. | 09-04-2014 |
20140317469 | MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION - Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword. | 10-23-2014 |
20140359242 | MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE - A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device. | 12-04-2014 |
20150067448 | METHOD OF OPERATING MEMORY DEVICE AND METHODS OF WRITING AND READING DATA IN MEMORY DEVICE - In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word. | 03-05-2015 |
20150117083 | MEMORY DEVICE - A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal. | 04-30-2015 |
20160055056 | MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION - A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses. | 02-25-2016 |
20160062830 | SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF CORRECTING ERRORS IN THE SAME - A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array. | 03-03-2016 |
20160077940 | MEMORY DEVICE CAPABLE OF QUICKLY REPAIRING FAIL CELL - The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation. | 03-17-2016 |
20160104522 | METHOD OF USE TIME MANAGEMENT FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING USE TIME MANAGING CIRCUIT - A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data. | 04-14-2016 |
Patent application number | Description | Published |
20120038307 | Measurement System Using Alignment Unit And Method Of Determining System Parameters Of Alignment Unit - In one embodiment a method determines a system parameter of an alignment unit in a system that measures a position and posture of a workpiece, such as a substrate (or a semiconductor wafer), using the alignment unit. A mounting error of the alignment unit is determined, and a real system parameter value of the alignment unit is determined based on the mounting error, thereby accurately measuring position and posture information of the workpiece. | 02-16-2012 |
20120038936 | Measurement System Using Alignment Unit And Position Measuring Method - In one example embodiment, position of the alignment unit is acquired using a fiducial mark formed on a moving table, and the moving table is moved such that an alignment mark formed on the workpiece is located within a field of view of the alignment unit to measure the position of the alignment mark. Subsequently, the position and posture of the workpiece are accurately measured based on the position of the alignment unit and the position of the alignment mark measured by the alignment unit. | 02-16-2012 |
20120081682 | MASKLESS EXPOSURE APPARATUS AND METHOD TO DETERMINE EXPOSURE START POSITION AND ORIENTATION IN MASKLESS LITHOGRAPHY - According to an example embodiment, a method to determine an exposure start position and orientation includes loading a substrate on a moving table. The substrate includes at least one alignment mark of a first set of alignment marks of a first pattern layer patterned thereon. At least one alignment mark of a second set of alignment marks of a second pattern layer is exposed on the substrate using maskless lithography. A position of the at least one alignment mark of the first set of alignment marks and a position of the at least one alignment mark of the second set of alignment marks on the substrate is measured. A relative orientation difference between a desired exposure start orientation and an obtained exposure start orientation is acquired using the measured positions of the at least one alignment mark of the first set of alignment marks and the at least one alignment mark of the second set of alignment marks. A relative position difference between a desired exposure start position and an obtained start position is acquired using the measured positions of the at least one alignment mark of the first set of alignment marks and the at least one alignment mark of the second set of alignment marks. An exposure start position and orientation compensated using the relative position difference and the relative orientation difference is determined. | 04-05-2012 |
20130001898 | APPARATUS AND METHOD OF CONTROLLING CHUCK, AND EXPOSURE APPARATUS AND CONTROL METHOD THEREOF - Exemplary embodiments of the invention disclose an exposure apparatus and a method of tuning parameters of a chuck, which may reduce a time taken to level the chuck by previously tuning parameters of the chuck. The method of tuning parameters of a chuck includes detecting a tilt component of the chuck, performing chuck tilt adjustment to minimize the tilt component of the chuck, and tuning the parameters of the chuck if a residual tilt component is present after performing the chuck tilt adjustment. | 01-03-2013 |
20130044938 | MEASUREMENT SYSTEM USING ALIGNMENT SYSTEM AND POSITION MEASUREMENT METHOD - Disclosed herein are a system of measuring position information of a workpiece, such as a substrate (or a semiconductor wafer) using one or more alignment systems, and a position measurement method using the same. Positions of respective alignment systems are calculated using multiple fiducial marks (FMs) disposed on a fiducial alignment scope unit mark array (FAA) on a table, and positions of alignment marks (AMs) disposed on the workpiece are measured by moving the table so that the AMs are located within a field of vision (FOV) of the alignment system. The position information of the workpiece is measured using the position information of the alignment system and the position information of the FMs. | 02-21-2013 |
20130218304 | ULTRA-PRECISION POSITION CONTROL DEVICE AND METHOD FOR DETERMINING POSITION AND ATTITUDE INFORMATION ASSOCIATED WITH A 6-DEGREE-OF-FREEDOM STAGE THEREOF - A method of determining and controlling position and attitude information associated with a 6-degree-of-freedom stage includes: receiving, from a plurality of sensors associated with the 6-degree-of-freedom stage, displacement information associated with the 6-degree-of-freedom stage. A plurality of equations associated with the plurality of sensors are determined by a control unit based on the displacement information to represent an amount of change in position and attitude associated with each measurement axis of each of the plurality of sensors. The control unit determines position information and attitude information associated with the 6-degree-of-freedom stage using the equations. Movement of the 6-degree-of-freedom stage is caused, at least in part, to be controlled based on the position information, the attitude information, or both the position information and the attitude information. Three coordinate values associated with each valid measurement point of each of the plurality of sensors are associated with at least one degree of freedom. | 08-22-2013 |