Patent application number | Description | Published |
20080291737 | PROGRAM AND ERASE METHODS FOR NONVOLATILE MEMORY - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device. | 11-27-2008 |
20090055577 | PROGRAMMING METHODS FOR NONVOLATILE MEMORY - Example embodiments are directed to methods, memory devices, and systems for programming a nonvolatile memory device having a charge storage layer including performing at least one unit programming loop, each unit programming loop including, applying a programming pulse to at least two pages, applying a time delay to the at least two pages, and applying a verifying pulse to the at least two pages. | 02-26-2009 |
20100246258 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory cells, a voltage generator configured to generate voltages to program the plurality of memory cells, and a control logic component configured to control the voltage generator to provide a plurality of program voltages to selected memory cells during successive iterations of a program loop. Wherein where memory cells corresponding to one logic state are judged to be program passed during a current iteration of the program loop, the control logic component controls the voltage generator such that a program voltage corresponding to the one logic state is skipped during subsequent iterations of the program loop. | 09-30-2010 |
20100254188 | METHOD FOR PROGRAMMING NONVOLATILE MEMORY DEVICE - A method programs a nonvolatile memory device to program memory cells from one or more first logic states to two or more second logic states. In the method, a number of program voltages are provided to a selected word line, and verify voltages corresponding to the second logic states are provided to the selected word line. The number of the program voltages provided to the selected word line varies according to the threshold voltage difference between each of the first logic states and each of the second logic states. | 10-07-2010 |
20100302861 | Program and erase methods for nonvolatile memory - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device. | 12-02-2010 |
20120137067 | Non-Volatile Memory Device And Read Method Thereof - In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled. | 05-31-2012 |
20130083607 | METHOD OF READING MEMORY CELLS WITH DIFFERENT THRESHOLD VOLTAGES WITHOUT VARIATION OF WORD LINE VOLTAGE AND NONVOLATILE MEMORY DEVICE USING THE SAME - A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells. | 04-04-2013 |
20130223143 | NONVOLATILE MEMORY DEVICE HAVING ADJUSTABLE PROGRAM PULSE WIDTH - A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line. | 08-29-2013 |
20130223156 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A program method is provided for a nonvolatile memory device, including a substrate and multiple memory cells formed in a pocket well in the substrate. The program method includes supplying a program voltage to a selected word line during a program execution period of a program loop, supplying a verification voltage to the selected word line during a verification period of the program loop, and supplying a negative voltage to the pocket well as a well bias voltage during the verification period. | 08-29-2013 |
20130322171 | METHODS OF OPERATING NONVOLATILE MEMORY DEVICES THAT SUPPORT EFFICIENT ERROR DETECTION - Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells. | 12-05-2013 |
20140334233 | METHOD OF READING MEMORY CELLS WITH DIFFERENT THRESHOLD VOLTAGES WITHOUT VARIATION OF WORD LINE VOLTAGE AND NONVOLATILE MEMORY DEVICE USING THE SAME - A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells. | 11-13-2014 |
20150052294 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a nonvolatile memory device includes receiving a read command from a memory controller; determining a read mode based on the received read command, controlling a precharge time and an offset of a precharge control signal according to the determination result, and precharging a sensing bit line among bit lines to a precharge voltage based on the controlled precharge control signal. The sensing bit line is a bit line being precharged according to the determined read mode among the bit lines. | 02-19-2015 |
20150179271 | NONVOLATILE MEMORY DEVICE AND METHOD OF ERASING NONVOLATILE MEMORY DEVICE - A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block. | 06-25-2015 |
20150248930 | METHODS OF OPERATING NONVOLATILE MEMORY DEVICES THAT SUPPORT EFFICIENT ERROR DETECTION - Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells. | 09-03-2015 |
Patent application number | Description | Published |
20150114466 | CIGS Solar Cell Having Flexible Substrate Based on Improved Supply of Na and Fabrication Method Thereof - A CIGS solar cell having a flexible substrate based on improved supply of Na. The CIGS solar cell includes a substrate formed of a flexible material, a rear electrode formed on the substrate, a CIGS light-absorption layer formed on the rear electrode, a buffer layer formed on the CIGS light-absorption layer, and a front electrode formed on the buffer layer, wherein the rear electrode comprise a single-layered Na-added metal electrode layer. A single-layered Na-added Mo electrode layer, specific resistance of which is about 1/10th the specific resistance under conditions of a process of forming a typical multilayer rear electrode, is applied to the rear electrode, thereby providing a CIGS solar cell having a flexible substrate and high conversion efficiency. | 04-30-2015 |
20150162480 | METHOD OF MANUFACTURING CI(G)S-BASED THIN FILM HAVING REDUCED CARBON LAYER, THIN FILM MANUFACTURED BY THE METHOD, AND SOLAR CELL COMPRISING THE THIN FILM - Disclosed is a method of manufacturing a CI(G)S-based thin film, in which a slurry prepared by mixing two or more kinds of binary nanoparticles containing CI(G)S-based elements, a solution precursor containing a CI(G)S-based element, an alcoholic solvent and a chelating agent is used to reduce the carbon layer formed between the CI(G)S-based thin film and molybdenum, and which includes (a) mixing two or more kinds of binary nanoparticles containing CI(G)S-based elements, a solution precursor containing a CI(G)S-based element, an alcoholic solvent and a chelating agent, thus preparing a slurry; (b) subjecting the slurry to non-vacuum coating, thus forming a CI(G)S-based thin film; and (c) subjecting the CI(G)S-based thin film to selenization heat treatment. | 06-11-2015 |
20150243382 | PASSIVE CONTAINMENT AIR COOLING DEVICE AND SYSTEM WITH ISOLATED PRESSURE BOUNDARY - Provided is a passive containment air cooling device with an isolated pressure boundary, including a heat exchanger positioned inside and outside a containment, penetrating through an outer wall of the containment to be connected to the containment through a pipe and thus form a closed loop, and including a coolant, an air induction duct circulating air outside the heat exchanger, and a cooled air exhaust unit formed in the air induction duct to increase cooling efficiency of the heat exchanger. | 08-27-2015 |
20150243383 | WATER-AIR COMBINED PASSIVE FEED WATER COOLING APPARATUS AND SYSTEM - Disclosed herein is a water-air combined passive feed water cooling apparatus including a water cooling heat exchanger connected to the inside of a containment building to cool down heat of a steam generator using a water cooling method, a cooling tank including the water cooling heat exchanger therein and storing cooling water condensing main steam generated by the steam generator, an evaporative steam pipe connected to the cooling tank, the evaporative steam pipe, into which steam of the cooling water generated by the water cooling heat exchanger in the cooling tank flows, an air cooling heat exchanger connected to the evaporative steam pipe and cooling down and liquefying the steam flowing into the evaporative steam pipe, and a condensed water collecting pipe for refilling the cooling tank with the steam liquefied by the air cooling heat exchanger. | 08-27-2015 |
20150243384 | COOLING WATER SUPPLY TANK HAVING HEAT MIXING PREVENTION FUNCTION AND PASSIVE HIGH-PRESSURE SAFETY INJECTION SYSTEM AND METHOD USING THE SAME - A passive high-pressure safety injection system includes a compressor which generates high-temperature and high-pressure steam, a cooling water supply tank which supplies cooling water using the compressed steam, a nuclear reactor which receives the cooling water so that the nuclear reactor is maintained in a cooled state, and an internal circulation prevention structure which is provided in the cooling water supply tank and prevents the cooling water from circulating in the cooling water supply tank. | 08-27-2015 |
20150287868 | ULTRA THIN HIT SOLAR CELL AND FABRICATING METHOD OF THE SAME - Disclosed is an ultra-thin HIT solar cell, including: an n- or p-type crystalline silicon substrate; an amorphous silicon emitter layer having a doping type different from that of the silicon substrate; and an intrinsic amorphous silicon passivation layer formed between the crystalline silicon substrate and the amorphous silicon emitter layer, wherein the HIT solar cell further includes a transparent conductive oxide layer made of ZnO on an upper surface thereof, and the surface of the crystalline silicon substrate is not textured but only the surface of the transparent conductive oxide layer is textured, and thereby a very thin crystalline silicon substrate can be used, ultimately achieving an ultra-thin HIT solar cell having a very low total thickness while maintaining light trapping capacity. | 10-08-2015 |