Patent application number | Description | Published |
20100075503 | INTEGRAL PATTERNING OF LARGE FEATURES ALONG WITH ARRAY USING SPACER MASK PATTERNING PROCESS FLOW - Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit. | 03-25-2010 |
20110061810 | Apparatus and Methods for Cyclical Oxidation and Etching - Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device. | 03-17-2011 |
20110065276 | Apparatus and Methods for Cyclical Oxidation and Etching - Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device. | 03-17-2011 |
20130273733 | Methods for Depositing Manganese and Manganese Nitrides - Described are manganese-containing films, as well as methods for providing the manganese-containing films. Doping manganese-containing films with Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V allows for enhanced copper barrier properties of the manganese-containing films. Also described are methods of providing films with a first layer comprising manganese silicate and a second layer comprising a manganese-containing film. | 10-17-2013 |
20130292806 | Methods For Manganese Nitride Integration - Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer. | 11-07-2013 |
Patent application number | Description | Published |
20100022067 | DEPOSITION METHODS FOR RELEASING STRESS BUILDUP - A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature. | 01-28-2010 |
20100062603 | SEMICONDUCTOR DEVICES SUITABLE FOR NARROW PITCH APPLICATIONS AND METHODS OF FABRICATION THEREOF - Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device. | 03-11-2010 |
20110053380 | SILICON-SELECTIVE DRY ETCH FOR CARBON-CONTAINING FILMS - A method of etching silicon-and-carbon-containing material is described and includes a SiConi™ etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi™ etch reducing the carbon content in the near surface region and allowing the SiConi™ etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi™ etch further improving the effective etch rate. | 03-03-2011 |
20110151674 | SMOOTH SICONI ETCH FOR SILICON-CONTAINING FILMS - A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size. | 06-23-2011 |
20110151676 | METHODS OF THIN FILM PROCESS - A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space. | 06-23-2011 |
20110230052 | INVERTABLE PATTERN LOADING WITH DRY ETCH - A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench. | 09-22-2011 |
20110266252 | HIGH-TEMPERATURE SELECTIVE DRY ETCH HAVING REDUCED POST-ETCH SOLID RESIDUE - Methods of dry etching silicon-containing dielectric films are described. The methods include maintaining a relatively high temperature of the dielectric films while etching in order to achieve reduced solid residue on the etched surface. Partially or completely avoiding the accumulation of solid residue increases the etch rate. | 11-03-2011 |
20120196447 | UNIFORM DRY ETCH IN TWO STAGES - A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages. | 08-02-2012 |
Patent application number | Description | Published |
20090245718 | Optical Sensor And Method Employing Half-Core Hollow Optical Waveguide - An optical sensor, sensing system and method of sensing employ a half-core hollow optical waveguide adjacent to a surface of an optical waveguide layer of a substrate. The half-core hollow optical waveguide and the adjacent optical waveguide layer cooperatively provide both an optical path that confines and guides an optical signal and an internal hollow channel. The optical path and channel extend longitudinally along a hollow core of the half-core hollow optical waveguide. The system further includes an optical source at an input of the optical path and an optical detector at an output of the optical path. A spectroscopic interaction between an analyte material that is introduced into the channel and an optical signal propagating along the optical path determines a characteristic of the analyte material. | 10-01-2009 |
20100079754 | SYSTEMS FOR PERFORMING RAMAN SPECTROSCOPY - Various embodiments of the present invention relate generally to systems for performing Raman spectroscopy. In one embodiment, a system for performing Raman spectroscopy comprises an analyte holder having a surface configured to retain an analyte and a light concentrator configured to receive an incident beam of light, split the incident beam into one or more beams, and direct the one or more beams to substantially intersect at the surface. The system may also include a collector configured to focus each of the one or more beams onto the surface, collect the Raman scattered light emitted from the analyte, and direct the Raman scattered light away from the surface. | 04-01-2010 |
20110227032 | Memristor with Nanostructure Electrodes - A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode. | 09-22-2011 |
20110228266 | SUBSTRATE FOR SURFACE ENHANCED RAMAN SCATTERING (SERS) - A substrate for Surface Enhanced Raman Scattering (SERS). The substrate comprises at least one nanostructure protruding from a surface of the substrate and a SERS active metal over the at least one nanostructure, wherein the SERS active metal substantially covers the at least one nanostructure and the SERS active metal creates a textured layer on the at least one nanostructure. | 09-22-2011 |
20120182550 | WAVEGUIDES CONFIGURED WITH ARRAYS OF FEATURES FOR PERFORMING RAMAN SPECTROSCOPY - Embodiments of the present invention are directed to systems for performing surface-enhanced Raman spectroscopy. In one embodiment, a system for performing Raman spectroscopy includes a waveguide layer (102,402,702,902) configured with at least one array of features, and a material (110,410,710,910) disposed on at least a portion of the features. Each array of features and the waveguide layer are configured to provide guided-mode resonance for at least one wavelength of electromagnetic radiation. The electromagnetic radiation produces enhanced Raman scattered light from analyte molecules located on or in proximity to the material. | 07-19-2012 |
Patent application number | Description | Published |
20120187467 | FLOATING GATES AND METHODS OF FORMATION - The present invention generally relates to a floating gate structure and method of forming the same. The floating gate structure has an upper portion which is wider than a middle portion of the floating gate structure. The upper portion may have a flared, rounded or bulbous shape instead of being pointed or having sharp corners. The reduction in pointed or sharp features of the upper portion reduces the electric field intensity near the upper portion, which decreases current leakage through the interpoly dielectric. The method includes forming a nitride cap on the upper surface of the floating gate structure to assist in shaping the floating gate. The floating gate is then formed using multiple selective oxidation and etching processes. | 07-26-2012 |
20130048605 | DOUBLE PATTERNING ETCHING PROCESS - A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C. | 02-28-2013 |
20130260533 | INTRENCH PROFILE - A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. | 10-03-2013 |
20130260564 | INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION - Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF. | 10-03-2013 |
20150031211 | INTRENCH PROFILE - A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. | 01-29-2015 |