Patent application number | Description | Published |
20100304057 | COATED MEDIUM FOR INKJET PRINTING AND METHOD OF FABRICATING THE SAME - A coated medium for inkjet printing is disclosed. The coated medium includes a coating layer formed on at least one side of a supporting substrate. The coating layer includes precipitated calcium carbonate with an average particle size of less than about 1 micron, silica with a surface area of greater than 100 m | 12-02-2010 |
20110008542 | INKJET RECORDING MATERIAL - An inkjet recording material which comprises a supporting substrate, a first bottom base coat applied to at least one surface of said substrate, and a second topcoat layer applied over said base coat. In said inkjet recording material, the base coat includes a combination of at least three pigments and the topcoat layer comprises pigments selected from the group consisting of fumed silica, silica gel, precipitated silica, colloidal silica, fumed alumina, boehmite, pseudo-boehmite or a mixture thereof. | 01-13-2011 |
20110104408 | PRINT MEDIUM FOR INKJET WEB PRESS PRINTING - A print medium suitable for inkjet web press printing is disclosed herein. The print medium includes a paper substrate and an ink-receiving layer coated onto at least one surface of the paper substrate. The ink-receiving layer includes: two different inorganic pigments with different particle sizes; a binder; a water-soluble metallic salt; and a colorant durability enhancer selected from the group consisting of boric acid, borax, sodium tetraborate, phenyl boronic acid, butyl boronic acid and combinations thereof. | 05-05-2011 |
20110104410 | COATED MEDIUM FOR INKJET PRINTING - A coated medium for inkjet printing, which includes a supporting substrate and a coating layer formed on at least one side thereof. The coating layer includes at least one binder and at least two different inorganic pigments: modified calcium carbonate (MCC) and either precipitated calcium carbonate (PCC) or clay. | 05-05-2011 |
20130257990 | PRINTING METHOD - A printing method for producing durable images onto a printable recording medium is disclosed herein. The printing method encompasses providing a printable recording media; applying an ink composition containing a liquid vehicle and a colorant; wherein the print speed of the printing method is 50 fpm or higher. The printable recording media encompasses a base substrate, a first ink-receiving layer containing more than about 80 wt % of one or more particulate inorganic pigments and a second ink-receiving layer, on top of the first ink-receiving layer, including particulate inorganic pigments having an average particle size of about 0.1 to about 2 μm. | 10-03-2013 |
20140044896 | MEDIA USED IN DIGITAL HIGH SPEED INKJET WEB PRESS PRINTING - A media for digital high speed inkjet web press printing has a CD residual tensile energy absorption index greater than 300 J/Kg. The media includes a paper base having a MD/CD tensile stiffness index ratio of less than 2.0 and a tensile energy absorption index of greater than 500 J/Kg. The paper base includes a mixture of fibers having a softwood fiber to hardwood fiber ratio within a range of 3 to 7 to 7 to 1, an internal starch having a cationic starch to fiber ratio greater than 1.0%, and a filler within a range of about 1.0% to about 12.0% of paper base weight. The media further includes an image receiving coating on a side of the paper base. | 02-13-2014 |
20140154433 | PRINT MEDIUM - A print medium includes a first layer on at least one of a first side and a second side of a substrate and a second layer. The first layer consists essentially of at least 80% by dry weight of one or more particulate inorganic pigments (PIPs). A combination of a particle size and a coat weight of the first layer on the substrate yields an effective pore size of the first layer in a range of about 0.008 to about 0.5 microns. For two or more PIPs in the first layer, the average particle size of one of the PIPs differs by no more than about 50% from the average particle size of another of the PIPs. The second layer is on top of the first layer and includes a particulate inorganic pigment (PIP) having an average particle size of about 0.1 to about 2 microns. | 06-05-2014 |
20140212591 | PRE-TREATMENT COATING - The present disclosure provides pre-treatment compositions and related methods. As such, a pre-treatment coating for a print medium can include an evaporable solvent, a matrix, and a wax. The matrix can include from 50 wt % to 80 wt % of a fixer and from 5 wt % to 20 wt % of a low Tg latex. The wax can be present at from 5 wt % to 30 wt %. The weight percentages of the matrix and the wax are based on a total amount present in the pre-treatment coating after removal of the solvent. | 07-31-2014 |
20150336400 | Post-Printing Treatment - A post-printing treatment for printed media includes a wax suspended in water. Particles of the wax to lie upon at least an inkjet ink image on the printed media to facilitate abrasion resistance of the image. | 11-26-2015 |
20150344708 | SWELLABLE PRE-TREATMENT COATING - The present disclosure provides swellable pre-treatment compositions, printable media, and related methods. As such, a swellable pre-treatment coating for a print medium can include an evaporable solvent, a matrix, and a wax. The matrix can include from 10 wt % to 20 wt % of a fixer, from 25 wt % to 35 wt % of aluminum chiorohydrate, from (15 wt % to 10 wt % of a first binder, from 20 wt % to 30 wt % of a second cross-linkable binder, and from 1 wt % to 5 wt % of a cross-linker. The wax can be present at from 10 wt % to 20 wt %, The weight percentages of the matrix and the wax are based on a total amount present in the swellabie pre-treatment coating after removal of the evaporable solvent. | 12-03-2015 |
20150352877 | PRE-TREATMENT COATING - The present disclosure provides pre-treatment coatings, media substrates, and related methods. As such, a pre-treatment coating can include an evaporable solvent, a matrix, and a wax. The matrix can include a binder and a fixer, and the wax can include wax particles dispersed within the matrix. At least a portion of the wax particles can have a particle size that is greater than a thickness of the matrix when the pre-treatment coating is applied to a media substrate at a basis weight from 0.5 gsm to 20 gsm and the evaporable solvent removed. | 12-10-2015 |
Patent application number | Description | Published |
20100215139 | COUNTERS AND EXEMPLARY APPLICATIONS - Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C | 08-26-2010 |
20100271246 | PROVIDING LINEAR RELATIONSHIP BETWEEN TEMPERATURE AND DIGITAL CODE - Mechanisms for providing linear relationship between temperatures and digital codes are disclosed. In one method, at a particular temperature, a circuit in the sensor provides a temperature dependent reference voltage, and a compared voltage, to a comparator. The temperature dependent reference voltage depends on temperature in complement to absolute temperature or alternatively depends on temperature in proportion to absolute temperature. The compared voltage is generated corresponding to digital analog converter (DAC) codes as inputs. Another circuit varies the DAC codes until the temperature dependent reference voltage and the compared voltage are equal so that the dependent reference voltage corresponds to a DAC code. The various temperatures experienced by the temperature sensing circuit and the DAC codes are substantially linearly related | 10-28-2010 |
20110001557 | VOLTAGE REFERENCE CIRCUIT WITH TEMPERATURE COMPENSATION - A voltage reference circuit with temperature compensation includes a power supply, a reference voltage supply, a first PMOS transistor with its source connected to the power supply voltage, a second PMOS transistor with its source connected to the power supply and its gate and drain connected to the first PMOS gate, a first NMOS transistor with its gate and drain connected the first PMOS drain, a second NMOS transistor with its drain connected to the second PMOS drain and its gate connected with the first NMOS gate to the reference voltage supply, a resistor connected to the second NMOS source and ground, and an op-amp with its inverting input and its output connected the first NMOS source and its non-inverting input connected to the ground. In another aspect, a voltage reference circuit output is coupled to an NMOS gate in saturation mode connected to another voltage reference circuit. | 01-06-2011 |
20110199152 | INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF - An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node. | 08-18-2011 |
20110255568 | THERMAL SENSORS AND METHODS OF OPERATING THEREOF - A thermal sensor includes a comparator having a first and second input nodes. A reference voltage generator is electrically coupled with the first input node. The reference voltage generator is configured to provide a reference voltage that is substantially temperature-independent. A temperature sensing circuit is electrically coupled with the second input node. The temperature sensing circuit is configured to provide a temperature-dependent voltage. The temperature sensing circuit includes a current mirror. A first metal-oxide-semiconductor (MOS) transistor is electrically coupled between the current mirror and ground. A first resistor is electrically coupled with the current mirror. A second MOS transistor is electrically coupled with the first resistor in series. The second MOS transistor and the first resistor are electrically coupled with the first MOS transistor in a parallel fashion. | 10-20-2011 |
20110267880 | MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASED CONTROL - A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor. | 11-03-2011 |
20120013374 | PHASE-LOCK ASSISTANT CIRCUITRY - Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock. | 01-19-2012 |
20120200323 | PHASE-LOCK ASSISTANT CIRCUITRY - A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal. | 08-09-2012 |
20130106475 | METHOD OF OPERATING PHASE-LOCK ASSISTANT CIRCUITRY | 05-02-2013 |
20130188416 | MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASED CONTROL - A memory circuit including at least one memory array and at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage. The memory circuit further includes at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line and a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor. | 07-25-2013 |
20130272340 | TEMPERATURE SENSING CIRCUIT - A circuit includes a comparator, a first circuit, and a second circuit. The comparator has a first input node and a second input node. The first circuit is configured to output a temperature-dependent voltage at the first input node of the comparator. The first circuit includes a current mirror configured to generate a first reference voltage. The second circuit is configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage. | 10-17-2013 |
20140035553 | VOLTAGE REFERENCE CIRCUIT WITH TEMPERATURE COMPENSATION - A voltage reference circuit with temperature compensation includes a power supply, a first reference voltage supply, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor connected to the second NMOS source and ground. The voltage reference circuit also includes a second reference voltage supply, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor with a drain connected to the source of the fourth NMOS transistor, a source connected to the ground, and a gate connected to the first reference voltage output. | 02-06-2014 |
Patent application number | Description | Published |
20100253303 | VOLTAGE REGULATOR WITH HIGH ACCURACY AND HIGH POWER SUPPLY REJECTION RATIO - A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed. | 10-07-2010 |
20100259311 | LEVEL SHIFTERS, INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR OPERATING THE LEVEL SHIFTERS - A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor. | 10-14-2010 |
20110285445 | DRIVE LOOP FOR MEMS OSCILLATOR - Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range. | 11-24-2011 |
20110310690 | VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF - A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator. | 12-22-2011 |
20120032731 | CHARGE PUMP DOUBLER - An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor. | 02-09-2012 |
20120044008 | LEVEL SHIFTERS FOR IO INTERFACES - A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device. | 02-23-2012 |
20130069724 | SUPPLY INDEPENDENT BIASING CIRCUIT - A supply-independent biasing source includes an upper current mirror including first and second PMOS transistors and a lower current mirror coupled to the upper current mirror including first and second NMOS transistors. The first NMOS and first PMOS transistors have drain terminals coupled together and form a first stack of transistors and the second NMOS and second PMOS transistors have drain terminals coupled together and form a second stack of transistors. A first resistive load is connected to one of the first and second stacks, wherein the resistive load comprises a first MOSFET transistor biased at triode region. | 03-21-2013 |
20130082754 | PHASE LOCKED LOOP CALIBRATION - An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range. | 04-04-2013 |
20130099767 | DRIVERS HAVING T-COIL STRUCTURES - A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage. | 04-25-2013 |
20130120884 | INPUT/OUTPUT CIRCUIT WITH INDUCTOR - An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. | 05-16-2013 |
20130121396 | DECISION FEEDBACK EQUALIZER HAVING PROGRAMMABLE TAPS - A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel. | 05-16-2013 |
20130127433 | METHOD OF OPERATING VOLTAGE REGULATOR - A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating. | 05-23-2013 |
20130141170 | AMPLIFIER INDUCTOR SHARING FOR INDUCTIVE PEAKING - A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking. | 06-06-2013 |
20130222015 | LEVEL SHIFTERS FOR IO INTERFACES - An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level. | 08-29-2013 |
20130346811 | DECISION FEEDBACK EQUALIZER - A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. | 12-26-2013 |
20140015611 | METHOD AND APPARATUS FOR FEEDBACK-BASED RESISTANCE CALIBRATION - A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage. | 01-16-2014 |
20140037035 | PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS - A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal. | 02-06-2014 |
20140085009 | AMPLIFIER INDUCTOR SHARING FOR INDUCTIVE PEAKING AND METHOD THEREFOR - A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking. | 03-27-2014 |
20140092511 | INPUT/OUTPUT CIRCUIT HAVING AN INDUCTOR - An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage. | 04-03-2014 |
20140103967 | LEVEL SHIFTERS, METHODS FOR MAKING THE LEVEL SHIFTERS AND METHODS OF USING INTEGRATED CIRCUITS - A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal. | 04-17-2014 |
20140126656 | CLOCK DATA RECOVERY CIRCUIT WITH HYBRID SECOND ORDER DIGITAL FILTER HAVING DISTINCT PHASE AND FREQUENCY CORRECTION LATENCIES - A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles. | 05-08-2014 |
20140266114 | METHOD OF OPERATING VOLTAGE REGULATOR - A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit. | 09-18-2014 |
20150035566 | DRIVERS HAVING T-COIL STRUCTURES - A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance. | 02-05-2015 |
20150131711 | APPARATUS HAVING PROGRAMMABLE TAPS - An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors. | 05-14-2015 |
20150243341 | VOLTAGE REGULATOR - A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode. | 08-27-2015 |
20150319017 | APPARATUS HAVING PROGRAMMABLE TAPS AND METHOD OF USING THE SAME - An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights. | 11-05-2015 |
20160072279 | CIRCUIT AND METHOD FOR INCREASING INDUCTOR CURRENT - A method of increasing a current flowing through an inductor includes receiving an input signal with a driver stage, the driver stage including the inductor coupled in series with a loading between an output node of the driver stage and a power line. In response to a transition in the input signal from a first voltage state to a second voltage state, a first current flowing through the loading and the inductor is increased. During the transition in the input signal, the current flowing through the inductor is increased by increasing a second current in a circuitry though a node between the inductor and the loading. | 03-10-2016 |
20160087817 | DECISION FEEDBACK EQUALIZER SUMMATION CIRCUIT - A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. | 03-24-2016 |