Patent application number | Description | Published |
20110267974 | COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, AND SLAVE STATION APPARATUS - A communication apparatus includes a main-data processing unit that performs predetermined data processing on input data, and operates by switching two states of a sleep state as a state where an operation of the main-data processing unit is stopped and a normal state as a state where the main-data processing unit is operating. The communication apparatus includes a filtering unit that extracts communication state information for indicating a communication state from the input data, and a signal processing unit of a sub-data processing unit that shifts the main-data processing unit to a sleep state or a normal state based on the communication state information. | 11-03-2011 |
20120128372 | OPTICAL LINE TERMINATION, PON SYSTEM, AND DATA RECEPTION PROCESSING METHOD - An optical line termination includes a deserializer that parallelizes burst data received from a termination device, a fixed-pattern generating unit that generates fixed pattern data that is a predetermined fixed data, and a data selecting unit that selects either the fixed pattern data or the burst data based on a data-head instruction signal indicating a head of the burst data and a data-end instruction signal indicating an end of the burst data, and inputs the selected data to a deserializer as data to be parallelized. | 05-24-2012 |
20130045005 | COMMUNICATION METHOD FOR OPTICAL COMMUNICATION SYSTEM, OPTICAL COMMUNICATION SYSTEM, SLAVE STATION APPARATUS, CONTROL DEVICE, AND COMPUTER PROGRAM - The control device includes a power-saving control unit that intermittently repeats, based on a power saving permission signal transmitted from the master station apparatus, power saving control in which the slave station stops or reduces power supply to a transmitter or a receiver for a predetermined pause duration while maintaining a communication link and a monitoring unit that monitors out of synchronization by comparing a synchronization signal received from the OLT and a time of the ONU. The control device shifts from a registered state to a deregistered state when the monitoring unit detects the out of synchronization. On the other hand, after the pause duration of the power saving control, the control device suppresses the shift to the deregistered state due to the detection of the out of synchronization. | 02-21-2013 |
20130266306 | TIME SYNCHRONIZATION METHOD FOR COMMUNICATION SYSTEM, SLAVE STATION APPARATUS, MASTER STATION APPARATUS, CONTROL DEVICE, AND PROGRAM - A time synchronization method for a communication system configured to perform protection switching, the communication system including a first network in which a master station and a slave station are connected via plural physical lines including a working line and a backup line and a second network connected to the slave station, the method including a time synchronization in which the slave station executes, when not detecting a communication failure of a downlink signal transmitted from the master station, synchronization processing for synchronizing, based on a clock of the slave station and timing information, time information transmitted to the second network with time information included in a time synchronization command and suppresses, when detecting a communication failure or receiving a switching notification from the master station apparatus, a synchronization error due to a difference between the clock of the slave station and the timing information. | 10-10-2013 |
20130315587 | COMMUNICATION SYSTEM, COMMUNICATION-LINE SWITCHING METHOD, AND MASTER STATION DEVICE - A communication system in which a combination of redundant configurations of communication lines and a power-saving-mode operating function is incorporated, and includes a power-saving-device identification unit that identifies a slave station device in a power saving mode, and a line switching unit that switches a communication line forming a communication route from the currently used communication line to the backup communication line when a state where a master station device does not receive a signal from any of a plurality of slave station devices except for the slave station device identified by the power-saving-device identification unit as being in the power saving mode among the slave station devices continues for a predetermined time. | 11-28-2013 |
Patent application number | Description | Published |
20110292715 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element. | 12-01-2011 |
20120014163 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line. | 01-19-2012 |
20120075909 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. | 03-29-2012 |
20120266043 | SEMICONDUCTOR MEMORY DEVICE - The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse. | 10-18-2012 |
20120314480 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit. | 12-13-2012 |
20130088911 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device includes a writing circuit and a reading circuit. The writing circuit executes a setting action for converting a resistance of a variable resistance element to a low resistance by applying current from one end side to the other end side of a memory cell via the variable resistance element, and a resetting action for converting the resistance to a high resistance by applying current from the other end side to the one end side via the variable resistance element. The reading circuit executes a first reading action for reading a resistance state of the variable resistance element by applying current from one end side to the other end side of the memory cell via the variable resistance element, and a second reading action for reading the resistance state by applying current from the other end side to the one end side via the variable resistance element. | 04-11-2013 |
20150036217 | OPTICAL FILTER - An optical filter configured to transmit light of a predetermined wavelength includes a substrate; a first conductive thin film that is disposed on the substrate and has apertures extending through the first conductive thin film and arranged with a period of less than the predetermined wavelength; and a second conductive thin film at least a portion of which faces the apertures so as to be separated from the apertures. | 02-05-2015 |
Patent application number | Description | Published |
20100251046 | FAILURE PREDICTION CIRCUIT AND METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs. | 09-30-2010 |
20140091830 | TEST APPARATUS - A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values. | 04-03-2014 |
20140176205 | SIGNAL CONVERSION CIRCUIT, PLL CIRCUIT, DELAY ADJUSTMENT CIRCUIT, AND PHASE CONTROL CIRCUIT - A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC | 06-26-2014 |
Patent application number | Description | Published |
20130266278 | OPTICAL CONNECTOR - An optical connector includes a housing, a photoelectric conversion circuit board on which a photoelectric conversion element is mounted, and a resin member made of a light transmissive synthetic resin and arranged on a plate surface of the photoelectric conversion circuit board so as to cover the photoelectric conversion element. The photoelectric conversion circuit board is housed in the housing. The resin member includes a sleeve to which a ferrule attached to an end of an optical fiber is fitted. The sleeve of the resin member is arranged such that an axial direction thereof is substantially perpendicular to the plate surface of the photoelectric circuit board. The resin member integrally includes a lens on an axial line of the sleeve such that the lens faces the photoelectric conversion element. | 10-10-2013 |
20130272663 | OPTICAL ASSEMBLY - An optical assembly includes a circuit board including an electrically conductive path formed by printed wiring technology, a photoelectric conversion element connected to the circuit board via the electrically conductive path, a resin member made of light transmissive synthetic resin and attached to the circuit board, and a shielding member made of metal. The resin member includes a sleeve into which a ferrule attached to an end of an optical fiber is inserted and integrally includes a lens through which an optical path passes. The optical path extends between the sleeve and the photoelectric conversion element. The shielding member is connected to the circuit board and arranged to cover the photoelectric conversion element. The shielding member includes a window through which the optical path extends to the photoelectric conversion element. | 10-17-2013 |
20130336620 | OPTICAL MODULE AND METHOD OF MANUFACTURING OPTICAL MODULE - A method of manufacturing an optical module includes the steps of applying the invisible light onto the resin member and the optical device, observing, with use of a camera, a part of the resin member located at the optical fiber coupling plane and an image formed at the optical fiber coupling plane by the optical device active layer while applying the invisible light onto the resin member and the optical device, aligning positions of the resin member and the circuit board with respect to each other while observing the part of the resin member located at the optical fiber coupling plane and the image formed at the optical fiber coupling plane, and fixing the resin member to the circuit board while maintaining the aligned positions of the resin member and the circuit board. | 12-19-2013 |