Patent application number | Description | Published |
20100291088 | IL-18 BINDING PROTEINS - The present invention encompasses IL-18 binding proteins, particularly antibodies that bind human interleukin-18 (hIL-18). Specifically, the invention relates to antibodies that are entirely human antibodies. Preferred antibodies have high affinity for hIL-18 and/or that neutralize hIL-18 activity in vitro and in vivo. An antibody of the invention can be a full-length antibody or an antigen-binding portion thereof. Method of making and method of using the antibodies of the invention are also provided. The antibodies, or antibody portions, of the invention are useful for detecting hIL-18 and for inhibiting hIL-18 activity, e.g., in a human subject suffering from a disorder in which hIL-18 activity is detrimental. | 11-18-2010 |
20140088296 | IL-18 BINDING PROTEINS - The present invention encompasses IL-18 binding proteins, particularly antibodies that bind human interleukin-18 (hIL-18). Specifically, the invention relates to antibodies that are entirely human antibodies. Preferred antibodies have high affinity for hIL-18 and/or that neutralize hIL-18 activity in vitro and in vivo. An antibody of the invention can be a full-length antibody or an antigen-binding portion thereof. Method of making and method of using the antibodies of the invention are also provided. The antibodies, or antibody portions, of the invention are useful for detecting hIL-18 and for inhibiting hIL-1 activity, e.g., in a human subject suffering from a disorder in which hIL-18 activity is detrimental. | 03-27-2014 |
Patent application number | Description | Published |
20120330232 | HIGH STRENGTH BALLOON COVER AND METHOD OF MAKING - A balloon cover is provided to enhance the performance of a medical balloon, the cover, in accordance with an embodiment, having overlapping portions and opposed apertures located at apexes of tapered ends of the balloon cover. A method of making balloon covers is also disclosed. | 12-27-2012 |
20130253466 | CONTROLLABLE INFLATION PROFILE BALLOON COVER APPARATUS AND METHODS - Embodiments are presented of a balloon assembly operable to provide a balloon diameter vs. balloon pressure profile generally depicting a balloon inflation sequence providing at least one intermediate inflated diameter and a final inflated diameter of a balloon such that the balloon attains the at least one intermediate diameter at a predetermined pressure, and attains the final diameter at a final predetermined pressure that is lower than a predetermined pressure of a last intermediate pressure. | 09-26-2013 |
20130306232 | DEVICES AND METHODS FOR ATTACHING SUPPORT FRAMES TO SUBSTRATES - Devices and methods for attaching support frames to substrates to form articles such as implantable stent grafts. | 11-21-2013 |
20140172066 | MEDICAL BALLOON DEVICES AND METHODS - A balloon or balloon cover comprising a composite material having a least one expanded fluoropolymer material and an elastomer is provided. The expanded fluoropolymer material can contain serpentine fibrils. In exemplary embodiments, the fluoropolymer is polytetrafluoroethylene. The composite material may be axially, helically, and/or circumferentially wrapped to form a balloon or balloon cover. The balloon or balloon cover exhibits a sharp increase in stiffness at a predetermined diameter. The balloon or balloon cover can be designed to have a stop point in either a radial or axial direction. | 06-19-2014 |
Patent application number | Description | Published |
20090144492 | STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE - A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache. | 06-04-2009 |
20090144504 | STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS - A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, which is smaller than retention time of data in the DRAM data cache; wherein, for any of the cache lines not accessed as a result of a read or a write operation during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid. | 06-04-2009 |
20090144507 | APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS - An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid. | 06-04-2009 |
20140143748 | SEMICONDUCTOR TIMING IMPROVEMENT - Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip. | 05-22-2014 |
20140184242 | In-Line Transistor Bandwidth Measurement - A method and apparatus measure transistor bandwidth of a device under test in-line and on-wafer. The method includes disposing a measurement circuit on a chip within a wafer, the measurement circuit including a ring oscillator generating an oscillation frequency for transition through the device under test on the wafer, and obtaining an amplitude gain based on the measurement circuit for the corresponding frequency. | 07-03-2014 |
20140188265 | SYSTEMS AND METHODS FOR SEMICONDUCTOR LINE SCRIBE CENTERING - Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits. | 07-03-2014 |
20140188266 | MULTIPLE MANUFACTURING LINE QUALIFICATION - Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one or more manufacturing lines. The products include product macros placed on a chip. The method also includes establishing allowed parametric match from line to line. The method further includes determining that products from the one or more manufacturing lines meet the allowed parametric match. | 07-03-2014 |
Patent application number | Description | Published |
20120102401 | METHOD AND APPARATUS FOR PROVIDING TEXT SELECTION - A method for providing selection of a portion of text for touch screen devices may include receiving an indication of a touch gesture in association with a primary word among text being displayed at a touch screen display, causing provision of a selected word indication to indicate inclusion of the primary word as a selected word, causing provision of a pre-selected word indication in relation to at least one secondary word adjacent to the primary word, and enabling expansion of the selected word indication to include the at least one secondary word in response to a touch event selecting the at least one secondary word. A corresponding apparatus and computer program product are also provided. | 04-26-2012 |
20120198343 | METHOD AND APPARATUS FOR REPRESENTING CONTENT DATA - An approach is provided for representing content data. The cleanup manager determines one or more data types of content associated with a device. Next, the cleanup manager determines effect information regarding one or more effects on one or more resources of the device with respect to the one or more data types. Then, the cleanup manager presents one or more representations of the one or more data types, wherein the one or more representations are based, at least in part, on the effect information. | 08-02-2012 |
20120253894 | METHOD AND APPARATUS FOR PROVIDING TAG-BASED CONTENT INSTALLATION - An approach is provided for providing tag-based content installation. The content manager causes, at least in part, reading of tag information from one or more memory tags, the one or more memory tags compliant with at least one protocol for automated content installation. Next, the content manager processes and/or facilitates a processing of the tag information to determine at least one link to one or more content items. Then, the content manager causes, at least in part, retrieval, installation, or a combination thereof of the one or more content items according to the at least one protocol. | 10-04-2012 |