Patent application number | Description | Published |
20090013155 | System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor - An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array. | 01-08-2009 |
20090016428 | METHOD AND APPARATUS FOR DECODING OF VIDEO SIGNALS HAVING REDUCED MEMORY AND A NOVEL METHOD FOR OUTPUT THEREFORE - A method and apparatus for in mobile communication systems, wherein the display image size is less than that of in the home entertainment purpose, are provided. Instead of using the high definition video decoding from incoming bit stream to the memory and the display for any size video display, the image is scaled during the decoding process to save the memory size and memory access bandwidth at a macro-block level. As the result, the power consumption involved will be substantially reduced, and the reduce display optimized. | 01-15-2009 |
20090019068 | DECODER WITH REDUCED MEMORY REQUIREMENTS DECODING OF VIDEO SIGNALS - A decoder decoding at a block level provided. The decoder comprises: a down-scalar receiving a multiplicity of blocks of data and down-scaling the blocks of data at the block level and storing the down-scaled data in a memory; and an output device for outputting the down-scaled blocks of data at the block level. | 01-15-2009 |
20090019261 | High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution - A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order. | 01-15-2009 |
20090158014 | System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor - An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations. | 06-18-2009 |
20090217001 | System and Method for Handling Load and/or Store Operations in a Superscalar Microprocessor - The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data. | 08-27-2009 |
Patent application number | Description | Published |
20080263556 | REAL-TIME SYSTEM EXCEPTION MONITORING TOOL - Techniques for monitoring resources of a computer system are provided. A monitoring process collects and reports utilization data for one or more resources of a computer system, such as CPU, memory, disk I/O, and network I/O. Instead of reporting just an average of the collected data over a period of time (e.g., 10 seconds), the monitoring process at least reports individually collected resource utilization values. If one or more of the utilization values exceed specified thresholds for the respective resources, then an alert may be generated. In one approach, the monitoring process is made a real-time priority process in the computer system to ensure that the memory used by the monitoring process is not swapped out of memory. Also, being a real-time priority process ensures that the monitoring process obtains a CPU in order collect resource utilization data even when the computer system is in a starvation mode. | 10-23-2008 |
20100211959 | ADAPTIVE CLUSTER TIMER MANAGER - Described herein are techniques for adaptively managing timers that are used in various layers of a node. In many cases, the number of timers that occur in the system is reduced by proactively and reactively adjusting values of the timers based on conditions affecting the system, thereby making such a system to perform significantly better and more resiliently than otherwise. | 08-19-2010 |
20110099412 | CLUSTER NEIGHBORHOOD EVENT ADVISORY - Database server instances in a database server cluster broadcast, to other instances in the cluster, information concerning certain problem events. Because each server instance is aware of problems that other server instances are experiencing, each server instance is enabled to make more intelligent decisions regarding the actions that it should perform in response to the problems that the server instance is experiencing. Instead of terminating itself, a server instance might opt to wait for a longer amount of time for an operation to complete. The server instance may do so due to the server instance having received information that indicates that other server instances are experiencing similar problems. Whenever the information received from other server instances makes it appear that a problem is unlikely to be solved in the cluster as a whole by terminating a server instance, that server instance may continue to wait instead of terminating itself. | 04-28-2011 |
20130185270 | LOCK ACCELERATION - A method for locking resources, including: receiving, by an accelerator, a first request from a first client to lock a first resource; evaluating, by a computer processor of a server, a hash function using an identifier of the first resource as an input to the hash function; identifying, by the computer processor and based on evaluating the hash function, a first hash bucket in a shared memory residing in a physical memory of the server; detecting that the first hash bucket is occupied; and sending the first request to a master lock monitor residing in a user space of the server based at least on detecting that the first hash bucket is occupied. | 07-18-2013 |