Patent application number | Description | Published |
20100247514 | GAMMA SECRETASE MODULATORS - In its many embodiments, the present invention provides a novel class of heterocyclic compounds as modulators of gamma secretase, methods of preparing such compounds, pharmaceutical compositions containing one or more such compounds, methods of preparing pharmaceutical formulations comprising one or more such compounds, and methods of treatment, prevention, inhibition, or amelioration of one or more diseases associated with the central nervous system using such compounds or pharmaceutical compositions. | 09-30-2010 |
20110110948 | BENZENESULFONYL-CHROMANE, THIOCHROMANE, TETRAHYDRONAPHTHALENE AND RELATED GAMMA SECRETASE INHIBITORS - Disclosed are novel gamma secretase inhibitors of the formula (I): or a pharmaceutically acceptable salt, solvate, or ester thereof, wherein L | 05-12-2011 |
20110257156 | GAMMA SECRETASE MODULATORS - In its many embodiments, the present invention provides novel heterocyclic compounds as modulators of gamma secretase, methods of preparing such compounds, pharmaceutical compositions containing one or more such compounds, methods of preparing pharmaceutical formulations comprising one or more such compounds, and methods of treatment, prevention, inhibition, or amelioration of one or more diseases associated with the central nervous system using such compounds or pharmaceutical compositions. | 10-20-2011 |
20110294784 | GAMMA SECRETASE MODULATORS - This invention provides novel compounds that are modulators of gamma secretase. The compounds have the formula (Chemical formula should be inserted here as it appears on abstract in paper form). Also disclosed are methods of modulating gamma secretase activity and methods of treating Alzheimer's Disease using the compounds of formula (I). | 12-01-2011 |
20120107328 | GAMMA SECRETASE MODULATORS - This invention provides novel compounds that are modulators of gamma secretase. The compounds have the formula (I). Also disclosed are methods of modulating gamma secretase activity and methods of treating Alzheimer's Disease using the compounds of formula (I). | 05-03-2012 |
20120135980 | GAMMA SECRETASE MODULATORS - This invention provides novel compounds that are modulators of gamma secretase. The compounds have the formula (Chemical formula should be inserted here as it appears on abstract in paper form). Also disclosed are methods of modulating gamma secretase activity and methods of treating Alzheimer's Disease using the compounds of formula (I). | 05-31-2012 |
20120264736 | BENZENESULFONYL-CHROMANE, THIOCHROMANE, TETRAHYDRONAPHTHALENE AND RELATED GAMMA SECRETASE INHIBITORS - This invention discloses novel gamma secretase inhibitors of the formula: | 10-18-2012 |
20140200213 | 2-SPIRO-SUBSTITUTED IMINOTHIAZINES AND THEIR MONO-AND DIOXIDES AS BACE INHIBITORS, COMPOSITIONS AND THEIR USE - In its many embodiments, the present invention provides certain iminothiazine dioxide compounds, including compounds Formula (I): | 07-17-2014 |
Patent application number | Description | Published |
20130007507 | MECHANISM FOR ADVANCED SERVER MACHINE CHECK RECOVERY AND ASSOCIATED SYSTEM SOFTWARE ENHANCEMENTS - Embodiments of a hardware processor including a plurality of machine state registers (MSRs) are described. At least one of the MSRs includes an erroring logical processing (ELP) bit which when set, indicates that a particular thread executing on the hardware processor caused an error. | 01-03-2013 |
20130151930 | Injecting A Data Error Into A Writeback Path To Memory - In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed. | 06-13-2013 |
20130275810 | METHOD AND APPARATUS FOR INJECTING ERRORS INTO MEMORY - Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory. | 10-17-2013 |
20130339829 | Machine Check Summary Register - In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view. | 12-19-2013 |
20140223226 | APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS - An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage. | 08-07-2014 |
20140237299 | SECURE ERROR HANDLING - Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed. | 08-21-2014 |
20140298140 | APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY - An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. | 10-02-2014 |
20150089280 | RECOVERY FROM MULTIPLE DATA ERRORS - Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process. | 03-26-2015 |