Patent application number | Description | Published |
20090015535 | DRIVING CIRCUIT FOR A LIQUID CRYSTAL DISPLAY - Provided is a driving circuit for a liquid crystal display which is suitable for reducing a chip size and has improved noise immunity in a circuit which uses a level shifter and is constructed with a channel array. The driving circuit includes: the level shifter which is disposed in a previous stage of a channel region and shifts up a level of a data signal output from a buffer to output the data signal to the channel region; and the channel region which processes an output data of the level shifter in a format requested by a system and outputs a final data in a high or low format, and wherein the level shifter is disposed in a region excluding the channel region. | 01-15-2009 |
20100027223 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING HEAT RELEASE PATTERN - Provided are a semiconductor integrated circuit having a heat release pattern in a chip so as to release heat generated inside the chip and a system board having a heat release unit used to release heat generated inside the semiconductor integrated circuit. The semiconductor integrated circuit includes: one or more output pads directly connected to an output terminal having a heat release pattern; a power supply pad supplying power; and one or more dummy pads connected to a metal line for supplying power or an internal output terminal of an internal function block, wherein the heat release pattern includes a plurality of unit contacts at the output terminal or a plurality of strip contacts having an area of about or larger than the sum of two or more of the unit contacts. | 02-04-2010 |
20100118024 | METHOD FOR REMOVING OFFSET BETWEEN CHANNELS OF LCD PANEL - A method of removing offsets between channels of a liquid crystal panel is provided. The method includes: alternately arranging first type output buffers and second type output buffers for driving the pixels in units of at least two rows of the pixels; and arranging the first type output buffers and the second type output buffers in units of at least two columns of the pixels so that the output buffers with types opposite to those of previous two columns are arranged. The second type output buffers are embodied by switching connections among the differential transistors and connections among the load transistors in the first type output buffers. | 05-13-2010 |
20100141687 | METHOD OF ARRANGING GAMMA BUFFERS AND FLAT PANEL DISPLAY APPLYING THE METHOD - Provided are a method of arranging gamma buffers capable of decreasing a Kelvin of a source driver included in a flat panel display and minimizing a temperature deviation between source drivers, and the flat panel display applying the method. The method of arranging a plurality of gamma buffers which are arranged in one or more source drivers to output corresponding gamma voltages, includes a step of calculating power consumptions of the gamma buffers, wherein the method further comprises one or more steps of: changing tab points of the gamma buffers by using the calculated power consumptions of the gamma buffers; and changing positions of the gamma buffers by using the calculated power consumptions of the gamma buffers. | 06-10-2010 |
20100155957 | PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP - Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides. | 06-24-2010 |
20100246077 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE OF OUTPUT DRIVER STAGE - Provided is an electrostatic discharge (ESD) protection device of an output driver stage of a semiconductor chip. The ESD protection device of an output driver stage, which includes a p-channel metal-oxide-semiconductor (PMOS) transistor having a source connected to a first source voltage and an n-channel metal-oxide-semiconductor (NMOS) transistor having a source connected to a second source voltage, the MOS transistors having gates applied with output signals from an internal circuit and drains connected to the output pad, wherein a distance between contacts formed on a drain region and a gate poly of the MOS transistors is relatively greater than a value according to a predetermined design rule. | 09-30-2010 |
20100259564 | DISPLAY DRIVING INTEGRATED CIRCUIT AND DISPLAY DRIVING SYSTEM - Provided is a high-resolution display driving system without a new design of interfaces between a timing controller and DDIs, particularly, without an entire change of a DAC unit having a role of determining gradation representation of DDIs and offsets between channels. The high-resolution display driving system includes a timing controller and a DDI unit. The timing controller generates a differential clock signal and differential data. The DDI unit generates a plurality of converted signals corresponding to the differential data in response to an operation instructing signal, a reset/enable signal, and the differential clock signal. A scheme of data transmission from the timing controller to the DDI unit is at least one of a multi-drop scheme and an m-LVDS (mini low voltage differential signaling) scheme. | 10-14-2010 |
20100265274 | OFFSET COMPENSATION GAMMA BUFFER AND GRAY SCALE VOLTAGE GENERATION CIRCUIT USING THE SAME - Disclosed are an offset compensation gamma buffer and a gray scale voltage generation circuit using the same. The offset compensation gamma buffer includes: a buffer which outputs an input voltage input to a positive or negative input terminal as an output voltage; and a switching unit which selectively connects the input voltage and the output voltage of the buffer to the positive and negative input terminals in response to a control signal. The output voltage of the offset compensation gamma buffer is supplied to the input of a gray scale voltage generation circuit of a source driver for driving a liquid crystal panel. The offset of the offset compensation gamma buffer is compensated using an inversion timing of the control signal. The output voltage of the offset compensation gamma buffer is supplied as a reference voltage of the voltage divider unit for generating the gray scale voltages, and the offset of the gray scale voltages is also compensated. | 10-21-2010 |
20100308472 | SEMICONDUCTOR CHIP HAVING POWER SUPPLY LINE WITH MINIMIZED VOLTAGE DROP - Disclosed is a power supply line in which a voltage drop generated in a resistance component of a metal line which delivers a power voltage is minimized so that the level of the power supply voltage delivered to a semiconductor chip becomes constant in the entire area of the semiconductor chip. The semiconductor chip includes: at least two power supply pads to which a power voltage applied from an external unit of the semiconductor chip is supplied; power supply main metal lines connected to each of the power supply pads; power supply branch metal lines extended from each of the power supply main metal lines to deliver a power voltage to a circuit in the semiconductor chip; and at least an electrostatic discharge (ESD) improvement dummy pad, wherein the ESD improvement dummy pad is electrically connected to the corresponding power supply main metal line and the corresponding power supply branch metal line to minimize a voltage drop. | 12-09-2010 |
20110089576 | PAD LAYOUT STRUCTURE OF A DRIVER IC CHIP - A pad layout structure of a driver IC chip to be mounted to a liquid crystal display panel. The pad layout structure includes power pad sections placed at respective four corners of the driver IC chip and each having a first power pad for supplying first power to the driver IC chip, a second power pad for supplying second power to the driver IC chip, a third power pad for supplying third power to the driver IC chip and a fourth power pad for supplying fourth power to the driver IC chip. | 04-21-2011 |
20110096054 | LIQUID CRYSTAL DISPLAY PANEL DRIVING CIRCUIT - Disclosed is a liquid crystal display panel driving circuit for driving a liquid crystal display panel with a resolution of N bits. N-bit digital data including upper X bits and lower Y bits is inputted. The liquid crystal display panel driving circuit includes a resistor string unit according to areas, a DAC converter switching unit according to areas, and an interpolation amplifier. The resistor string unit outputs analog reference voltages at different ratios according to three areas. The DAC converter switching unit receives the N-bit digital data, selects (Y+1) analog voltages from the analog reference voltages based on the upper X bits, outputs the (Y+1) analog voltages, and outputs the (Y+1) analog voltages of different combinations based on the lower Y bits. The interpolation amplifier receives the (Y+1) analog voltages and generates an interpolated output voltage by setting weights for the (Y+1) analog voltages by using multi-factors. | 04-28-2011 |
20110102408 | LAYOUT OF LCD DRIVING CIRCUIT - A layout of a liquid crystal display driving circuit is capable of minimizing an area which the layout occupies. The layout of the liquid crystal display driving circuit transmits positive analog voltages and negative analog voltages to a liquid crystal display, and includes a digital-to-analog converter (DAC) block and a buffer block. The DAC block has N/2 positive DACs generating the respective positive analog voltages corresponding to corresponding digital data using a positive reference voltage, where N is the integer, and N/2 negative DACs generating the respective negative analog voltages corresponding to corresponding digital data using a negative reference voltage. The buffer block has N/2 positive and negative buffers, which buffer the N/2 positive and negative analog voltages, and are alternately arranged. The N/2 positive and negative DACs are divided into groups one by one or in twos or more, and the groups are alternately arranged. | 05-05-2011 |
20110102410 | CIRCUIT AND METHOD FOR DRIVING OLED DISPLAY - A circuit for driving an organic light emitting diode display includes a display panel that displays an image by using organic light emitting diodes disposed at intersection areas of a plurality of gate lines and a plurality of data lines; a threshold voltage detection control unit that supplies a precharge voltage by sequentially turning on transistors for threshold voltage detection, which are connected among the data lines and the organic light emitting diodes on the display panel, in units of horizontal lines, and enables threshold voltages to be detected; and a source driver that detects threshold voltages of all organic light emitting diodes arranged on a corresponding horizontal line, and repeats an operation, as necessary, for sampling/holding the detected threshold voltages through M sample/hold circuits, converting the sampled/held threshold voltages into digital signals, and storing the digital signals in a memory. | 05-05-2011 |
20110102687 | LCM FOR A DISPLAY PANEL - An LCM for a display panel includes a pixel array, a plurality of source driver ICs, and a plurality of gate driver ICs. The plurality of source driver ICs are disposed in a horizontal direction at an upper side or lower side of the pixel array. The plurality of gate driver ICs are disposed in a vertical direction at a left side or right side of the pixel array. The plurality of gate driver ICs are disposed at an opposite position to a position where a source driver IC, among the plurality of source driver ICs, first supplied with video data and a clock signal is disposed. | 05-05-2011 |
20110109816 | CIRCUIT FOR DRIVING LCD DEVICE AND DRIVING METHOD THEREOF - A liquid crystal display driving circuit and method. A data register block of a controller applies in advance a polarity control signal to data before the data are stored in latches of a data driver, exchanges the data, and then stores the exchanged data in the latches. Thereby, it is possible to provide multiplexers, which are otherwise required for respective channels, to one controller and to decrease the size of a chip. | 05-12-2011 |
20110164006 | DISPLAY DRIVE CIRCUIT - A display driving circuit includes a buffer section, an N-dot switch circuit, a charge sharing switch circuit, and a sharing voltage level control switch circuit. The buffer section buffers a plurality of pixel driving signals outputted from a plurality of DACs. The N-dot switch circuit selects paths of the plurality of pixel driving signals outputted from the buffer section in response to a first path selecting signal or a second path selecting signal that is determined depending upon a dot inversion method, and switches the paths to a plurality of output terminals. The charge sharing switch circuit shares charges among the plurality of output terminals in response to a charge sharing control signal. The sharing voltage level control switch circuit controls charge sharing between the plurality of output terminals and a voltage level upon charge sharing, in response to a sharing voltage level control signal. | 07-07-2011 |
20110164020 | DISPLAY DRIVE CIRCUIT AND DRIVE METHOD - A display driving circuit and method is capable of minimizing the residual image of a display panel as well as consumption electric current. The display driving circuit generates driving signals corresponding to valid data and black data and transmits the driving signals to a display panel, and includes N data selection switches (where N is the integer), N buffers, N buffer output selection switches, and multiple charge sharing switches. The N data selection switches select one of the valid data and the black data. The N buffers buffer the signal selected by the respective data selection switches. The N buffer output selection switches switch outputs of the buffers to output the respective driving signals. The multiple charge sharing switches connect the neighboring pairs of the driving signals. | 07-07-2011 |
20110169808 | AMPLIFIER INCLUDING DITHERING SWITCH AND DISPLAY DRIVING CIRCUIT USING THE AMPLIFIER - An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other. | 07-14-2011 |
20110199821 | POWER MANAGEMENT CHIP FURNISHED WITH VOLTAGE CONTROLLER - A power management IC includes a first IC having a boost converter IC which generates a second voltage using a first voltage supplied from an outside and supplies the second voltages to a charge pump, a reference voltage generation circuit, and an EEPROM; and a second IC configured to be inputted with a third voltage and a fourth voltage as outputs of the charge pump and output a fifth voltage and a sixth voltage. The second IC has a voltage regulator which regulates the third voltage and the fourth voltage or the fifth voltage and the sixth voltage and generates an eighth voltage and a ninth voltage as voltages required for programming operation or erasing operation of the EEPROM. | 08-18-2011 |
20110298769 | LIQUID CRYSTAL DISPLAY DRIVING CIRCUIT WITH LESS CURRENT CONSUMPTION - An LCD driving circuit includes a first buffer configured to have a terminal for a first voltage, a terminal for a second voltage and a terminal for an intermediate voltage between the first voltage and the second voltage, and be driven in a range from the first voltage to the intermediate voltage; and a second buffer configured to have a terminal for the first voltage, a terminal for the second voltage and a terminal for the intermediate voltage, and be driven in a range from the intermediate voltage to the second voltage. The terminal for the intermediate voltage of the first buffer and the terminal for the intermediate voltage of the second buffer are connected with each other, and the first voltage is a highest voltage, the second voltage is a lowest voltage, and the intermediate voltage is in a range from the first voltage to the second voltage. | 12-08-2011 |
20120044227 | POWER SUPPLY CIRCUIT FOR LIQUID CRYSTAL DISPLAY DEVICE - A power supply circuit of a liquid crystal display device includes a first positive polarity charge charging unit including a first capacitor connected to positive and negative power terminals through switches to charge a charge, a second positive polarity charge charging unit including a second capacitor connected to the positive power terminal and a ground terminal through switches to charge a charge, a first positive polarity charge loading unit loading the charge supplied through the positive power terminal to a negative polarity terminal, a second positive polarity charge loading unit loading the charge charged in the first capacitor to a negative polarity terminal, a third positive polarity charge loading unit loading the charge charged in the second capacitor, and a positive polarity charge charging/loading control unit outputting charging control signals with a same phase to the switches, and periodically or irregularly changing durations of the charging and loading control signals. | 02-23-2012 |
20120169701 | READOUT INTEGRATED CIRCUIT FOR A TOUCH SCREEN - A readout integrated circuit (ROIC) for a touch screen, the readout integrated circuit includes: a touch sensor unit configured to include a plurality of touch sensors which are arranged in a matrix form having rows and columns in an inside or outside of a touch screen panel (TSP); a plurality of sensing blocks configured to sense an electrical change in each of the touch sensors, to convert the electrical change into a voltage value, and to store the voltage value; a delta circuit unit configured to receive a difference between two sensing voltage values stored in two sensing blocks, respectively, which are spaced by a predetermined distance and selected from among the plurality of sensing blocks, and to produce a delta (Ī) voltage; and an analog-to-digital converter configured to convert an analog signal output from the delta circuit unit into an N-bit digital signal (wherein, āNā is a natural number). | 07-05-2012 |
20120292776 | PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP - Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides. | 11-22-2012 |
20120299903 | SOURCE DRIVER CIRCUIT OF LIQUID CRYSTAL DISPLAY DEVICE - Provided is a technology for preventing noisy data from being displayed before valid data is inputted when power is turned on in a liquid crystal display. A source driver circuit for a liquid crystal display includes: a power supply voltage input unit configured to divide a first power supply voltage and a second power supply voltage, such that a middle level of the second power supply voltage is lower than a level of the first power supply voltage; a power supply voltage comparison unit configured to compare division voltages inputted from the power supply voltage input unit, and output an output voltage of a high level in a time period in which the middle level of the second power supply voltage is higher than the level of the first power supply voltage; a Schmitt trigger configured to output the output voltage of the power supply voltage comparison unit as a reset signal while preventing a sensitive response to external environment; and a specific voltage supply unit configured to output a voltage of a specific level in a time period between the input of the reset signal from the Schmitt trigger and the input of a first gate start pulse. | 11-29-2012 |
20130244529 | METHOD FOR ROUTING GAMMA VOLTAGES IN FLAT PANEL DISPLAY - A method for routing gamma voltages in a flat panel display that includes a plurality of source driver integrated circuits (SDICs) each having a plurality of gamma buffers. The method includes forming routing lines to route a plurality of gamma voltages; connecting the routing lines to output terminals of the gamma buffers; applying the reset gamma voltage to the gamma buffer of selected SDIC after selecting the SDIC in which the gamma voltage is required to be reset in consideration of heating values of the SDICs, and changing connection between a routing line corresponding to the selected gamma buffer and a tap point of a resistor string of the SDIC such that the connection corresponds to the reset gamma voltage. | 09-19-2013 |
20130335123 | DRIVER IC CHIP AND PAD LAYOUT METHOD THEREOF - Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique. | 12-19-2013 |