Patent application number | Description | Published |
20080248649 | First inter-layer dielectric stack for non-volatile memory - A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer ( | 10-09-2008 |
20080254617 | Void-free contact plug - A semiconductor device manufacturing process for forming a contact plug includes sequentially depositing a titanium or tantalum contact layer ( | 10-16-2008 |
20090142895 | METHOD OF FORMING A VIA - A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region. | 06-04-2009 |
20090218625 | Modified Hybrid Orientation Technology - A semiconductor process and apparatus includes forming first and second metal gate electrodes ( | 09-03-2009 |
20100035434 | PLASMA TREATMENT OF A SEMICONDUCTOR SURFACE FOR ENHANCED NUCLEATION OF A METAL-CONTAINING LAYER - A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of | 02-11-2010 |
20100081290 | METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA - A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer. | 04-01-2010 |
20100090287 | ELECTRONIC DEVICE WITH A GATE ELECTRODE HAVING AT LEAST TWO PORTIONS - A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure. | 04-15-2010 |
20110294292 | METHOD OF FORMING A SHARED CONTACT IN A SEMICONDUCTOR DEVICE - A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material. | 12-01-2011 |