Patent application number | Description | Published |
20090161210 | MICROSCOPY SYSTEM WITH REVOLVABLE STAGE - A microscopy system includes an objective lens and a stage for holding a sample. The objective lens focuses incident light coming from one side of the objective lens to the sample disposed on the other side of the objective lens, and focuses an optical signal emitted from the sample to a photosensor disposed on the one side of the objective lens. The stage supports the sample and is configured to be revolvable about an axis, which is substantially perpendicular to an extending direction from the sample to the objective lens. | 06-25-2009 |
20090162246 | SAMPLE CARRYING APPARATUS CAPABLE OF REVOLVING SAMPLE - A sample carrying apparatus capable of revolving a sample includes a body and a revolvable structure. The body has a slot. The revolvable structure partially accommodated within the slot is pivotally connected to the body and is revolvable relative to the body. | 06-25-2009 |
20120081518 | METHOD FOR 3-DIMENSIONAL MICROSCOPIC VISUALIZATION OF THICK BIOLOGICAL TISSUES - The present invention discloses a method of visualizing the 3-dimensional microstructure of a thick biological tissue. This method includes: a process of immersing thick, opaque biological tissues in the optical-clearing solution, for example FocusClear (U.S. Pat. No. 6,472,216), and utilizing an optical scanning microscope and a cutter. In microscopy, the cutter removes a portion of the tissue after each round of optical scanning. Each round of optical scanning follows the principal that the depth of the removal plane is less than the depth of the boundary plane derived from the scanning This method acquires an image stack to provide the information of thick biological tissue's 3-dimensional microstructure with minimal interference by the tissue removal. | 04-05-2012 |
Patent application number | Description | Published |
20080301497 | Testing Apparatus, System, and Method for Testing at Least One Device with a Connection Interface - A system, a testing apparatus, and a method for testing at least one device with a connection interface are provided. The system comprises a host, a testing apparatus, and a power supply. The testing apparatus further comprises a microprocessor and at least one current limit module. The host sending a test signal. The power supply provides a voltage to the testing apparatus. The at least one current limit module of the testing apparatus, which is electrically connected to the microprocessor, the at least one device, and the power supply, provides the voltage to the at least one device. When the current passing through the at least one device is greater than the predetermined value, the at least one current limit module of the testing apparatus stops providing the voltage to the at least one device and sends an over current signal to the host via the microprocessor. | 12-04-2008 |
20090300753 | METHOD FOR PREVENTING DATA IN A COMPUTER SYSTEM FROM BEING ACCESSED BY UNAUTHORIZED USER - A computer system is provided comprising a non-volatile storage medium and a processor. The processor acquires authentication information from a first removable storage device, stores the authentication information into the non-volatile storage medium, and forbids data access of the computer system when detecting that a second removable storage device has been inserted and identification data of the second removable storage device is different from the authentication information. | 12-03-2009 |
20100241768 | METHOD FOR CONTROLLING ICON DISPLAY CORRESPONDING TO A USB MASS STORAGE, ASSOCIATED PERSONAL COMPUTER, AND STORAGE MEDIUM STORING AN ASSOCIATED USB MASS STORAGE DRIVER - A method for controlling icon display corresponding to a Universal Serial Bus (USB) Mass Storage is provided. The USB Mass Storage is electrically connected to a USB port of a personal computer. The method includes: when it is detected that there is nothing inserted into any memory card slot of the USB Mass Storage, preventing the USB Mass Storage from triggering a specific icon to be displayed, wherein the specific icon is selectively utilized for indicating that at least one USB device is electrically connected to the personal computer; and when it is detected that a memory card is inserted into any of at least one memory card slot of the USB Mass Storage, allowing the specific icon to be displayed. An associated personal computer and a storage medium storing an associated USB Mass Storage driver for controlling icon display corresponding to the USB Mass Storage are further provided. | 09-23-2010 |
20100241883 | METHOD FOR CONTROLLING POWER CONSUMPTION OF A USB MASS STORAGE, ASSOCIATED PERSONAL COMPUTER, AND STORAGE MEDIUM STORING AN ASSOCIATED USB MASS STORAGE DRIVER - A method for controlling power consumption of a Universal Serial Bus (USB) Mass Storage is provided. The USB Mass Storage is electrically connected to a USB port. The method includes: monitoring at least one Test Unit Ready (TUR) command from an operating system (OS) to the USB Mass Storage; and when it is detected that there is no other command from the OS to the USB Mass Storage for a predetermined time period, controlling the USB port to enter a suspend mode in order to save power supplied to the USB Mass Storage. An associated personal computer and a storage medium storing an associated USB Mass Storage driver for controlling power consumption of the USB Mass Storage are further provided, where the personal computer includes the storage medium. In particular, when the USB Mass Storage driver is executed by the personal computer, the personal computer operates according to the method. | 09-23-2010 |
20110060858 | METHOD FOR ENHANCING PERFORMANCE OF DATA ACCESS BETWEEN A PERSONAL COMPUTER AND A USB MASS STORAGE, ASSOCIATED PERSONAL COMPUTER, AND STORAGE MEDIUM STORING AN ASSOCIATED USB MASS STORAGE DRIVER - A method for enhancing performance of data access between a personal computer and a USB Mass Storage is provided. The personal computer is equipped with a plurality of layers of drivers regarding USB data access, and a lower layer of the layers of the drivers includes a USB Bus Driver. The method includes: monitoring commands sent from an operating system (OS) file system to an upper layer; and when a command sent from the OS file system to the upper layer is utilized for accessing data of a data amount that is greater than a predetermined threshold value, omitting a portion of a plurality of IRPs, automatically generating a plurality of replies for replying to the omitted IRPs, and altering at least one IRP of remaining IRPs in order to correctly access the data with a lower IRP count, wherein the plurality of IRPs is associated with the command. | 03-10-2011 |
Patent application number | Description | Published |
20090245780 | Shutter device - A shutter device comprises a base, two electromagnetic valves, two blades, and a cover plate. A first light hole is formed in the center of base. The electromagnetic valve comprises a magnetic core, a coil unit, and a magnetic part. The magnetic cores and coil units are on the base, being axially symmetrical at the periphery of first light hole of the base. The blades join with the corresponding magnetic parts of the electromagnetic valves, in which each of the blades may travel between first and second positions at a degree of freedom to open or shut the first light hole through which rays of light pass. The cover plate is assembled onto the base and provided with a second light hole corresponding to the first light hole. The two magnetic cores are axially symmetrical on the base and lie at the periphery of first light hole. | 10-01-2009 |
20110116783 | MAGNET ARRAY MEMBER WITH MORE THAN FOUR POLES AND SHUTTER - A magnet array member with more than four poles is used for being mounted on a shutter of a camera module of a portable mobile communication device, adjacent to one side of a yoke iron of the shutter. The magnet array member includes a disc portion and a driving portion. The disc portion has more than four N poles and S poles, and an annular side face and opposite first end face and second end face. The driving portion protrudes from one of the first end face and the second end face of the disc portion in a vertical direction. Since the driving portion protrudes from one end face of the disc portion, the disc portion can form more than four N poles and S poles when magnetized, thereby being convenient for mass production. | 05-19-2011 |
Patent application number | Description | Published |
20090011545 | CHIP PACKAGE PROCESS - The present invention further provides a chip package process, which includes providing a substrate, disposing a chip on the substrate and forming a buffering compound on the substrate and the chip, wherein the buffering compound covers the chip. The present invention further provides another chip package process, which includes providing a substrate, forming a buffering compound on the substrate and disposing a chip in the buffering compound. | 01-08-2009 |
20100047965 | FABRICATING METHOD OF PACKAGING STRUCTURE - A fabricating method of packaging structure is provided. First, a capacitive element is formed. Then, a first dielectric layer is formed on a first electronic component by performing a build-up process, an interconnection is formed in the first dielectric layer, and a plurality of contacts are formed on the upper and lower surfaces of the first dielectric layer, wherein the capacitive element is embedded in the first dielectric layer during the fabrication of the interconnection and the capacitive element is electrically connected to the corresponding contacts through the interconnection. A second electronic component is disposed on the first dielectric layer, wherein the second electronic component is electrically connected to the corresponding contacts. | 02-25-2010 |
Patent application number | Description | Published |
20080248638 | PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR - The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential. | 10-09-2008 |
20100038677 | Semiconductor device for electrostatic discharge protection - A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also has an anode and a cathode. The anode of the diode is coupled to the anode of the HVSCR, and the cathode of the diode is coupled to a terminal applied with a positive voltage. The diode has a second conductivity type zone that could be constructed to form several strips or small blocks spaced apart from each other. Those small blocks could be any shapes and arranged regularly or randomly. | 02-18-2010 |
20100091420 | CONTROL CIRCUIT WITH PROTECTION CIRCUIT FOR POWER SUPPLY - A control circuit with protection circuit for power supply according to the present invention comprises a peak-detection circuit and a protection circuit. The peak-detection circuit detects an AC input voltage and generates a peak-detection signal. The protection circuit generates a reset signal to reduce the output of the power supply in response to the peak-detection signal. The present invention can protect the power supply in response to the AC input voltage effectively through the peak-detection circuit. | 04-15-2010 |
Patent application number | Description | Published |
20100230749 | SEMICONDUCTOR DEVICES AND FORMATION METHODS THEREOF - A semiconductor device is provided and includes a substrate of a first conductivity type, a deep well of a second conductivity type, and a first high-side device. The deep well is formed on the substrate. The first high-side device is disposed within the deep well and includes an insulation layer of the second conductivity type, a well of the first conductivity type, first and second regions of the second conductivity type, and a first poly-silicon material. The insulation layer is formed on the substrate. The well is formed within the deep well. The first and second regions are formed within the well. The first poly-silicon material is disposed between the first region and the second region and on the deep well. | 09-16-2010 |
20110180858 | Semiconductor Device - A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. Wherein the first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second drain electrode of the JFET respectively. | 07-28-2011 |
20110180878 | High Side Semiconductor Structure - A high side semiconductor structure is provided. The high side semiconductor structure includes a substrate, a first deep well, a second deep well, a first active element, a second active element and a doped well. The first deep well and the second deep well are formed in the substrate, wherein the first deep well and the second deep well have identical type of ion doping. The first active element and the second active element are respectively formed in the first deep well and the second deep well. The doped well is formed in the substrate and is disposed between the first deep well and the second deep well. The doped well, the first deep well and the second deep well are interspaced, and the type of ion doping of the first deep well and the second deep well is complementary with that of the doped well. | 07-28-2011 |
20110260291 | Semiconductor Structure - A semiconductor structure. The semiconductor comprises a substrate, a first deep well, a diode and a transistor. The first deep well is formed in the substrate. The diode is formed in the first deep well. The transistor is formed in the first deep well. The diode is connected to a first voltage, the transistor is connected to a second voltage, and the diode and the transistor are cascaded. | 10-27-2011 |
20120249220 | Trim Circuit for Power Supply Controller - A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection. | 10-04-2012 |
Patent application number | Description | Published |
20090158763 | REFRIGERANT FLOATING EXPANSION APPARATUS - A refrigerant floating expansion apparatus including a main body, a standpipe, a float element and a separation element is provided. The main body includes a base plate and a pipe-shaped housing. The standpipe fixed on the base plate has a second pipe opening and a third pipe opening. The pipe wall of the standpipe has at least an opening near the second pipe opening. The float element surrounds the standpipe for controlling a fluid-passing area of the opening. The separation element surrounding the float element is disposed on the base plate and forms an inner path with the pipe-shaped housing. The separation element has several fluid passageways near the base plate. A high-pressure fluid entering the main body is guided to pass through the fluid passageways to move the float element for controlling the fluid-passing area of the opening. Then, the high-pressure fluid is transferred to a low-pressure fluid. | 06-25-2009 |
20100211228 | METHOD AND SYSTEM FOR CONTROLLING COMPRESSOR - In the present invention, a method and a system for controlling a compressor are provided. The method includes the steps of: providing a condenser connected to the compressor, and at least one evaporator connected to the condenser; measuring an inlet pressure and an outlet pressure of the compressor to obtain a flow rate of the condensate; determining a secure flow rate and a demanding flow rate based on a total number of the at least one evaporator; comparing at least two of the flow rate, the demanding flow rate and the secure flow rate with each other to obtain a compared result; and controlling the compressor based on the comparing result. | 08-19-2010 |
20100229587 | AIR CONDITIONING SYSTEM - An air conditioning system includes a first circulation module and a second circulation module. Two circulation modules are joined by a heat exchanger. The first circulation is a modular refrigeration system includes a compressor, expansion device, and heat exchangers. The second circulation module includes a main liquid refrigerant tank, a number of distributed liquid refrigerant tanks, liquid pumps and a plurality of indoor units which includes a heat exchange device and a vapor propelling device. The heat exchange device is connected to the main liquid tank. The vapor propelling device propels the working fluid in a saturated vapor state to the first heat exchanger, thus forming a working fluid loop. It can be switched between the heating and cooling modes. | 09-16-2010 |
20120103571 | HEAT DISSIPATION STRUCTURE OF ELECTRONIC DEVICE - A structure of heat dissipation of an electronic device includes at least one heat pipe and a cooler. The heat pipe has a condensation end and an evaporation end opposite to each other, and the evaporation end is disposed on a heat generating element of the electronic device. The cooler is disposed on a rack and has a chamber therein, and the chamber has an inner shell having a cooling fluid therein. When the electronic device is mounted in the rack, the condensation end of the heat pipe is inserted into the cooler and positioned into the inner shell. The evaporation end absorbs the heat energy of the heat generating element, and transfers the heat energy to the condensation end, such that the cooling fluid dissipates the heat energy of the condensation end. | 05-03-2012 |
20120106073 | DATA CENTER MODULE - A module for data center is presented, which is used for heat sinking of a heat source. The module for data center includes a first chamber, a second chamber, and a heat pipe. The heat source is positioned in the first chamber. The second chamber is adjacent to the first chamber. In addition, the heat pipe has an evaporation end positioned inside the first chamber and a condensation end positioned inside the second chamber. The heat pipe absorbs the heat energy in the first chamber with the evaporation end, transfers the heat energy to the condensation end, and eliminates the heat energy with the condensation end. | 05-03-2012 |
20130182388 | DATA CENTER MODULE - A module for data center is presented, which is used for heat sinking of a heat source. The module for data center includes a first chamber, a second chamber, and a heat pipe. The heat source is positioned in the first chamber. The second chamber is adjacent to the first chamber. In addition, the heat pipe has an evaporation end positioned inside the first chamber and a condensation end positioned inside the second chamber. The heat pipe absorbs the heat energy in the first chamber with the evaporation end, transfers the heat energy to the condensation end, and eliminates the heat energy with the condensation end. | 07-18-2013 |
Patent application number | Description | Published |
20140018011 | DIRECT-CONVERSION TRANSCEIVER WITH DC OFFSET COMPENSATION AND THE OPERATION METHOD USING THE SAME - The present invention discloses a direct-conversion transceiver with dc offset compensation, and method using the same. The transceiver mainly comprises an antenna, a first filter, a second filter, a third filter, a first variable gain amplifier with multi-stages, a second variable gain amplifier with multi-stages, a first analog-to-digital converter, a second analog-to-digital converter, a first dc offset loop, a second dc offset loop, a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, a fourth digital-to-analog converter, a third mixer, a fourth mixer, a power amplifier, a local oscillator, and a baseband circuit. By using the second filters, the third filter, the first digital-to-analog converter and the second digital-to-analog converter for both in transmitting mode or receiving mode, the numbers of the filter and digital-to-analog converter can be reduced and thus the circuit area of the transceiver can be further miniaturized. | 01-16-2014 |
Patent application number | Description | Published |
20110006356 | NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME - A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the substrate, each of which includes a control gate and a gate dielectric layer. The control gates are disposed on the substrate, and two first spacers are deployed at both sides of each control gate. The gate dielectric layers are disposed between the control gates and the substrate, respectively. Each of the doped regions is formed in the substrate between two adjacent gate structures. The second spacers are disposed on the sidewalls of the gate structures. The contact plugs are formed between two adjacent second spacers, respectively. | 01-13-2011 |
20110053338 | FLASH MEMORY AND METHOD OF FABRICATING THE SAME - In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation structures in a periphery region and the isolation structure in a cell region adjacent to the periphery region. The isolation structures in the cell region not covered by the mask layer are partially removed. Therefore, a first height difference is between surfaces of the isolation structures in the periphery region and a surface of the dielectric layer, and between a surface of the isolation structure in the cell region adjacent to the periphery region and the surface of the dielectric layer. A second height difference smaller than the first height difference is between surfaces of other isolation structures in the cell region and the surface of the dielectric layer. | 03-03-2011 |
20110201170 | METHOD OF FABRICATING MEMORY - A method of fabricating a memory is provided. A substrate comprising a memory region and a periphery region is provided. A plurality of gates is formed on the substrate and a first spacer is formed on a sidewall of each gate, where a plurality of openings is formed between the gates in the memory region. A first material layer formed on the substrate in the memory region covers the gates in the memory region and fills the openings. A process is performed to the periphery region. The first material layer is partially removed to form a first pattern in each opening respectively. A second material layer formed on the substrate covers the memory region and the periphery region to expose the first patterns. The first patterns are removed to form a plurality of contact openings in the second material layer. The contact plugs are formed in the contact openings. | 08-18-2011 |
20130016560 | SEMICONDUCTOR MEMORY DEVICESAANM YANO; MasaruAACI TokyoAACO JPAAGP YANO; Masaru Tokyo JPAANM CHIANG; Lu-PingAACI Hsinchu CityAACO TWAAGP CHIANG; Lu-Ping Hsinchu City TW - A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well. | 01-17-2013 |
20130078775 | METHOD OF FABRICATING MEMORY - A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings. | 03-28-2013 |
20140063970 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE′ is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit | 03-06-2014 |
20140127905 | METHOD OF FORMING PATTERN IN SUBSTRATE - A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material. | 05-08-2014 |
Patent application number | Description | Published |
20090009242 | LINE DRIVER CAPABLE OF AUTOMATICALLY ADJUSTING OUTPUT IMPEDANCE - A line driver includes: a differential amplifier for amplifying an input signal to generate an output signal; first and second series resistors coupled respectively to output terminals of the differential amplifier and through which the output signal is output; first and second negative-feedback resistors each coupled between a respective input terminal and a respective output terminal of the differential amplifier; first and second positive-feedback variable resistors each coupled between a respective input terminal of the differential amplifier and a respective one of the first and second series resistors; and an adjusting unit coupled to the first and second positive-feedback variable resistors to adjust a resistance thereof with reference to the output signal. | 01-08-2009 |
20090167276 | Soft-Start Circuit and Method Thereof - A soft-start circuit and a method thereof are described. The circuit includes an amplifier and a voltage ramp generator. The amplifier has a first input end, a second input end, an output end, and a power source control end. The first input end is coupled to a reference voltage. The second input end is coupled to a feedback voltage. The output end outputs an output voltage, and the feedback voltage corresponds to the output voltage. The voltage ramp generator is coupled to the power source control end, and generates a ramp-up voltage. When the ramp-up voltage is lower than a threshold value, the output voltage rises with the ramp-up voltage. When the ramp-up voltage is not lower than the threshold voltage, the output voltage remains at a stable value. A surge current occurring during smooth soft-start or even in operation is thus prevented. | 07-02-2009 |
20090310395 | Content-Addressable Memory - A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, and compares the second data bit with a second search bit to determine if they are matched. The first CAM cell comprises a first logic circuit, the second CAM cell comprises a second logic circuit, and the first logic circuit and the second logic circuit form a static CMOS logic circuit. | 12-17-2009 |
20100067277 | Content-Addressable Memory - A CAM includes first and second memory units. The first memory unit includes: a first data memory cell for storing a first data bit; a first comparison circuit for comparing a first search bit with the first data bit to determine if there is a match, and outputting a first comparison result; and a first CMOS logic circuit for performing a logic operation on the first comparison result and outputting a first matching result. The second memory unit includes: a second data memory cell for storing a second data bit; a second comparison circuit for comparing a second search bit with the second data bit to determine if there is a match, and outputting a second comparison result; and a second static CMOS logic circuit for performing a logic operation on the first matching result and the second comparison result, and outputting an output matching result. | 03-18-2010 |
20140167993 | HYBRID DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF - Hybrid digital-to-analog converter and method thereof are provided. The hybrid digital-to-analog converter (DAC) includes a data processor, at least one first type DAC, at least one second type DAC, and an output circuit. The data processor processes an input digital signal to output at least one of first and second digital signals which are related to a higher bit portion and a lower bit portion of the input digital signal, respectively. If the data processor outputs the first digital signal to the first type DAC, the first type DAC converts the first digital signal. The at least one second type DAC receives and converts the second digital signal outputted from the data processor. The output circuit receives at least one output signal of the first and the second type DACs to output an output analog signal. | 06-19-2014 |
20150048885 | GAIN CONTROL CIRCUIT AND METHOD CAPABLE OF EASING LEAKAGE CURRENT INFLUENCE - The present invention discloses a gain control circuit capable of easing leakage current influence. According to an embodiment of the present invention, the gain control circuit comprises: at least one signal input end for receiving at least one input signal; a signal output end for outputting an output signal; an amplifier coupled between an amplifier input end and the signal output end; and a plurality of gain schemes. Each of the gain schemes is set between the at least one signal input end and the signal output end; and when one of the gain schemes is activated to generate the output signal, the rest gain schemes are inactivated to stop gain production and concurrently discharge leakage currents through their respective grounding paths. | 02-19-2015 |
Patent application number | Description | Published |
20150028384 | GaN TRANSISTORS WITH POLYSILICON LAYERS FOR CREATING ADDITIONAL COMPONENTS - A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer. | 01-29-2015 |
20150028390 | GaN DEVICE WITH REDUCED OUTPUT CAPACITANCE AND PROCESS FOR MAKING SAME - A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor. | 01-29-2015 |
20150034962 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 02-05-2015 |
Patent application number | Description | Published |
20120212797 | FLEXIBLE DISPLAY DEVICE - A flexible display device includes a flexible substrate, a display layer, a first protecting layer, and at least one light-pervious polymer film. The display layer is arranged on the flexible substrate. The first protecting layer is arranged on the display layer. The at least one light-pervious polymer film is arranged on the first protecting layer. The light-pervious polymer film is used to protect the flexible display device from being damaged by external force. | 08-23-2012 |
20130027853 | ELECTRONIC DEVICE WITH IMPACT-RESISTANT DISPLAY MODULE - An electronic device includes a shell, a display module and a cushion. The shell includes a bottom plate and a top plate. The top plate defines an opening The display module is disposed in the shell and faces the opening The display module is spaced from the bottom plate of the shell. The cushion is disposed between the display module and the bottom plate of the shell, and brought into contact with the display module for cushioning the display module when an external force is applied to the display module. | 01-31-2013 |
20130174985 | PEELING PROCESS OF SUBSTRATE - A peeling process of substrate used for peeling a first substrate and a second substrate bonded to each other is provided. The first substrate has a first bonding surface, and the second substrate has a second bonding surface and a back surface, wherein the first bonding surface and the second bonding surface are bonded to each other. In the peeling process of substrate, a light beam is incident through the back surface of the second substrate at a first incident angle and then illuminates the first bonding surface and the second bonding surface, wherein the first incident angle is smaller than 90 degree and larger than 0 degree. After that, the second substrate is peeled off from the first substrate. | 07-11-2013 |
Patent application number | Description | Published |
20100126418 | GAS SHOWER MODULE - A gas shower module for gas deposition chamber with gas channel is disclosed, which comprises: a distributor with at least one diffusion cell positioned therein along first axial direction and a plurality of inlets respectively connecting to the gas channel and the diffusion cell; and a shower with at least one shower channel positioned therein along second axial direction, gas-inlet passages connected to the diffusion cell and the shower channel, and gas-outlet passages connected to the shower channel and gas deposition chamber; wherein the distributor is connected to the shower so that the diffusion cell will be connected to the shower channel through gas-inlet passages and the first axial direction is not be parallel to the second axial direction. | 05-27-2010 |
20110186159 | GAS DISTRIBUTION MODULE AND GAS DISTRIBUTION SCANNING APPARATUS USING THE SAME - The present invention provides a gas distribution module, which is capable of directing a plurality of different gases and rendering the gases to be diffused evenly by the turning channels disposed within the module so that the gases can be distributed uniformly within the gas distribution module and thereby being delivered onto a substrate evenly. In addition, the present further provides a gas distribution scanning apparatus, which has a displacement driving unit coupled to the gas distribution module or a carrier supporting the substrate so that the gases can be delivered uniformly onto the substrate by means of the linear movement of the gas distribution module or the carrier. | 08-04-2011 |
20120121807 | FILM DEPOSITION SYSTEM AND METHOD AND GAS SUPPLYING APPARATUS BEING USED THEREIN - The present invention provides a film deposition system and method by combining a plurality of gas supplying apparatuses and a deposition apparatus being in communication with the plurality of gas supplying apparatuses. By means of respectively providing different types of vapor precursors with high concentration and high capacity into a process chamber of the deposition apparatus through the plurality of gas supplying apparatus, the deposition reaction is accelerated so as to improve the efficiency of film deposition. In an embodiment of the gas supplying apparatus, it utilizes a first gas for providing high pressure toward on a liquid surface of the precursor, thereby transporting the precursor into an atomizing and heating unit whereby the precursor is atomized and then is heated so as to form a high-concentration and high capacity vapor precursor transported by another carrier gas. | 05-17-2012 |
20120240855 | TRANSMISSION MECHANISM AND THE DEPOSITION APPARATUS USING THE SAME - The deposition apparatus has a plurality of said transmission mechanisms arranged therein in a symmetrical manner. Each transmission mechanism comprises: a drive shaft, formed with a tapered end; a driving wheel, configured with a shaft hole for the tapered end to bore coaxially therethrough; a plurality of slide pieces, radially mounted to the driving wheel; a first elastic member, mounted enabling the plural slide pieces to be ensheathed thereby; a second elastic member, disposed between the first elastic member and the first axial end of the drive shaft while being mounted to the periphery of the driving wheel; an enclosure, configured with an opening; wherein, the driving wheel that is moving in a reciprocating manner drives the sliding pieces to slide in radial directions, thereby, causing the outer diameter of the first elastic member to change accordingly and enabling the opening of the enclosure to open or close in consequence. | 09-27-2012 |
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20090027373 | DISPLAY AND DRIVING CONTROL METHOD THEREFOR - A display and a driving control method for the display are provided. The display includes a display panel, a driving control module and a power-saving control module. The display panel is configured to display a plurality of frames. The driving control module is coupled to the display panel for providing a driving signal of each frame to the display panel. The power saving control module is coupled to the driving control module. The displaying period of each frame includes a first period and a second period. During the first period, the display enters a displaying mode. During the second period, the power-saving control module adjusts the operating parameters of the driving control module such that the display enters a power-saving mode. As a result, the power consumption of the display can be reduced. | 01-29-2009 |
20090319185 | Navigation device with global position system and navigation method thereof - A navigation device with a global position system (GPS) includes an information input module and a global position system module. The information input module includes an image fetching unit and an image recognition unit. The image fetching unit fetches a pattern of an external object to produce image data. The image recognition unit transfers the image data into input data. The global position system module receives location position data associated with a present location of the navigation device, and provides navigation information according to the location position data and the input data. | 12-24-2009 |
20100182333 | Color Deviation Compensating Method and Driving Device for an LCD Panel and Related LCD Device - A color deviation compensating method for a LCD panel is disclosed. The LCD panel includes a plurality of pixel units arranged as a matrix, and each of the pixel units includes a plurality of sub-pixel units corresponding to a plurality of colors. The color deviation compensating method includes dividing the plurality of pixel units into a plurality of groups by columns, wherein each group is corresponding to a column of the LCD panel, and driving pixel units of the groups according to a plurality of triggering orders, wherein each of the triggering orders is corresponding to a charging sequence of sub-pixel units of pixel units corresponding to a group when displaying an image. | 07-22-2010 |
20110063245 | TOUCH APPARATUS AND DISPLAY PANEL THEREOF - A touch apparatus and a display panel thereof are provided. The touch apparatus includes an upper substrate and a lower substrate. The lower substrate at least includes a first selection line, a first readout line intersected with the first selection line, a first conductive bump, and a second conductive bump. The first and the second conductive bumps are disposed at the intersection of the first selection line and the first readout line, and electrically connected with the first selection line and the first readout line, respectively. The upper substrate at least includes a first conductive layer without potential, which is disposed above the first and the second conductive bumps. When an external force is exerted to the first conductive layer without potential, the first and the second conductive bumps are electrically connected to each other by the first conductive layer without potential. | 03-17-2011 |
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20100328442 | HUMAN FACE DETECTION AND TRACKING DEVICE - A human face detection device includes a photosensitive element, a human face detection unit, and a skin color threshold generation unit. The photosensitive element is used for capturing a first image containing a first human face block. The human face detection unit compares the first image with at least one human face feature, so as to detect the first human face block. The skin color threshold generation unit is used for updating a skin color threshold value according to the detected first human face block. The skin color threshold value is used for filtering the first image signal to obtain a candidate region, the human face detection unit compares the candidate region with the at least one human face feature to obtain the first human face block, and the skin color threshold value determines whether the first human face block detected by the human face detection unit is correct. | 12-30-2010 |
20100328498 | SHOOTING PARAMETER ADJUSTMENT METHOD FOR FACE DETECTION AND IMAGE CAPTURING DEVICE FOR FACE DETECTION - A shooting parameter adjustment method for face detection includes (A) acquiring an image; (B) dividing the image into a plurality of blocks, and calculating a brightness value of each of the blocks; (C) selecting at least one of the plurality of blocks, and adjusting a shooting parameter according to the brightness value of the selected block; and (D) acquiring another image according to the shooting parameter, and performing a face detection procedure with the another image. The shooting parameter adjustment method can automatically adjust a shooting parameter of an image capturing device according to brightness of different blocks in an image. Therefore, by using this method, the brightness of a face, no matter being too high or too low, can be adjusted to a value suitable for face detection, so as to improve the accuracy of the face detection procedure. | 12-30-2010 |
20100329518 | DYNAMIC IMAGE COMPRESSION METHOD FOR HUMAN FACE DETECTION - A dynamic image compression method for human face detection includes the following steps. An original image is acquired. The image is divided into a plurality of blocks. A first brightness and a plurality of gradient values of each block are calculated. A second brightness of each block is calculated according to a brightness transformation function and the first brightness. A reconstruction image is generated according to the second brightness and the plurality of gradient values of each block. Human face detection is performed according to the reconstruction image. Therefore, gradient values within an original square are. When the human face detection process is performed through gradient direction information, a success rate of detection is greatly increased. | 12-30-2010 |
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20080304287 | Microstructure transfer medium and application thereof - The present invention discloses a microstructure transfer medium and application thereof to produce various microstructures on a film, glass substrate, plastic substrate, etc. for utilization in a variety of optical films of a backlight module, light guide plates, color enhancement film for liquid crystal displays, various patterned nanoimprint for semiconductor or flat panel display processes, and Fresnel lens. Furthermore, the microstructure transfer medium according to the present invention can be applied in producing microstructures on a non-planar surface. The microstructure transfer medium according to the present invention comprises a substrate and a release layer formed on the substrate wherein the release layer has microstructures thereon. Preferably, the surface energy of the release layer is lower than 30 dyne/cm. | 12-11-2008 |
20090122540 | LIGHTING DEVICE - The invention discloses a lighting device, comprising at least one light source, a light source holder for holding the at least one light source, at least one microstructure member for deflecting light from the at least one light source, and at least one supporting member for maintaining the predetermined distance between the at least one light source and the at least one microstructure member. | 05-14-2009 |