Patent application number | Description | Published |
20110196855 | REAL TIME CONTENT SEARCHING IN SOCIAL NETWORK - Indexing and retrieving real time content in a social networking system is disclosed. A user-term index includes user-term partitions, each user-term partition comprising temporal databases. As a post is received from a user, a user identifier, a post identifier, and a post is extracted. An object store communicatively coupled to a temporal database for recently received content is queried to determine whether terms in the post has already been stored. A term identifier is stored in the user-term index with the user and post identifiers. A forward index stores the post by post identifier. Responsive to a search query, the user-term index is searched by the user's connections and the terms. A real time search engine compiles the results of the user-term index query and retrieves the stored posts from the forward index. The search results may then be ranked and cached before presentation to the searching user. | 08-11-2011 |
20130246390 | REAL TIME CONTENT SEARCHING IN SOCIAL NETWORK - Indexing and retrieving real time content in a social networking system is disclosed. A user-term index includes user-term partitions, each user-term partition comprising temporal databases. As a post is received from a user, a user identifier, a post identifier, and a post is extracted. An object store communicatively coupled to a temporal database for recently received content is queried to determine whether terms in the post has already been stored. A term identifier is stored in the user-term index with the user and post identifiers. A forward index stores the post by post identifier. Responsive to a search query, the user-term index is searched by the user's connections and the terms. A real time search engine compiles the results of the user-term index query and retrieves the stored posts from the forward index. The search results may then be ranked and cached before presentation to the searching user. | 09-19-2013 |
20140250101 | REAL TIME CONTENT SEARCHING IN SOCIAL NETWORK - Indexing and retrieving real time content in a social networking system is disclosed. A user-term index includes user-term partitions, each user-term partition comprising temporal databases. As a post is received from a user, a user identifier, a post identifier, and a post is extracted. An object store communicatively coupled to a temporal database for recently received content is queried to determine whether terms in the post has already been stored. A term identifier is stored in the user-term index with the user and post identifiers. A forward index stores the post by post identifier. Responsive to a search query, the user-term index is searched by the user's connections and the terms. A real time search engine compiles the results of the user-term index query and retrieves the stored posts from the forward index. The search results may then be ranked and cached before presentation to the searching user. | 09-04-2014 |
20150154237 | REAL TIME CONTENT SEARCHING IN SOCIAL NETWORK - Indexing and retrieving real time content in a social networking system is disclosed. A user-term index includes user-term partitions, each user-term partition comprising temporal databases. As a post is received from a user, a user identifier, a post identifier, and a post is extracted. An object store communicatively coupled to a temporal database for recently received content is queried to determine whether terms in the post has already been stored. A term identifier is stored in the user-term index with the user and post identifiers. A forward index stores the post by post identifier. Responsive to a search query, the user-term index is searched by the user's connections and the terms. A real time search engine compiles the results of the user-term index query and retrieves the stored posts from the forward index. The search results may then be ranked and cached before presentation to the searching user. | 06-04-2015 |
Patent application number | Description | Published |
20090093501 | Heterocyclic antiviral compounds - This invention relates to piperidine derivatives of formula I wherein R | 04-09-2009 |
20090215750 | Pyrrolopyrazine kinase inhibitors - The present invention relates to the use of novel pyrrolopyrazine derivatives of Formula I, | 08-27-2009 |
20090215788 | Pyrrolopyrazine kinase inhibitors - The present invention relates to the use of novel pyrrolopyrazine derivatives of Formula I, | 08-27-2009 |
20090281133 | Heterocyclic antiviral compounds - This invention relates to piperidine derivatives of formula I wherein R | 11-12-2009 |
20100267666 | Pyrrolopyrazine kinase inhibitors - The present invention relates to the use of novel pyrrolopyrazine derivatives of Formula I, | 10-21-2010 |
20110071179 | MACROCYCLIC INHIBITORS OF JAK - The present invention relates to the use of novel macrocyclic compounds of Formula I, | 03-24-2011 |
20120264737 | Heterocyclic Modulators of Lipid Synthesis - Compounds that are fatty acid synthesis modulators are provided. The compounds may be used to treat disorders characterized by disregulation of the fatty acid synthase function by modulating the function and/or the fatty acid synthase pathway. Methods are provided for treating such disorders including viral infections, such as hepatitis C infection, cancer and metabolic disorders. | 10-18-2012 |
20140322355 | HETEROCYCLIC MODULATORS OF LIPID SYNTHESIS - Compounds that are fatty acid synthesis modulators are provided. The compounds may be used to treat disorders characterized by disregulation of the fatty acid synthase function by modulating the function and/or the fatty acid synthase pathway. Methods are provided for treating such disorders including viral infections, such as hepatitis C infection, cancer and metabolic disorders. | 10-30-2014 |
20150210688 | HETEROCYCLIC MODULATORS OF LIPID SYNTHESIS - Heterocyclic modulators of lipid synthesis are provided as well as pharmaceutically acceptable salts thereof; pharmaceutical compositions comprising such compounds; and methods of treating conditions characterized by disregulation of a fatty acid synthase pathway by the administration of such compounds. | 07-30-2015 |
20150259292 | HETEROCYCLIC MODULATORS OF LIPID SYNTHESIS - Compounds that are fatty acid synthesis modulators are provided. The compounds may be used to treat disorders characterized by disregulation of the fatty acid synthase function by modulating the function and/or the fatty acid synthase pathway. Methods are provided for treating such disorders including viral infections, such as hepatits C infection, cancer and metabolic disorders. | 09-17-2015 |
20160102091 | HETEROCYCLIC MODULATORS OF LIPID SYNTHESIS - Compounds that are fatty acid synthesis modulators are provided. The compounds may be used to treat disorders characterized by disregulation of the fatty acid synthase function by modulating the function and/or the fatty acid synthase pathway. Methods are provided for treating such disorders including viral infections, such as hepatitis C infection, cancer and metabolic disorders. | 04-14-2016 |
Patent application number | Description | Published |
20130325755 | METHODS AND SYSTEMS FOR OPTIMIZING MESSAGES TO USERS OF A SOCIAL NETWORK - Techniques to optimize messages sent to a user of a social networking system. In one embodiment, information about the user may be collected by the social networking system. The information may be applied to train a model for determining likelihood of a desired action by the user in response to candidate messages that may be provided for the user. The social networking system may provide to the user a message from the candidate messages with a selected likelihood of causing the desired action. | 12-05-2013 |
20130325948 | METHODS AND SYSTEMS FOR INCREASING ENGAGEMENT OF LOW ENGAGEMENT USERS IN A SOCIAL NETWORK - Techniques to increase engagement with a social networking system. In one embodiment, an engagement level of a user with a social networking system is monitored. A low engagement user type associated with the user is identified from a plurality of low engagement user types. It is determined whether the engagement level of the user is less than a threshold. If so, a communication is provided for the user based on the low engagement user type associated with the user. The communication may be a notification or a digest communication. | 12-05-2013 |
20150058423 | METHODS AND SYSTEMS FOR INCREASING ENGAGEMENT OF LOW ENGAGEMENT USERS IN A SOCIAL NETWORK - Techniques to increase engagement with a social networking system. In one embodiment, an engagement level of a user with a social networking system is monitored. A low engagement user type associated with the user is identified from a plurality of low engagement user types. It is determined whether the engagement level of the user is less than a threshold. If so, a communication is provided for the user based on the low engagement user type associated with the user. The communication may be a notification or a digest communication. | 02-26-2015 |
20150074215 | Methods And Systems For Optimizing Messages To Users Of A Social Network - Techniques to optimize messages sent to a user of a social networking system. In one embodiment, information about the user may be collected by the social networking system. The information may be applied to train a model for determining likelihood of a desired action by the user in response to candidate messages that may be provided for the user. The social networking system may provide to the user a message from the candidate messages with a selected likelihood of causing the desired action. | 03-12-2015 |
Patent application number | Description | Published |
20090250335 | Method of controlling plasma distribution uniformity by superposition of different constant solenoid fields - A method for processing a workpiece in a plasma reactor having a set of n coils includes constructing, for each one of the n coils, a set of plasma distributions for discrete values of coil current in a predetermined current range. The distributions are grouped, each group having one distribution for each of the n coils, and being a unique set of n distributions. A combined plasma distribution is computed from each group of distributions. The variance of each combined distribution is computed. The method further includes finding an optimum one of the combined distributions having an at least nearly minimum variance, and identifying the n coil currents associated with the optimum distribution. During plasma processing of the workpiece, currents through the coils are maintained at levels corresponding to the n coil currents associated with the one combined distribution. | 10-08-2009 |
20090250432 | Method of controlling plasma distribution uniformity by time-weighted superposition of different solenoid fields - A method of processing a workpiece in a chamber of a plasma reactor having a set of plural electromagnet coils includes selecting plural predetermined plasma density distributions relative to a workpiece surface, the predetermined plasma density distributions corresponding to different sets of D.C. currents in the coils, and flowing a process gas into the chamber and generating a plasma in the chamber. The method further includes switching plasma in the chamber between the predetermined plasma density distributions by switching D.C. currents through the coils between the different sets of D.C. currents. | 10-08-2009 |
20110201134 | CAPACITIVELY COUPLED PLASMA REACTOR WITH MAGNETIC PLASMA CONTROL - A plasma reactor includes a vacuum enclosure including a side wall and a ceiling defining a vacuum chamber, and a workpiece support within the chamber and facing the ceiling for supporting a planar workpiece, the workpiece support and the ceiling together defining a processing region between the workpiece support and the ceiling. Process gas inlets furnish a process gas into the chamber. A plasma source power electrode is connected to an RF power generator for capacitively coupling plasma source power into the chamber for maintaining a plasma within the chamber. The reactor further includes at least a first overhead solenoidal electromagnet adjacent the ceiling, the overhead solenoidal electromagnet, the ceiling, the side wall and the workpiece support being located along a common axis of symmetry. A current source is connected to the first solenoidal electromagnet and furnishes a first electric current in the first solenoidal electromagnet whereby to generate within the chamber a magnetic field which is a function of the first electric current, the first electric current having a value such that the magnetic field increases uniformity of plasma ion density radial distribution about the axis of symmetry near a surface of the workpiece support. | 08-18-2011 |
Patent application number | Description | Published |
20130328873 | FORWARD RENDERING PIPELINE WITH LIGHT CULLING - A method for enhanced forward rendering is disclosed which includes a depth pre-pass, light culling and a final shading. The depth pre-pass minimizes the cost of final shading by avoiding high pixel overdraw. The light culling stage calculates a list of light indices overlapping a pixel. The light indices are calculated on a per-tile basis, where the screen has been split into units of tiles. The final shading evaluates materials using information stored for each light. The forward rendering method may be executed on a processor, such as a single graphics processing unit (GPU) for example. | 12-12-2013 |
20140280492 | Method and System for Distributing Data among a Multi-Tenant service with a Shared Userbase - A method and system for distributing data among a multi-tenant system with shared and non-shared users. Shared users may be global across the system or per tenant or developer. Non-shared users would be per app. While some data would be shared across users, other data stored within the multi-tenant system would be related specifically to the app, including gameplay data and non-gameplay data, such as leaderboards, inventory, virtual currency. Userbases may be upgraded and downgraded per app or per developer. | 09-18-2014 |
20140327696 | VARIABLE ACUITY RENDERING USING MULTISAMPLE ANTI-ALIASING - Embodiments are described for a method for using anti-aliasing hardware to generate a higher resolution image at the processing of a lower resolution image with anti-aliasing. A graphics image comprising allocating a buffer used in a multisample anti-aliasing process, wherein the allocated buffer has a dimension comprising a reduction in at least one of the width or height of an original dimension of an original buffer provided by the anti-aliasing hardware; rendering sampled image data to the allocated buffer at a sampling rate proportional to the reduction; and expanding the allocated buffer back to the dimension of the original buffer. | 11-06-2014 |
Patent application number | Description | Published |
20100244106 | Fabrication and structure of asymmetric field-effect transistors using L-shaped spacers - Fabrication of an asymmetric field-effect transistor ( | 09-30-2010 |
20100244128 | Configuration and fabrication of semiconductor structure using empty and filled wells - A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs ( | 09-30-2010 |
20100244130 | Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket - Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET ( | 09-30-2010 |
20100244131 | Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions - An asymmetric insulated-gate field-effect transistor ( | 09-30-2010 |
20100244143 | Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length - A semiconductor structure contains a bipolar transistor ( | 09-30-2010 |
20100244147 | Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone - An asymmetric insulated-gate field effect transistor ( | 09-30-2010 |
20100244149 | Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses - A group of high-performance like-polarity insulated-gate field-effect transistors ( | 09-30-2010 |
20120181619 | Configuration and Fabrication of Semiconductor Structure Having Bipolar Junction Transistor in Which Non-monocrystalline Semiconductor Spacing Portion Controls Base-link Length - A semiconductor structure contains a bipolar transistor ( | 07-19-2012 |
20120264263 | Structure and Fabrication of Like-polarity Field-effect Transistors Having Different Configurations of Source/Drain Extensions, Halo Pockets, and Gate Dielectric Thicknesses - A group of high-performance like-polarity insulated-gate field-effect transistors ( | 10-18-2012 |
20130015535 | Configuration and Fabrication of Semiconductor Structure Having Asymmetric Field-effect Transistor with Tailored Pocket Portion Along Source/Drain Zone - An asymmetric insulated-gate field effect transistor ( | 01-17-2013 |
20130126970 | CONFIGURATION AND FABRICATION OF SEMICONDUCTOR STRUCTURE USING EMPTY AND FILLED WELLS - A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs ( | 05-23-2013 |
Patent application number | Description | Published |
20090254516 | ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS - Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements. | 10-08-2009 |
20090254532 | ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES - Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups. | 10-08-2009 |
20110167055 | HARDWARE ACCELERATED RECONFIGURABLE PROCESSOR FOR ACCELERATING DATABASE OPERATIONS AND QUERIES - Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance. | 07-07-2011 |
20110167083 | HARDWARE ACCELERATED RECONFIGURABLE PROCESSOR FOR ACCELERATING DATABASE OPERATIONS AND QUERIES - Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance. | 07-07-2011 |
20110218987 | HARDWARE ACCELERATED RECONFIGURABLE PROCESSOR FOR ACCELERATING DATABASE OPERATIONS AND QUERIES - Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance. | 09-08-2011 |
20110246432 | ACCESSING DATA IN COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES - Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups. | 10-06-2011 |
20140279759 | TRAINING OF STORAGE DEVICES IN COMPUTING SYSTEMS AND ENVIRONMENTS - Storage devices and components, including memory components (e.g., non-volatile memory) can be trained by executable code that facilitates and/or performs reads and/or write requests to one or more storage sub-modules of a storage component (e.g., memory configured on a memory channel) made up of multiple storage components (e.g., DIMMs). The executable code can also train multiple storage components at the same time and/or in parallel. | 09-18-2014 |
20140281780 | ERROR DETECTION AND RECOVERY OF TRANSMISSION DATA IN COMPUTING SYSTEMS AND ENVIRONMENTS - Errors that can be detected as a result of the mapping of transmission data from its physical form back to its logical form can be considered in addition to the errors detected by using an error detection technique (e.g., a conventional CRC technique), thereby allowing fewer error detection/recovery bits (error recovery data or bits) to be used as would be possible by using the error detection technique alone. In other words, less error recovery data would be needed to achieve a given level accuracy using conventional techniques. As a result, overhead associated with adding error detection/recovery bits can be reduced. | 09-18-2014 |
20140324821 | ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS - Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements. | 10-30-2014 |
Patent application number | Description | Published |
20110252743 | Bolted Steel Connections with 3-D Jacket plates and Tension Rods - This new versatile steel connection has three unique features: (1) utilizes three dimensional connection plates in a simple and consistent manner, and is suitable for all possible connection type that is made of steel W-sections; (2) uses through the depth steel rods, coupled with typical web stiffeners to transfer shear and bending moment across the connection. The shear transfer mechanism is similar to stirrups in reinforced concrete beams; (3) all components and parts can be prefabricated in shop, and conveniently bolted together at field. The merits of the connections include higher strength and ductility, stronger yet simpler connections, higher quality, small components for easy storage and transportation. In one word, it eliminates all of the inherent drawbacks and problems of conventional bolted and/or welded connections. | 10-20-2011 |
20120011805 | STEEL AND WOOD COMPOSITE STRUCTURE WITH METAL JACKET WOOD STUDS AND RODS - A composite member provides support to a structure. A wooden core of the composite member has a perimeter and a length. The wooden core provides support to the structure. A metal jacket is attached to the perimeter of the wooden core of the composite member and spans the entire length. The metal jacket provides also support to the structure. Furthermore, the interaction between the wooden core and the metal jacket provide a combination of strength that surpasses the sum of individual strengths. | 01-19-2012 |
20120298943 | Composite Guardrail Posts and Composite Floor I-Joist - The first product is Composite Guardrail Post (CGP). CGP is designed overcome all these drawbacks by substituting standard timber posts with metal jacket composite posts. The second product is Composite Floor Joist (CFI). The current invention (CFI) is similar to TJI in concept, but uses all composite material for both flanges and webs. Also, the connections between flange and web are much stronger, enabling the development of composite actions to the fullest extent. | 11-29-2012 |
20130160398 | COMPOSITE I-BEAM MEMBER - A composite steel I-beam member. The member includes confined top and bottom flanges, and a composite laminated web. The confined flange comprises a wooden core and a metal jacket wrapped around an outer perimeter of the wooden core. The overall load carrying capacity of the composite I-beam is significantly increased through a list of composite actions occurring in the individual components and their connections. Most importantly, a two-way lateral interaction can be normal to the interface between the metal jacket and the wooden core and provide an amount of compressive support to the top flange surpassing the sum of amount of support provided by the metal jacket and the wooden core when being used separately. | 06-27-2013 |
20130239512 | STEEL AND WOOD COMPOSITE STRUCTURE WITH METAL JACKET WOOD STUDS AND RODS - A composite member provides support to a structure. A wooden core of the composite member has a perimeter and a length. The wooden core provides support to the structure. A metal jacket is tightly wrapped to an optimum circumferential pre-stress around the entire perimeter of the wooden core of the composite member and spans the entire length. The metal jacket provides also support to the structure. Furthermore, the interaction between the wooden core and the metal jacket provide a combination of strength that surpasses the sum of individual strengths. | 09-19-2013 |
20140083046 | BOLTED STEEL CONNECTIONS WITH 3-D JACKET PLATES AND TENSION RODS - A three-dimensional jacket-plate connector connects at least two members. Each member comprises wide-flanged steel I-beam section. The jacket-plate connector comprises first and second three-dimensional jacket plates. | 03-27-2014 |
20140182234 | BOLTED STEEL CONNECTIONS WITH 3-D JACKET PLATES AND TENSION RODS - A three-dimensional jacket-plate connector connects at least two members. The jacket-plate connector comprises first and second three-dimensional jacket plates. Each jacket plate comprises a single continuous side web and segments of combined flanges perpendicular to, and located around the perimeter of, the side web. With all interior flanges notched out, the side web and perimeter flanges envelopes a void interior space without obstacles against accommodation of I-beam members installed from all directions. | 07-03-2014 |
20140182235 | BOLTED STEEL CONNECTIONS WITH 3-D JACKET PLATES AND TENSION RODS - A three-dimensional jacket-plate connector connects at least two members. Each member comprises wide-flanged steel I-beam section. The jacket-plate connector comprises first and second three-dimensional jacket plates. | 07-03-2014 |
20150135638 | COMPOSITE I-BEAM MEMBER - A composite steel I-beam member. The member includes confined top and bottom flanges, and a composite laminated web. The confined flange comprises a wooden core and a metal jacket wrapped around an outer perimeter of the wooden core. The overall load carrying capacity of the composite I-beam is significantly increased through a list of composite actions occurring in the individual components and their connections. Most importantly, a two-way lateral interaction can be normal to the interface between the metal jacket and the wooden core and provide an amount of compressive support to the top flange surpassing the sum of amount of support provided by the metal jacket and the wooden core when being used separately. | 05-21-2015 |
Patent application number | Description | Published |
20090040081 | ENCODING AND DECODING METHODS USING GENERALIZED CONCATENATED CODES (GCC) - Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. | 02-12-2009 |
20090055605 | METHOD AND SYSTEM FOR OBJECT-ORIENTED DATA STORAGE - In accordance with the present invention, data may be written and read differently in accordance with their attributes, which may include, inter alia, critical vs. non-critical data, streaming vs. non-streaming media, confidential vs. non-confidential, or read/write speed requirements. A data block to be written may be considered an object, and is examined, and from its attributes one or more memory device operating modes may be determined, such as different numbers of bits per cell, different numbers of error-correction code (ECC) parities per user data block, and encryption vs. lack of encryption. The storage controller then performs the writing process according to the mode(s) of operation determined by the attributes. Multi-level flash memory, in particular, is capable of operating in these various modes, at a trade-off between reliability, speed, endurance on the one hand, and capacity on the other hand. | 02-26-2009 |
20090059661 | SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE - A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells. | 03-05-2009 |
20090300465 | STATISTICAL TRACKING FOR FLASH MEMORY - A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data. | 12-03-2009 |
20090319825 | MONITORING MEMORY - Devices, systems, methods, and other embodiments associated with monitoring memory are described. In one embodiment, a method determines a first data quality associated with a set of data stored in flash memory. Based, at least in part, on the first data quality, the flash memory is controlled to correct the set of data to produce a corrected set of data. The corrected set of data is reprogrammed into the flash memory. | 12-24-2009 |
20110043390 | ENCODING AND DECODING METHODS USING GENERALIZED CONCATENATED CODES (GCC) - Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. | 02-24-2011 |
20120099372 | Sequence Detection for Flash Memory With Inter-Cell Interference - A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells. | 04-26-2012 |
20120278682 | ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells. | 11-01-2012 |
20130080729 | PILOT PLACEMENT FOR NON-VOLATILE MEMORY - A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison. | 03-28-2013 |
20130107622 | SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE | 05-02-2013 |
20140325179 | SYSTEM AND METHOD FOR WRITING PILOT DATA INTERSPERSED WITH USER DATA FOR ESTIMATING DISTURBANCE EXPERIENCED BY USER DATA - A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page. | 10-30-2014 |
Patent application number | Description | Published |
20100067288 | MEMORY DEVICE STRUCTURES INCLUDING PHASE-CHANGE STORAGE CELLS - A conductive write line of a memory device includes a resistive heating portion for setting and resetting a phase-change material (PCM) storage cell of the device. A dielectric interface extends between the resistive heating portion of the write line and a side of the storage cell, and provides electrical insulation while allowing for thermal coupling between the resistive heating portion and the storage cell. A width of the resistive heating portion of the write line may be less than a width of the storage cell and/or may be less than a width of adjacent portions of the write line, between which the resistive heating portion extends. The side of the storage cell may define a channel of the storage cell through which the write line passes, such that the resistive heating portion is located within the channel. | 03-18-2010 |
20100237496 | Thermal Interface Material with Support Structure - Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader. | 09-23-2010 |
20110304051 | THERMAL INTERFACE MATERIAL WITH SUPPORT STRUCTURE - Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader. | 12-15-2011 |
20120043668 | STACKED SEMICONDUCTOR CHIPS WITH THERMAL MANAGEMENT - A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture. | 02-23-2012 |
20120278029 | Transient Thermal Modeling of Multisource Power Devices - Embodiments of systems and methods for improved measurement of transient thermal responses in electronic systems are described herein. Embodiments of the disclosure use the known thermal transfer function of an electronic system to generate an equivalent resistor-capacitor (RC) network having a dynamic response that is identical to a given power excitation as the actual electronic system would have to that power excitation. Using the analogy between thermal and electrical systems, a Foster RC network is constructed, comprising a plurality of RC stages in which resistors and capacitors are connected in parallel. Subsequently, the analog thermal RC network is converted into an infinite impulse response (IIR) digital filter, whose coefficients can be obtained the Z-transform of the analog thermal RC network. This IIR digital filter establishes the recursive relationship between temperature output at the current time step and measured power input at the previous time step. Using this IIR digital filter, temperature response subject to arbitrary time-dependent power can be calculated in very small amount of time compared with prior art methods. | 11-01-2012 |
20150117486 | System and Method for Calibrating Temperatures Sensor for Integrated Circuits - In some embodiments, a method may be provided for calibrating integrated circuit temperature sensors. The method may include sensing a first temperature using a first temperature sensor and a second temperature using a second temperature sensor. The first temperature sensor may be calibrated and is external to a package of the integrated circuit. The second temperature sensor may be included in the integrated circuit. The method may include increasing a temperature of the integrated circuit. The method may include allowing the integrated circuit and the package to thermally equilibrate over a first period of time. The method may include sensing a first slope of a temperature decay by the first temperature sensor. The method may include sensing a second slope of a temperature decay by the second temperature sensor. The method may include calibrating the second temperature sensor responsive to a difference between the first and second temperatures and the first and second slopes. | 04-30-2015 |
20150118795 | PoP STRUCTURE WITH ELECTRICALLY INSULATING MATERIAL BETWEEN PACKAGES - A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages. | 04-30-2015 |
Patent application number | Description | Published |
20130128193 | Displays with Multilayer Masks and Color Filters - An electronic device may have a display such as a liquid crystal display. The display may have multiple layers of material such as a color filter layer and a thin-film transistor layer. An opaque masking layer may be formed on a display layer such as the color filter layer. In an inactive portion of the display, the opaque masking layer may form a rectangular ring that serves as a border region surrounding a rectangular active portion of the display. In the active portion of the display, the opaque masking layer may be patterned to from an opaque matrix that separates color filter elements in an array of color filter elements. The opaque masking layer and color filter elements may be formed from polymers such as photoresist. The opaque masking layer may include a black pigment such as carbon black. Color filter elements and opaque masking material may include multiple sublayers. | 05-23-2013 |
20130201429 | Display With Color Mixing Prevention Structures - An electronic device may have a liquid crystal display having a backlight and color mixing prevention structures. The color mixing prevention structures may, in part, be formed from one or more arrays of color filter elements. The liquid crystal display may include first and second transparent substrate layers on opposing sides of a liquid crystal layer. The display may include a first array of color filter elements on the first transparent substrate layer and a second array of color filter elements on the second transparent substrate layer. One or more of the arrays of color filter elements may include a black matrix formed over portions of the color filter elements. The color filter elements may fill or partially fill openings in the black matrix. The display may include a collimating layer on the second transparent substrate layer. The color filter elements may include cholesteric color filter elements. | 08-08-2013 |
20130265521 | Displays with Low Reflectance Border Regions - An electronic device may have a display such as a liquid crystal display. A color filter layer may be formed on a display layer such as a transparent substrate layer of the display. The color filter layer may include an array of color filter elements on an inner surface of the transparent substrate layer. The color filter layer may include opaque masking material. In an inactive portion of the display, the opaque masking material may be formed over the color filter elements and interposed between the color filter elements. In the inactive portion of the display, the opaque masking material and the color filter elements may form a ring that serves as a border region surrounding an active portion of the display. In the active portion of the display, the opaque masking layer may be patterned to from an opaque matrix that separates the color filter elements. | 10-10-2013 |
20130300978 | Display with Minimized Light Leakage - Displays such as liquid crystal displays may be provided with transparent substrates that minimize light leakage from the display. The transparent substrates may include a thin-film transistor substrate having thin-film transistors formed on a surface of the thin-film transistor substrate and a color filter substrate having color filter elements formed on a surface of the color filter substrate. The thin-film transistor substrate may be formed from a material having a relatively low photo-elastic constant. The color filter substrate may be formed from a material having a relatively low photo-elastic constant. Reduced birefringence effects in the thin-film transistor substrate and the color filter substrate may help minimize light leakage from the display when some or all of the display experiences internal or external stresses. | 11-14-2013 |
20140078448 | Stress Insensitive Liquid Crystal Display - A display is provided that has upper and lower polarizers, a color filter layer, a liquid crystal layer, and a thin-film transistor layer. The color filter layer and thin-film transistor layer may be formed from materials such as glass that are subject to stress-induced birefringence. To reduce light leakage that reduces display performance, one or more internal layers may be incorporated into the display to help ensure that linearly polarized backlight that passes through the display is not undesirably converted into elliptically polarized light. The internal layers may include a thin-film polarizer layer that forms a coating on the color filter layer, a thin-film polarizer layer that forms a coating on the thin-film-transistor layer, a retarder layer that is formed as a coating on the color filter layer, and a retarder layer that is formed as a coating on the thin-film-transistor layer. | 03-20-2014 |
20140078450 | Stress Insensitive Liquid Crystal Display - A display is provided that has upper and lower polarizers, a color filter layer, a liquid crystal layer, and a thin-film transistor layer. The color filter layer and thin-film transistor layer may be formed from materials such as glass that are subject to stress-induced birefringence. To reduce light leakage that reduces display performance, one or more internal layers may be incorporated into the display to help ensure that linearly polarized backlight that passes through the display is not undesirably converted into elliptically polarized light. The internal layers may include a thin-film polarizer layer that forms a coating on the color filter layer, a thin-film polarizer layer that forms a coating on the thin-film-transistor layer, a retarder layer that is formed as a coating on the color filter layer, and a retarder layer that is formed as a coating on the thin-film-transistor layer. | 03-20-2014 |
20140104527 | Process Architecture for Color Filter Array in Active Matrix Liquid Crystal Display - An active matrix liquid crystal display having an array of pixels is provided. The display includes a thin film transistor (TFT) for each pixel. The TFT has a gate electrode, a source electrode overlapping with a first area of the gate electrode, and a drain electrode overlapping with a second area with the gate electrode. The display also includes a color filter layer disposed over the TFT. The color filter layer has a first via hole to expose a portion of the drain electrode. The display further includes a metal layer disposed over the color filter layer and covering the gate electrode. The metal layer is configured to connect to the drain electrode through the first via hole. The display also includes an organic insulator layer disposed over the metal layer. The organic insulator layer has a second via hole to expose a first portion of the metal layer and a third via hole to expose a second portion of the metal layer. | 04-17-2014 |
20140118666 | Display with Column Spacer Structures Resistant to Lateral Movement - A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor layer. Column spacers may be formed on the color filter layer to maintain a desired gap between the color filter and thin-film transistor layers. Support pads may be used to support the column spacers. Different column spacers may be located at different portions of the support pads to allow the support pad size to be reduced while ensuring adequate support. Lateral movement blocking structures such as circular rings may be used to prevent column spacer lateral movement. Subspacers located over pads may be used to create friction that retards lateral movement. Lateral movement may also be retarded by receiving column spacers in trenches or other recesses formed on a thin-film transistor layer. | 05-01-2014 |
20140152703 | Displays With Adjustable Circular Polarizers - An electronic device display may have an organic light-emitting diode layer that emits light to form images for a user. Reflective structures such as metal signal lines may be present in the organic light-emitting diode layer. Ambient light reflections from the metal signal lines may be suppressed using a circular polarizer on the organic light-emitting diode layer. To increase light emission efficiency from the organic light-emitting diode display layer under low ambient light conditions in which ambient light reflections are not significant, the polarization efficiency of the circular polarizer may be reduced. Control circuitry may make measurements of ambient light intensity using an ambient light sensor and can control the polarization efficiency of the circular polarizer accordingly by applying adjustable amounts of light or electric field. Polarization efficiency may also be adjusted using a photosensitive polarizer material that responds directly to changes in ambient light level. | 06-05-2014 |
20140327861 | Liquid Crystal Displays With Reduced Light Leakage - A display is provided that has upper and lower polarizers, a color filter layer, a liquid crystal layer, and a thin-film transistor layer. The color filter layer and thin-film transistor layer may be formed from materials such as glass that are subject to stress-induced birefringence. To reduce light leakage that reduces display performance, one or more birefringence compensation layers may be incorporated into the display to help compensate for any birefringence effects. The compensation layers may include a birefringence compensation layer attached to the color filter layer or the thin-film transistor layer. A display may include an upper compensation layer attached to the color filter layer and a lower compensation layer attached to the thin-film transistor layer. The compensation layer may be formed from glass or polymer materials that have a negative photo-elastic constant. | 11-06-2014 |
20150176775 | Display Having Backlight With Narrowband Collimated Light Sources - A display has an array of display pixels formed from display layers such as one or more polarizer layers, a substrate on which an array of display pixel elements such as color filter elements and downconverter elements are formed, a liquid crystal layer, and a thin-film transistor layer that includes display pixel electrodes and display pixel thin-film transistors for driving control signals onto the display pixel electrodes to modulate light passing through the display pixels. A light source such as one or more laser diodes or light-emitting diodes may be used to generate light for the display. The light may be launched into the edge of a polymer layer or other light guide plate structure. A light guide plate may include phase-matched structures such as holographically recorded gratings or photonic lattices that direct the light upwards through the array of display pixels. | 06-25-2015 |
20150227000 | Display With Color Mixing Prevention Structures - An electronic device may have a liquid crystal display having a backlight and color mixing prevention structures. The color mixing prevention structures may, in part, be formed from one or more arrays of color filter elements. The liquid crystal display may include first and second transparent substrate layers on opposing sides of a liquid crystal layer. The display may include a first array of color filter elements on the first transparent substrate layer and a second array of color filter elements on the second transparent substrate layer. One or more of the arrays of color filter elements may include a black matrix formed over portions of the color filter elements. The color filter elements may fill or partially fill openings in the black matrix. The display may include a collimating layer on the second transparent substrate layer. The color filter elements may include cholesteric color filter elements. | 08-13-2015 |
20150331292 | Display with Opaque Border Resistant to Electrostatic Discharge - A display may have a color filter layer and a thin-film transistor layer. A liquid crystal layer may be located between the color filter layer and the thin-film transistor layer. The display may have an active area surrounded by an inactive area. The opaque border layer may contain first and second opaque layers in the inactive area. The first opaque layer may have an opening in the inactive area that is overlapped by an isolation layer. The second opaque layer may be located in the inactive area and may overlap the opening in the first opaque layer to block light in the inactive area. The isolation layer may be interposed between the first and second opaque layers and may prevent static charge from an electrostatic discharge event along the edge of the display from migrating to the active area through the opaque border in the inactive area. | 11-19-2015 |
20150362795 | Color Filter Structures for Electronic Devices With Color Displays - A display may have a color filter layer and a thin-film transistor layer. A liquid crystal layer may be located between the color filter layer and the thin-film transistor layer. The color filter layer may have an array of color filter elements on a transparent substrate. The array of color filter elements may include more than three colors. Colored photoimageable polymer layers may be combined to form some of the color filter elements. The color filter may have cyan, magenta, and yellow color filter elements each formed from a respective single layer of cyan, magenta, and yellow polymer and may have blue elements formed by overlapping cyan and magenta polymer, green elements formed by overlapping cyan and yellow polymer, and red elements formed by overlapping magenta and yellow polymer. Filters with white elements may also be provided. | 12-17-2015 |
Patent application number | Description | Published |
20120155578 | MULTI-RAKE RECEIVER - A receiver includes a select module, an enable module, and a receiver module. The select module is configured to detect (i) a number of antennas in the receiver, or (ii) a number of enabled receiver paths in the receiver. The select module is also configured to generate a receiver select signal and an adjustment signal based on (i) the number of antennas detected, or (ii) the number of enabled receiver paths detected. The enable module is configured to, based on the receiver select signal, (i) determine that at least one of the enabled receiver paths is an unnecessary receiver path, and (ii) disable the at least one of the enabled receiver paths. The receiver module is configured to, based on the adjustment signal, adjust a bandwidth of the receiver or coefficient values of the receiver. | 06-21-2012 |
20130294553 | APPARATUSES FOR ADJUSTING A BANDWIDTH AND COEFFICIENT VALUES OF A RECEIVER IN A WIRELESS NETWORK - A receiver has a bandwidth. The receiver includes paths, a first receiver module, an enable module, and a second receiver module. The paths are configured to be enabled to receive signals. The first receiver module is configured to, prior to the receiver receiving the signals, detect a number of the paths that are enabled to receive a signal. The enable module is configured to, based on the number of the paths detected to have been enabled (i) determine if the signals to be received by the receiver are receivable by a number of the paths less than the number of the paths detected to have been enabled, and (ii) disable, based on a result of the determination, one or more of the paths detected to have been enabled. The second receiver module is configured to, based on the number of the paths enabled, adjust the bandwidth of the receiver. | 11-07-2013 |
Patent application number | Description | Published |
20080291217 | VIEWING AND NAVIGATING WITHIN PANORAMIC IMAGES, AND APPLICATIONS THEREOF - A panorama viewer is disclosed which facilitates navigation from within the panorama of a larger, structured system such as a map. The panorama viewer presents a viewport on a portion of a panoramic image, the viewport including a three-dimensional overlay rendered with the panoramic image. As the orientation of the viewport within the panoramic image changes, the three-dimensional overlay's orientation in three-dimensional space also changes as it is rendered with the panoramic image in a manner that matches the change in orientation of the viewport. | 11-27-2008 |
20110254915 | Three-Dimensional Overlays Within Navigable Panoramic Images, and Applications Thereof - A panorama viewer is disclosed which facilitates navigation from within the panorama of a larger, structured system such as a map. The panorama viewer presents a viewport on a portion of a panoramic image, the viewport including a three-dimensional overlay rendered with the panoramic image. As the orientation of the viewport within the panoramic image changes, the three-dimensional overlay's orientation in three-dimensional space also changes as it is rendered with the panoramic image in a manner that matches the change in orientation of the viewport. | 10-20-2011 |
20140160119 | THREE-DIMENSIONAL OVERLAYS WITHIN NAVIGABLE PANORAMIC IMAGES, AND APPLICATIONS THEREOF - A panorama viewer is disclosed which facilitates navigation from within the panorama of a larger, structured system such as a map. The panorama viewer presents a viewport on a portion of a panoramic image, the viewport including a three-dimensional overlay rendered with the panoramic image. As the orientation of the viewport within the panoramic image changes, the three-dimensional overlay's orientation in three-dimensional space also changes as it is rendered with the panoramic image in a manner that matches the change in orientation of the viewport. | 06-12-2014 |
20150161820 | THREE-DIMENSIONAL OVERLAYS WITHIN NAVIGABLE PANORAMIC IMAGES, AND APPLICATIONS THEREOF - A panorama viewer is disclosed which facilitates navigation from within the panorama of a larger, structured system such as a map. The panorama viewer presents a viewport on a portion of a panoramic image, the viewport including a three-dimensional overlay rendered with the panoramic image. As the orientation of the viewport within the panoramic image changes, the three-dimensional overlay's orientation in three-dimensional space also changes as it is rendered with the panoramic image in a manner that matches the change in orientation of the viewport. | 06-11-2015 |