Patent application number | Description | Published |
20090126901 | EXTERNAL NOISE REDUCTION OF HVAC SYSTEM FOR A VEHICLE - A HVAC system for a vehicle that includes a propulsion system, a frame, a passenger compartment, and a door coupled to the frame. The HVAC system includes a refrigeration circuit that selectively controls the temperature of the passenger compartment based on a sensed temperature within the passenger compartment. The refrigeration circuit includes an exterior heat exchanger, a first air moving device coupled to the exterior heat exchanger, an interior heat exchanger, a second air moving device coupled to the interior heat exchanger, and a compressor. The HVAC system also includes a controller that is operable to detect a condition of the vehicle that includes at least one of a position of the door, a location of the vehicle, and a load of the propulsion system. The controller is programmed to adjust the refrigeration circuit in response to the sensed passenger compartment temperature and the detected vehicle condition. | 05-21-2009 |
20100229581 | SYSTEMS AND METHODS OF POWERING A REFRIGERATION UNIT OF A HYBRID VEHICLE - Systems and methods for providing power to a refrigeration unit or an air conditioner used on a hybrid vehicle. The system includes an accumulation choke, a PWM rectifier, and a frequency inverter. The accumulation choke is configured to receive a first AC power, a second AC power, and a DC power. The accumulation choke and PWM rectifier convert the received power into an intermediate DC power having a peak voltage. The PWM rectifier provides the intermediate DC power to the frequency inverter. The frequency inverter converts the intermediate DC power to an output AC power. The frequency inverter provides the output AC power to the refrigeration unit. | 09-16-2010 |
20110120149 | EXTERNAL NOISE REDUCTION OF HVAC SYSTEM FOR A VEHICLE - A HVAC system for a vehicle that includes a propulsion system, a frame, a passenger compartment, and a door coupled to the frame. The HVAC system includes a refrigeration circuit that selectively controls the temperature of the passenger compartment based on a sensed temperature within the passenger compartment. The refrigeration circuit includes an exterior heat exchanger, a first air moving device coupled to the exterior heat exchanger, an interior heat exchanger, a second air moving device coupled to the interior heat exchanger, and a compressor. The HVAC system also includes a controller that is operable to detect a condition of the vehicle that includes at least one of a position of the door, a location of the vehicle, and a load of the propulsion system. The controller is programmed to adjust the refrigeration circuit in response to the sensed passenger compartment temperature and the detected vehicle condition. | 05-26-2011 |
20120319379 | TRACTOR AND TRAILER COMBINATION - A tractor and trailer combination including a tractor having a tractor frame, a supply unit, a trailer coupling, a skid plate, and a first connector coupled to the tractor frame and coupled to the supply unit to receive at least one of high voltage electrical power and coolant from the supply unit. The combination also includes a trailer having a trailer frame, a tractor coupling rotatably connecting the trailer to the tractor, and a second connector coupled to the trailer and configured to provide the at least one of high voltage electrical power and coolant to the trailer. The combination further includes a conduit having a first end coupled to the first connector, a second end coupled to the second connector. The conduit flexes and is supported between the first and second ends by the skid plate throughout rotation of the trailer relative to the tractor. | 12-20-2012 |
20130091872 | BUCK-BOOST RECTIFIER, REFRIGERATION SYSTEM INCLUDING A BUCK-BOOST RECTIFIER, AND METHOD OF PROVIDING POWER TO A REFRIGERATION UNIT VIA A BUCK-BOOST RECTIFIER - A buck/boost rectifier. The rectifier is connectable to an alternating current power source and includes an upper bus, a lower bus, an upper rectifier, a lower rectifier, a pulse-width-modulation (PWM) controller, a phase-angle (PA) controller, and a capacitor. The upper rectifier is coupled to the upper bus, and the lower rectifier is coupled in a series-type relationship with the upper rectifier and to the lower bus. The PWM controller is coupled to the lower rectifier and is configured to boost a direct current (DC) voltage output by the rectifier. The PA controller is coupled to the lower rectifier and is configured to buck the DC voltage output by the rectifier. The capacitor is coupled between the upper bus and the lower bus. | 04-18-2013 |
Patent application number | Description | Published |
20090200574 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side. A second layer of a second conductivity type is arranged in a central region of the first main side and a fourth electrically conductive layer is arranged on the second layer. On the second main side a third layer with a first zone of the first conductivity type with a higher doping than the first layer is arranged followed by a fifth electrically conductive layer. The area between the second layer and the first zone defines an active area. The third layer includes at least one second zone of the second conductivity type, which is arranged in the same plane as the first zone. A sixth layer of the first conductivity type with a doping, which is lower than that of the first zone and higher that that of the first layer, is arranged between the at least one second zone and the first layer. | 08-13-2009 |
20100244093 | SEMICONDUCTOR MODULE - A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer. | 09-30-2010 |
20100270585 | METHOD FOR MANUFACTURING A REVERSE-CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR - A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask. | 10-28-2010 |
20100276727 | REVERSE-CONDUCTING SEMICONDUCTOR DEVICE - A reverse-conducting semiconductor device is disclosed with an electrically active region, which includes a freewheeling diode and an insulated gate bipolar transistor on a common wafer. Part of the wafer forms a base layer with a base layer thickness. A first layer of a first conductivity type with at least one first region and a second layer of a second conductivity type with at least one second and third region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The RC-IGBT can be configured such that the following exemplary geometrical rules are fulfilled: each third region area is an area, in which any two first regions have a distance bigger (i.e., larger) than two times the base layer thickness; the at least one second region is that part of the second layer, which is not the at least one third region; the at least one third region is arranged in the central part of the active region in such a way that there is a minimum distance between the third region border to the active region border of at least once the base layer thickness; the sum of the areas of the at least one third region is between 10 and 30% of the active region; and each first region width is smaller than the base layer thickness. | 11-04-2010 |
20100301384 | DIODE - A diode for fast switching applications includes a base layer of a first conductivity type with a first main side and a second main side opposite the first main side, an anode layer of a second conductivity type, which is arranged on the second main side, a plurality of first zones of the first conductivity type with a higher doping concentration than the base layer, and a plurality of second zones of the second conductivity type. The first and second zones are arranged alternately on the first main side. A cathode electrode is arranged on top of the first and second zones on the side of the zones which lies opposite the base layer, and a anode electrode is arranged on top of the anode layer on the side of the anode layer which lies opposite the base layer. The base layer includes a first sublayer, which is formed by the second main sided part of the base layer, and a second sublayer, which is formed by the first main sided part of the base layer. A third layer of the first conductivity type is arranged between the first and second sublayers. The third layer has a higher doping concentration than the base layer and a lower doping concentration than the first zones. | 12-02-2010 |
20110108941 | FAST RECOVERY DIODE - A fast recovery diode includes a base layer of a first conductivity type. The base layer has a cathode side and an anode side opposite the cathode side. An anode buffer layer of a second conductivity type having a first depth and a first maximum doping concentration is arranged on the anode side. An anode contact layer of the second conductivity type having a second depth, which is lower than the first depth, and a second maximum doping concentration, which is higher than the first maximum doping concentration, is also arranged on the anode side. A space charge region of the anode junction at a breakdown voltage is located in a third depth between the first and second depths. A defect layer with a defect peak is arranged between the second and third depths. | 05-12-2011 |
20110147880 | POWER SEMICONDUCTOR DEVICE WITH NEW GUARD RING TERMINATION DESIGN AND METHOD FOR PRODUCING SAME - A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer. This spacer sub-region has a width for enabling a reliable alignment of a shadow mask during an ion implantation such that an implanted lifetime control region having carrier lifetime reducing defects may be restricted to a central area while no such defects are implanted into the junction termination region to improve electrical characteristics. | 06-23-2011 |
20110204414 | REVERSE-CONDUCTING SEMICONDUCTOR DEVICE - A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width. Each first pilot region width is equal to or larger than two times the base layer thickness, and the sum of the areas of the second pilot regions is larger than the sum of the areas of the first pilot regions. | 08-25-2011 |
20110278694 | BIPOLAR PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE - A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 μm and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 μm. | 11-17-2011 |
20120280272 | PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration N | 11-08-2012 |
20130026537 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer. | 01-31-2013 |
20130099279 | POWER SEMICONDUCTOR DEVICE - An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer. | 04-25-2013 |
20140034997 | BIPOLAR PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE - A method for manufacturing a bipolar punch-through semiconductor device is disclosed, which includes providing a wafer having a first and a second side, wherein on the first side a high-doped layer of the first conductivity type having constant high doping concentration is arranged; epitaxially growing a low-doped layer of the first conductivity type on the first side; performing a diffusion step by which a diffused inter-space region is created at the inter-space of the layers; creating at least one layer of the second conductivity type on the first side; and reducing the wafer thickness within the high-doped layer on the second side so that a buffer layer is created, which can include the inter-space region and the remaining part of the high-doped layer, wherein the doping profile of the buffer layer decreases steadily from the doping concentration of the high-doped region to the doping concentration of the drift layer. | 02-06-2014 |
20140124829 | INSULATED GATE BIPOLAR TRANSISTOR - An IGBT has layers between emitter and collector sides. The layers include a collector layer on the collector side, a drift layer, a base layer of a second conductivity type, a first source region arranged on the base layer towards the emitter side, a trench gate electrode arranged lateral to the base layer and extending deeper into the drift layer than the base layer, a well arranged lateral to the base layer and extending deeper into the drift layer than the base layer, an enhancement layer surrounding the base layer so as to completely separate the base layer from the drift layer and the well, an electrically conducting layer covering the well and separated from the well by a second electrically insulating layer, and a third insulating layer having a recess on top of the electrically conducting layer such that the electrically conducting layer electrically contacts a emitter electrode. | 05-08-2014 |
20140124830 | INSULATED GATE BIPOLAR TRANSISTOR - An IGBT has layers between emitter and collector sides, including a drift layer, a base layer electrically contacting an emitter electrode and completely separated from the drift layer, first and second source regions arranged on the base layer towards the emitter side and electrically contacting the emitter electrode, and first and second trench gate electrodes. The first trench gate electrodes are separated from the base layer, the first source region and the drift layer by a first insulating layer. A channel is formable between the emitter electrode, the first source region, the base layer and the drift layer. A second insulating layer is arranged on top of the first trench gate electrodes. An enhancement layer separates the base layer from the drift layer. The second trench gate electrode is separated from the base layer, the enhancement layer and the drift layer by a third insulating layer. | 05-08-2014 |
20140124831 | INSULATED GATE BIPOLAR TRANSISTOR - An IGBT has layers between emitter and collector sides. The layers include a drift layer, a base layer electrically contacting an emitter electrode and separated from the drift layer, a first source region arranged on the base layer towards the emitter side and electrically contacting the emitter electrode, and a first trench gate electrode arranged lateral to the base layer and separated from the base layer, the first source region and the drift layer by a first insulating layer. A channel exits between the emitter electrode, the first source region, the base layer and the drift layer. A second insulating layer is arranged on top of the first trench gate electrode. An enhancement layer separates the base layer from the drift layer in a plane parallel to the emitter side. A grounded gate electrode includes a second, grounded trench gate electrode and an electrically conducting layer. | 05-08-2014 |
20140320178 | INTELLIGENT GATE DRIVER FOR IGBT - A reverse-conducting insulated gate bipolar transistor, particularly a bi-mode insulated gate transistor, is controlled by responding to an ON command by applying high-level gate voltage for a first period, during which a current is fed into a connection point, from which it flows either through the RC-IGBT or along a different path. Based hereon, it is determined whether the RC-IGBT conducts in its forward/IGBT or reverse/diode mode, and the RC-IGBT is either driven at high or low gate voltage. Subsequent conduction mode changes may be monitored in the same way, and the gate voltage may be adjusted accordingly. A special turn-off procedure may be applied in response to an OFF command in cases where the RC-IGBT conducts in the reverse mode, wherein a high-level pulse is applied for a second period before the gate voltage goes down to turn-off level. | 10-30-2014 |