Patent application number | Description | Published |
20100258841 | BACK DIFFUSION SUPPRESSION STRUCTURES - An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer. | 10-14-2010 |
20100258842 | ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS - An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å. | 10-14-2010 |
20100258843 | ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME - An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process. | 10-14-2010 |
20100258844 | BUMPED, SELF-ISOLATED GaN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE - A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device. | 10-14-2010 |
20100258848 | COMPENSATED GATE MISFET AND METHOD FOR FABRICATING THE SAME - A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer. | 10-14-2010 |
20100258912 | DOPANT DIFFUSION MODULATION IN GaN BUFFER LAYERS - A semi-conductor crystal and method of forming the same. The method includes providing a flow of dopant and column III element containing gases, then stopping flow of dopant and column III element containing gases, reducing the temperature, restarting flow of column III containing gases and then elevating the temperature. | 10-14-2010 |
20110248283 | VIA STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor devices, such as GaN HEMT and HFET devices, and methods of forming such devices, with a via that provides an electrical connection between a contact and a corresponding external contact pad. Embodiments include semiconductor devices with a via extending through a dielectric material to connect a gate to a corresponding external contact pad, and semiconductor devices with a via extending through a dielectric material to connect an Ohmic contact and a corresponding external contact pad. Embodiments also include semiconductor devices with a via connecting an external contact pad to a gate that is formed above a dielectric material. | 10-13-2011 |
20120153300 | SEMICONDUCTOR DEVICES WITH BACK SURFACE ISOLATION - Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided. | 06-21-2012 |
20120175631 | ENHANCEMENT MODE GaN HEMT DEVICE WITH GATE SPACER AND METHOD FOR FABRICATING THE SAME - Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability. | 07-12-2012 |
20120193688 | ION IMPLANTED AND SELF ALIGNED GATE STRUCTURE FOR GaN TRANSISTORS - A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer. | 08-02-2012 |
20130234153 | ENHANCEMENT MODE GaN HEMT DEVICE - An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process. | 09-12-2013 |
20140106548 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 04-17-2014 |
20140264373 | III-Nitride Heterojunction Device - A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. | 09-18-2014 |
20150028384 | GaN TRANSISTORS WITH POLYSILICON LAYERS FOR CREATING ADDITIONAL COMPONENTS - A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer. | 01-29-2015 |
20150028390 | GaN DEVICE WITH REDUCED OUTPUT CAPACITANCE AND PROCESS FOR MAKING SAME - A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor. | 01-29-2015 |
20150034962 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 02-05-2015 |
20150037965 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 02-05-2015 |
20150132933 | III-Nitride Semiconductor Device Fabrication - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 05-14-2015 |
20150270241 | FLIP CHIP INTERCONNECTION WITH REDUCED CURRENT DENSITY - A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device. | 09-24-2015 |
20150357182 | Fabrication of III-Nitride Power Semiconductor Device - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 12-10-2015 |
20160027643 | Fabrication of Semiconductor Device Using Alternating High and Low Temperature Layers - A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps. | 01-28-2016 |
20160086980 | GAN TRANSISTORS WITH POLYSILICON LAYERS USED FOR CREATING ADDITIONAL COMPONENTS - A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer. | 03-24-2016 |
20160111416 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 04-21-2016 |
Patent application number | Description | Published |
20080259836 | Power Saving Function for Wireless LANs: Methods, System and Program Products - A wireless data communication system has a first station or mobile unit is linked to a second station configured as an access unit to support packet communication, voice or data, where the voice packets are transmitted in the Continuously Aware Mode (CAM) mode while other packets are buffered by the access point and held until asked for by the first station when in a Power Saving-Poll (PSP) mode. A monitoring apparatus at the access point monitors all transmitted packets and sorts the packets to the mobile unit according to CAM or PSP mode. Voice packets are sent out immediately to the mobile unit. Other packets are stored at the access point. The packet arrival rate may vary during transmission and due to random packet delays introduced by propagation characteristic and processing apparatus. The packet arrival rate and delays are taken into account by the first station in an algorithm to determine and extend the normal safe period in which the station receiver may be powered off. | 10-23-2008 |
20090009585 | WLAN Communications System - A wireless local area network audio and video communication system with mobile units is provided, wherein mobile units are operated in a power saving mode and become active at selected intervals corresponding to the duration of audio and video signals forming audio and video data packets. In a preferred arrangement the mobile units have a digital signal processor that operates at different clock rates during different portions of the intervals. | 01-08-2009 |
20090296671 | COMMUNICATIONS BETWEEN A CLIENT DEVICE AND AN INFRASTRUTURE DEVICE - Techniques are provided for communicating information between a wireless client device (CD) and an infrastructure device (ID) in a WLAN in which the CD wirelessly communicates with the ID in IBSS mode over a pseudo-BSS/IBSS air interface. The CD includes a WLAN NIC that operates in IBSS mode and a client host system that includes a client custom driver module (CCDM) and a WLAN NIC driver module configured to operate in IBSS mode. The ID includes a hardware interface and a host system which includes a packet separation driver module (PSDM) and an infrastructure custom driver module (ICDM). The CD operates in pseudo-BSS/IBSS mode (PBIM). The CCDM provides pseudo BSS-like service(s) with respect to packets generated by upper protocol layer modules to generate pseudo-BSS-like packets that it provides to the WLAN NIC via WLAN NIC driver module. Based on the pseudo-BSS-like packets, the WLAN NIC generates PBIM packets and transmits them. The PSDM receives packets from the hardware interface and separates them. When the PSDM receives PBIM packets, the PDSM sends the PBIM packets to the ICDM which performs one or more BSS-like services with respect to the PBIM packets. | 12-03-2009 |
20090296672 | METHODS FOR WIRELESSLY COMMUNICATING INFORMATION BETWEEN A CLIENT DEVICE AND AN INFRASTRUCTURE DEVICE - Techniques are provided for communicating information between a wireless client device (CD) and an infrastructure device (ID) in a WLAN in which the CD wirelessly communicates with the ID in IBSS mode over a pseudo-BSS/IBSS air interface. The CD includes a WLAN NIC that operates in IBSS mode and a client host system that includes a client custom driver module (CCDM) and a WLAN NIC driver module configured to operate in IBSS mode. The ID includes a hardware interface and a host system which includes a packet separation driver module (PSDM) and an infrastructure custom driver module (ICDM). The CD operates in pseudo-BSS/IBSS mode (PBIM). The CCDM provides pseudo BSS-like service(s) with respect to packets generated by upper protocol layer modules to generate pseudo-BSS-like packets that it provides to the WLAN NIC via WLAN NIC driver module. Based on the pseudo-BSS-like packets, the WLAN NIC generates PBIM packets and transmits them. The PSDM receives packets from the hardware interface and separates them. When the PSDM receives PBIM packets, the PDSM sends the PBIM packets to the ICDM which performs one or more BSS-like services with respect to the PBIM packets. | 12-03-2009 |
20090296673 | APPARATUS FOR IMPLEMENTING A PSEUDO-BASIC SERVICE SET (BSS)-LIKE NETWORK OVER AN INDEPENDENT BASIC SERVICE SET (IBSS) MODE AIR INTERFACE - Techniques are provided for communicating information between a wireless client device (CD) and an infrastructure device (ID) in a WLAN in which the CD wirelessly communicates with the ID in IBSS mode over a pseudo-BSS/IBSS air interface. The CD includes a WLAN NIC that operates in IBSS mode and a client host system that includes a client custom driver module (CCDM) and a WLAN NIC driver module configured to operate in IBSS mode. The ID includes a hardware interface and a host system which includes a packet separation driver module (PSDM) and an infrastructure custom driver module (ICDM). The CD operates in pseudo-BSS/IBSS mode (PBIM). The CCDM provides pseudo BSS-like service(s) with respect to packets generated by upper protocol layer modules to generate pseudo-BSS-like packets that it provides to the WLAN NIC via WLAN NIC driver module. Based on the pseudo-BSS-like packets, the WLAN NIC generates PBIM packets and transmits them. The PSDM receives packets from the hardware interface and separates them. When the PSDM receives PBIM packets, the PDSM sends the PBIM packets to the ICDM which performs one or more BSS-like services with respect to the PBIM packets. | 12-03-2009 |
20100128710 | INFRASTRUCTURE FOR WIRELESS LANS - A wireless data communications system includes simplified access points which are connected to ports of an intelligent switching hub. The switching hub relays data packets to the access points in accordance with destination address data in the data communications. In a preferred arrangement the access points are provided with power over the data cable from the switching hub location. | 05-27-2010 |
Patent application number | Description | Published |
20080248634 | ENHANCEMENT MODE III-NITRIDE FET - A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device. | 10-09-2008 |
20080274621 | III-Nitride semiconductor device with trench structure - A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications. | 11-06-2008 |
20080296621 | III-nitride heterojunction device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 12-04-2008 |
20090001424 | III-nitride power device - A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device. | 01-01-2009 |
20090065785 | III-nitride power semiconductor device - A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions. | 03-12-2009 |
20100006895 | III-NITRIDE SEMICONDUCTOR DEVICE - A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction. | 01-14-2010 |
20110143517 | III-Nitride Monolithic IC - III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures. | 06-16-2011 |
20110241019 | III-Nitride Power Semiconductor Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 10-06-2011 |
20110244671 | Method for Fabricating a III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 10-06-2011 |
20110275183 | Enhancement Mode III-Nitride FET - A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device. | 11-10-2011 |
20130240911 | III-Nitride Multi-Channel Heterojunction Device - A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. | 09-19-2013 |
20130248884 | III-Nitride Power Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 09-26-2013 |
20130256695 | III-Nitride Heterojunction Device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 10-03-2013 |
20130264579 | III-Nitride Heterojunction Device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 10-10-2013 |
20140030858 | Enhancement Mode III-Nitride Device - A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device. | 01-30-2014 |
20140038391 | III-Nitride Wafer Fabrication - A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof. | 02-06-2014 |