Patent application number | Description | Published |
20080248601 | Method of fusing trimming for semiconductor device - Deviation occurring in a particular region in a plane of a resistor group which constitutes a semiconductor integrated circuit is improved and a quick increase in yield is accomplished. Provided is a fuse trimming method for a semiconductor device in which circuit elements such as transistors and resistors are formed on a semiconductor wafer and which has fuse elements capable of adjusting a resistance value of the resistors by laser trimming, including a resistor correction step of correcting in the particular region of the semiconductor wafer the resistance value of the resistors based on an amount of deviation from a target value of the resistance value of the resistors. | 10-09-2008 |
20090014765 | High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region. | 01-15-2009 |
20090014816 | High voltage operating field effect transistor, and bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential. | 01-15-2009 |
20090061620 | Method of manufacturing a semiconductor device - Exuding of a interconnecting material to a substrate, which occurs because of a thinned state of and a beak in a barrier metal layer is prevented, irrespective of a laminated state of the barrier metal layer. In the present invention, a protective layer is formed on a side wall by using an insulating film or the like after the deposition of the barrier metal layer, whereby the interconnecting material can be prevented from exuding to the substrate due to influence of heat treatment such as alloying, irrespective of the laminated state of the side wall of the contact hole and the barrier metal layer. Further, the formation of the protective layer allows the side wall to be smoother to thereby improve coverage of the interconnecting material at the same time. | 03-05-2009 |
20090101973 | Field effect transistor formed on an insulating substrate and integrated circuit thereof - A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation. | 04-23-2009 |
20090156009 | Method for manufacturing semiconductor device - Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with respect to the first film; etching a region of a part of the second film and the first film to expose a surface of the semiconductor substrate in the region; and etching the exposed surface of the semiconductor substrate to form a trench. | 06-18-2009 |
20090200613 | SEMICONDUCTOR DEVICE - A transistor having a perpendicular channel direction and a transistor having a parallel channel direction are combined to cancel out stress-induced change in a characteristic value, providing a semiconductor device whose shift in characteristic value is small. Consequently, a channel that runs in a direction perpendicular to one side of a semiconductor chip is formed in one transistor ( | 08-13-2009 |
20100001377 | Semiconductor device - A semiconductor device ( | 01-07-2010 |
20100044765 | SEMICONDUCTOR DEVICE - Provided is a metal oxide semiconductor (MOS) capacitor, in which trenches ( | 02-25-2010 |
20100059832 | Semiconductor device - Provided is a semiconductor device including a depletion type MOS transistor and an enhancement type MOS transistor. In the semiconductor device, in order to provide a reference voltage generating circuit having an enhanced temperature characteristic or analog characteristic without increasing an area of the semiconductor device through addition of a circuit, well regions of the depletion type MOS transistor and the enhancement type MOS transistor, which have different concentrations from each other, are formed. | 03-11-2010 |
20120187476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Trench portions ( | 07-26-2012 |
20130016563 | MEMORY CIRCUITAANM OSANAI; JunAACI Chiba-shiAACO JPAAGP OSANAI; Jun Chiba-shi JPAANM Hirose; YoshitsuguAACI Chiba-shiAACO JPAAGP Hirose; Yoshitsugu Chiba-shi JPAANM Tsumura; KazuhiroAACI Chiba-shiAACO JPAAGP Tsumura; Kazuhiro Chiba-shi JPAANM Inoue; AyakeAACI Chiba-shiAACO JPAAGP Inoue; Ayake Chiba-shi JP - Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit ( | 01-17-2013 |