Patent application number | Description | Published |
20080247249 | Circuit and method for a sense amplifier - A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided. | 10-09-2008 |
20090290446 | Memory Word-line Tracking Scheme - A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter. | 11-26-2009 |
20100103719 | Two-Stage 8T SRAM Cell Design - An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node. | 04-29-2010 |
20100238753 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage. | 09-23-2010 |
20100259999 | KEEPERS, INTEGRATED CIRCUITS, AND SYSTEMS THEREOF - A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter. | 10-14-2010 |
20110019458 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ROUTING THE MEMORY CIRCUITS - A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array. | 01-27-2011 |
20110019460 | MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines. | 01-27-2011 |
20110063894 | SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line | 03-17-2011 |
20110090753 | POWER MANAGEMENT - An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power. | 04-21-2011 |
20110158007 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 06-30-2011 |
20110188326 | DUAL RAIL STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control. | 08-04-2011 |
20110199839 | WEAK BIT COMPENSATION FOR STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, wherein the current path block is connected to the data line and the data line bar. | 08-18-2011 |
20110242904 | Read Only Memory and Operating Method Thereof - A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages. | 10-06-2011 |
20120014158 | MEMORY DEVICES - A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time. | 01-19-2012 |
20120020176 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain. | 01-26-2012 |
20120020179 | METHOD AND APPARATUS FOR WORD LINE DECODER LAYOUT - A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines. | 01-26-2012 |
20120061764 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas. | 03-15-2012 |
20120092939 | SINGLE-ENDED SENSING SCHEME FOR MEMORY - A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground. | 04-19-2012 |
20120106269 | MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME - The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver. | 05-03-2012 |
20120106286 | MEMORY CIRCUIT HAVING DECODING CIRCUITS AND METHOD OF OPERATING THE SAME - The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals. | 05-03-2012 |
20120147688 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage. | 06-14-2012 |
20120182792 | BIASING CIRCUIT AND TECHNIQUE FOR SRAM DATA RETENTION - A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply. | 07-19-2012 |
20120195139 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 08-02-2012 |
20120206953 | MEMORY EDGE CELL - A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively. | 08-16-2012 |
20130003445 | SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line | 01-03-2013 |
20130010516 | MEMORY CHIP WITH MORE THAN ONE TYPE OF MEMORY CELL - A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines. | 01-10-2013 |
20130010560 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node. | 01-10-2013 |
20130028008 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - A memory array including at least one cross-latched pair of transistors for storing data. The memory array further includes a first power line for supplying a first reference voltage and a second power line for supplying a second reference voltage. The memory array further includes a first switch having a first output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the first power line. The memory array further includes a second switch having a second output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the second power line. The first output is coupled to the second output. | 01-31-2013 |
20130051130 | WEAK BIT COMPENSATION FOR STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) is provided. The SRAM includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, wherein the current path block is connected to the data line and the data line bar during an entire duration of operation of the SRAM. | 02-28-2013 |
20130188417 | MEMORY CIRCUIT AND METHOD FOR ROUTING THE MEMORY CIRCUIT - A memory circuit includes a first row of memory cells, a first word line and a second word line over and electrically coupled to the first row of memory cells, a second row of memory cells aligned with the first row of memory cells along a predetermined direction, and a third word line and a fourth word line over and electrically coupled to the second row of memory cells. The first word line is aligned with the third word line, and the second word line is aligned with the fourth word line. One of the first word line or the second word line is electrically coupled with one of the third word line or the fourth word line. The other one of the first word line or the second word line is electrically decoupled from the other one of the third word line or fourth word line. | 07-25-2013 |
20130194877 | MEMORY AND METHOD OF OPERATING THE SAME - A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit. | 08-01-2013 |
20130208533 | MEMORY HAVING READ ASSIST DEVICE AND METHOD OF OPERATING THE SAME - A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage. | 08-15-2013 |
20130258747 | METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT - A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold. | 10-03-2013 |
20130286708 | MEMORY EDGE CELL - A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell. | 10-31-2013 |
20130311964 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device. | 11-21-2013 |
20140035664 | VOLTAGE PROVIDING CIRCUIT - A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage. | 02-06-2014 |
20140084374 | CELL DESIGN - One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate to gate distance is selected based on a first gate to gate distance. For example, the first gate to gate distance and the second gate to gate distance are associated with a first transistor. In another example, the first gate to gate distance is associated with a first transistor and the second gate to gate distance is associated with a second transistor. In this manner, a cell design is provided to improve a static noise margin (SNM) or a write margin (WM) for the cell, for example. | 03-27-2014 |
20140092695 | HEADER CIRCUIT FOR CONTROLLING SUPPLY VOLTAGE OF A CELL - One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example. | 04-03-2014 |
20140146631 | VCCMIN FOR A DUAL PORT SYNCHRONOUS RANDOM ACCESS MEMORY (DPSRAM) CELL UTILIZED AS A SINGLE PORT SYNCHRONOUS RANDOM ACCESS MEMORY (SPSRAM) CELL - One or more techniques for improving Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell are provided herein. In some embodiments, a second word line signal is sent to a second word line of the DPSRAM cell. For example, the second word line signal is sent in response to a logical low at a first bit line or a logical low at a second bit line. In this way, Vccmin is improved for the DPSRAM cell. | 05-29-2014 |
20140233330 | WRITE ASSIST CIRCUIT, MEMORY DEVICE AND METHOD - A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state. | 08-21-2014 |
20140266436 | Sense Amplifier - The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed. | 09-18-2014 |
20140269110 | ASYMMETRIC SENSING AMPLIFIER, MEMORY DEVICE AND DESIGNING METHOD - A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current. | 09-18-2014 |
20140269114 | CIRCUIT FOR MEMORY WRITE DATA OPERATION - A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage. | 09-18-2014 |
20140269115 | Integrated Write Mux and Driver Systems and Methods - An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals. | 09-18-2014 |
20140269128 | SENSE AMPLIFIER - A sense amplifier includes a cross latch, a first pass gate, a second pass gate, a first data line, a second data line, a first circuit, and a second circuit. The cross latch has a first input/output (I/O) node and a second I/O node. The first pass gate is coupled between the first data line and the first I/O node. The second pass gate is coupled between the second data line and the second I/O node. The first circuit is coupled with the first I/O node and the second data line. The second circuit is coupled with the second I/O node and the first data line. The first circuit is configured to be turned off when the second data line has a first logical value and to be at least lightly turned on when the second data line has a voltage level between the first logical value and a second logical value different from the first logical value. The second circuit is configured to be turned off when the first data line has the first logical value and to be at least lightly turned on when the first data line has a voltage level between the first logical value and the second logical value. | 09-18-2014 |
20150048869 | CIRCUIT AND METHOD FOR POWER MANAGEMENT - A method comprises identifying a number of power domains in a device, connecting the power domains to each other by a number of control devices during a wake-up mode of the device, and disconnecting the power domains after the wake-up mode of the device. | 02-19-2015 |
20150058664 | DYNAMIC MEMORY CELL REPLACEMENT USING COLUMN REDUNDANCY - A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation. | 02-26-2015 |