Patent application number | Description | Published |
20080298126 | NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR REPLACING DEFECTIVE BLOCKS THEREOF - A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence. | 12-04-2008 |
20130015915 | SEMICONDUCTOR DEVICEAANM KOMATSU; YukioAACI Kanagawa-kenAACO JPAAGP KOMATSU; Yukio Kanagawa-ken JPAANM Ohta; HitoshiAACI Kanagawa-kenAACO JPAAGP Ohta; Hitoshi Kanagawa-ken JPAANM Awano; DaisukeAACI Kanagawa-kenAACO JPAAGP Awano; Daisuke Kanagawa-ken JP - A semiconductor device including: a first pad to receive first and second test commands supplied from the outside; a voltage generator circuit to generate a test target voltage on the basis of the first and second test commands; a second pad to receive first and second monitor voltages supplied from the outside in response to respective of the first and second test commands, the first and second monitor voltages corresponding to respective lower and upper limit voltages of the test target voltage; and a comparator to output a first output signal at one of first and second logical levels by comparing the test target voltage with the first monitor voltage, and to output a second output signal at one of the first and second logical levels by comparing the test target voltage with the second monitor voltage. | 01-17-2013 |
20130286752 | SEMICONDUCTOR MEMORY - A semiconductor memory according to one embodiment includes: a memory cell array including a plurality of memory cells storing data, a first buffer circuit for inputting/outputting data to and from the first memory cell array, a data transfer circuit connected with the first buffer circuit via the first data bus and configured to control data transfer, and a control circuit configured to control a first mode and a second mode. The data transfer circuit performs control such that a bus width of the first data bus differs between the first mode and the second mode. | 10-31-2013 |
Patent application number | Description | Published |
20090032875 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode. | 02-05-2009 |
20120241854 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film. | 09-27-2012 |
20120241896 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface. | 09-27-2012 |
20120241898 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of the first conductivity type and a second electrode. The first semiconductor region includes a first portion including a first major surface and a second portion extending in a first direction perpendicular to the first major surface on the first major surface. The first electrode includes a third portion provided to face the second portion and is provided to be separated from the first semiconductor region. The second semiconductor region is provided between the second and third portions, includes a first concentration region having a lower impurity concentration than the first semiconductor region and forms a Schottky junction with the third portion. The second electrode is provided on an opposite side of the first major surface and in conduction with the first portion. | 09-27-2012 |
20130069147 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region. | 03-21-2013 |
20130069151 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a substrate; a first conductive portion extending in a first direction perpendicular to a major surface of the substrate; a second conductive portion extending in the first direction; a semiconductor portion provided between the first and the second conductive portions and including a first semiconductor region; a first electrode portion extending in the first direction between the first and the second conductive portions; a second electrode portion extending in the first direction between the first and the second conductive portions; a first insulting portion provided between the first electrode portion and the semiconductor portion and having a first thickness; and a second insulating portion provided between the second electrode portion and the semiconductor portion and having a second thickness greater than the first thickness. | 03-21-2013 |