Hosseini
Abbas S. Hosseini, Richmond Hill CA
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20110182306 | GENERATION OF BURST OF LASER PULSES - This invention relates to a method for generating bursts of laser pulses and to an apparatus for generating bursts of laser pulses and to a Pockels cell driving circuit. A method for generating bursts of laser pulses comprising generating first repetition rate laser pulses, and generating first repetition rate laser bursts from the repetition laser pulses, the laser bursts each containing a sequence of second repetition rate laser pulses, wherein the second repetition rate is higher than the first repetition rate. | 07-28-2011 |
Abdollah Hosseini, Tehran IR
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20130206236 | INTELLIGENT EMERGENCY SHUT DOWN SYSTEM AND A METHOD FOR EMERGENCY CLOSING AND REGULATION OF FLUID STREAM IN FLUID STORAGE AND DISPENSING SYSTEMS DURING EARTHQUAKE - The various embodiments herein disclose a system and a method for regulating a flow of fluid stream in fluid storage and dispensing systems. The system comprising a valve arrangement including a compressed air unit bloated by a connecting air inlet tube, a frame and a valve elevating means to mount the valve arrangement on the frame, several sensors to detect one crisis factor, a communication unit, a data logger and processing unit, a remote management system and several actuators to regulate the operation of the valve arrangement. The valve arrangement shuts down the outflow of fluid stream on receiving a valve shutdown signal from one of the sensors and data processing unit in case of a crisis detection. The data processing unit informs the remote management system to take adequate safety measures through the communication unit. | 08-15-2013 |
Amir Hosseini, Austin, TX US
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20130005606 | Packaged chip for multiplexing photonic crystal waveguide and photonic crystal slot waveguide devices for chip-integrated label-free detection and absorption spectroscopy with high throughput, sensitivity, and specificity - Systems and methods for chip-integrated label-free detection and absorption spectroscopy with high throughput, sensitivity, and specificity are disclosed. The invention comprises packaged chips for multiplexing photonic crystal waveguide and photonic crystal slot waveguide devices. Other embodiments are described and claimed. | 01-03-2013 |
20140140655 | Packaged Chip For Multiplexing Photonic Crystal Microcavity Coupled Waveguide And Photonic Crystal Slot Waveguide Devices For Chip-Integrated Label-Free Detection And Absorption Spectroscopy With High Throughput, Sensitivity, Specificity, And Wide Dynamic Range - Systems and methods for chip-integrated label-free detection and absorption spectroscopy with high throughput, sensitivity, and specificity are disclosed. The invention comprises packaged chips for multiplexing photonic crystal microcavity waveguide and photonic crystal slot waveguide devices. The packaged chips comprise crossing waveguides to prevent leakage of fluids from the microfluidic channels from the trenches or voids around the light guiding waveguides. Other embodiments are described and claimed. | 05-22-2014 |
20140141999 | Method for Chip-Integrated Label-Free Detection and Absorption Spectroscopy with High Throughput, Sensitivity, and Specificity - Systems and methods for chip-integrated label-free detection and absorption spectroscopy with high throughput, sensitivity, and specificity are disclosed. The invention comprises packaged chips for multiplexing photonic crystal waveguide and photonic crystal slot waveguide devices. Other embodiments are described and claimed. | 05-22-2014 |
Dawood Hosseini, Tehran IR
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20090324486 | Fabrication of NiO nanoparticles and chip-like nanoflakes by solvothermal technique - A method is disclosed for fabrication of NiO nanoparticles and NiO chip-like nanoflakes by solvothermal technique. Mixed organic alcohols were used as solvent to make a homogenous solution from a nickel containing salt (or complex) for production of NiO nanoparticles and chip-like nanoflakes. The solution was heated in a sealed flask sitting inside a warm furnace. The precipitate was filtered, rinsed, dried and calcined to produce nanoparticles or nanoflakes. The size of the particles was controllable by heating time and temperature. Similar procedures were used for production of both nanostructures except hydrogen peroxide addition to the initial solution for NiO chip-like nanoflakes fabrication. | 12-31-2009 |
Ehsan Sha Hosseini, Cambridge, MA US
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20140269800 | PHOTONIC DEVICES AND METHODS OF USING AND MAKING PHOTONIC DEVICES - Examples of the present invention include integrated erbium-doped waveguide lasers designed for silicon photonic systems. In some examples, these lasers include laser cavities defined by distributed Bragg reflectors (DBRs) formed in silicon nitride-based waveguides. These DBRs may include grating features defined by wafer-scale immersion lithography, with an upper layer of erbium-doped aluminum oxide deposited as the final step in the fabrication process. The resulting inverted ridge-waveguide yields high optical intensity overlap with the active medium for both the 980 nm pump (89%) and 1.5 μm laser (87%) wavelengths with a pump-laser intensity overlap of over 93%. The output powers can be 5 mW or higher and show lasing at widely-spaced wavelengths within both the C- and L-bands of the erbium gain spectrum (1536, 1561 and 1596 nm). | 09-18-2014 |
Farid Hosseini, Redmond, WA US
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20100299343 | Identifying Task Groups for Organizing Search Results - Computer-readable media and computerized methods for automatically organizing search results according to task groups are provided. The methods involve aggregating a gallery of entities (e.g., search queries that share a common categorization) into a query class and assigning a dictionary (e.g., list of terms that are drawn from various sources) to the query class. The task groups are identified from the list of terms within the dictionary. The process of identification includes analyzing patterns of user search behavior to select terms from the list of terms, which reflect popular user search intents, and ranking the selected terms based on predetermined parameters to produce an ordering. Based on the ordering, a set of the selected terms that are highest ranked are declared the task groups. The task groups are employed to arrange the search results on a UI display and to provide a consistent and intuitive format for refining a search. | 11-25-2010 |
20110320470 | GENERATING AND PRESENTING A SUGGESTED SEARCH QUERY - The present invention is directed to presenting a suggested search query. Responsive to receiving a user-devised search parameter, a suggested search query is identified. The user-devised search parameter might have been previously received by a search system, or alternatively, might be a unique query that has not been previously received. A suggested search query might be generated using various techniques, such as by applying an n-gram language model. A classification of the suggested search query is determined, and the suggested search query is presented together with a visual indicator, which signifies the classification. | 12-29-2011 |
20120096033 | Disambiguation of Entities - Methods, systems, algorithms, and media are provided for disambiguating entities present in a received search query. Lists of categories from semi-structured data from external sites as well as internal sources are used to detect if ambiguity exists in an entity within the search query. Multiple senses or categories of the ambiguous entity are determined by ascertaining the primary intent of an entity extracted from a main term of a document. The probability of each sense is calculated by computing a total amount of traffic received for each of the senses of the ambiguous entity. The sense with the highest amount of computed traffic is the most probable determined sense. | 04-19-2012 |
20120158702 | Classifying Results of Search Queries - Computer-readable media, computer systems, and computing methods are provided for classifying search results as either of good quality or of poor quality. Initially, a portion of the search results, such as the highest ranked documents, are selected for evaluation. A level of quality for each of the selected search results is determined using a classification process that includes the following steps: targeting features demonstrated by the selected search results to be evaluated; evaluating the selected features to generate a level-of-quality score for each of the selected search results; comparing the score against a predefined threshold value; and, based on the comparison, assigning each of the selected search results an absolute measurement. The absolute measurement indicates poor quality when the score is less than the threshold value. Upon recognizing that the selected search results are of poor quality, automatically executing a corrective action that reformulates the issued search query. | 06-21-2012 |
20120158765 | User Interface for Interactive Query Reformulation - Computer-readable media, computer systems, and computing methods are provided for classifying search results as either of good quality or of poor quality. Initially, a portion of the search results, such as the highest ranked documents, are selected for evaluation. A level of quality for each of the selected search results is determined using a classification process that includes the following steps: targeting features demonstrated by the selected search results to be evaluated; evaluating the selected features to generate a level-of-quality score for each of the selected search results; comparing the score against a predefined threshold value; and, based on the comparison, assigning each of the selected search results an absolute measurement. The absolute measurement indicates poor quality when the score is less than the threshold value. Upon recognizing that the selected search results are of poor quality, a corrective action that reformulates the issued search query is automatically invoked. | 06-21-2012 |
20120209835 | Identifying Task Groups for Organizing Search Results - Computer-readable media and computerized methods for automatically organizing search results according to task groups are provided. The methods involve aggregating a gallery of entities (e.g., search queries that share a common categorization) into a query class and assigning a dictionary (e.g., list of terms that are drawn from various sources) to the query class. The task groups are identified from the list of terms within the dictionary. The process of identification includes analyzing patterns of user search behavior to select terms from the list of terms, which reflect popular user search intents, and ranking the selected terms based on predetermined parameters to produce an ordering. Based on the ordering, a set of the selected terms that are highest ranked are declared the task groups. The task groups are employed to arrange the search results on a UI display and to provide a consistent and intuitive format for refining a search. | 08-16-2012 |
20140025664 | IDENTIFYING TERMS ASSOCIATED WITH QUERIES - Computer-readable media and computerized methods are provided for identifying terms associated with one or more queries, including aspects directed to manipulating a list of terms associated with a query class by extracting terms, identifying equivalences or relevant terms, and condensing or expanding the list of terms. In embodiments, synonymous terms can be identified. An updated list of terms can be written to a storage location in association with a query or query class. | 01-23-2014 |
Kahlil Hosseini, Weihmichl DE
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20140220742 | METHOD FOR FORMING A THIN SEMICONDUCTOR DEVICE - A method for forming a thin semiconductor device is disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection. | 08-07-2014 |
Kaveh Hosseini, Rochestown IE
Patent application number | Description | Published |
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20130278334 | SLEW RATE AND BANDWIDTH ENHANCEMENT IN RESET - Embodiments of a capacitance sensing system including an integrating amplifier and methods for operating the same to provide a higher slew rate and bandwidth are described. In one embodiment, the integrating amplifier comprises an input stage including an inverting input coupled to an electrode of a capacitor to sense a capacitance and a non-inverting input coupled to a reference potential, and an output stage including a compensating capacitor coupled to an output. The compensating capacitor comprises two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in a RESET mode decoupling one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor. | 10-24-2013 |
Kaveh Hosseini, Cork IE
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20150162932 | Tunable Baseline Compensation Scheme for Touchscreen Controllers - A method for compensating for panel capacitance the associated current is proposed, wherein the mutual capacitances of a capacitance sensing array are selectively coupled to drive voltages and to a self capacitance under test. | 06-11-2015 |
Khalil Hosseini, Weihmichl DE
Patent application number | Description | Published |
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20080258277 | Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same - A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and external terminals to one another. | 10-23-2008 |
20090051016 | ELECTRONIC COMPONENT WITH BUFFER LAYER - An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip. | 02-26-2009 |
20100213613 | ARRANGEMENT FOR ELECTRICALLY CONNECTING SEMICONDUCTOR CIRCUIT ARRANGEMENTS TO AN EXTERNAL CONTACT DEVICE AND METHOD FOR PRODUCING THE SAME - An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability. | 08-26-2010 |
20110285033 | Chip Carrier - Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location. | 11-24-2011 |
20110291252 | METHOD AND SYSTEM FOR FORMING A THIN SEMICONDUCTOR DEVICE - A method and system for forming a thin semiconductor device are disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection. | 12-01-2011 |
20120025384 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 02-02-2012 |
20120061835 | DIE STRUCTURE, DIE ARRANGEMENT AND METHOD OF PROCESSING A DIE - A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded. | 03-15-2012 |
20120068364 | Device and Method for Manufacturing a Device - A device includes a semiconductor material having a first surface. A first material is applied to the first surface and a fiber material is embedded in the first material. | 03-22-2012 |
20120074553 | METHOD AND SYSTEM FOR IMPROVING RELIABILITY OF A SEMICONDUCTOR DEVICE - A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer. | 03-29-2012 |
20120074568 | METHOD AND SYSTEM FOR MINIMIZING CARRIER STRESS OF A SEMICONDUCTOR DEVICE - A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier. | 03-29-2012 |
20120267784 | Semiconductor Device and Bonding Wire - A semiconductor device includes a semiconductor chip, a contact pad of the semiconductor chip and a first layer arranged over the contact pad. The first layer includes niobium, tantalum or an alloy including niobium and tantalum. | 10-25-2012 |
20120292773 | Method for Producing a Metal Layer on a Substrate and Device - A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation. | 11-22-2012 |
20120327614 | METHOD FOR ATTACHING A METAL SURFACE TO A CARRIER, A METHOD FOR ATTACHING A CHIP TO A CHIP CARRIER, A CHIP-PACKAGING MODULE AND A PACKAGING MODULE - A method for attaching a metal surface to a carrier is provided, the method including: forming a first polymer layer over the metal surface; forming a second polymer layer over a surface of the carrier; and bringing the first polymer layer into physical contact with the second polymer layer such that at least one of an interpenetrating polymer structure and an inter-diffusing polymer structure is formed between the first polymer layer and the second polymer layer. | 12-27-2012 |
20130001803 | METHOD FOR ATTACHING A METAL SURFACE TO A CARRIER, A METHOD FOR ATTACHING A CHIP TO A CHIP CARRIER, A CHIP-PACKAGING MODULE AND A PACKAGING MODULE - A method for attaching a metal surface to a carrier is provided, the method including: depositing a porous layer over at least one of a metal surface and a side of a carrier; and attaching the at least one of a metal surface and a side of a carrier to the porous layer by bringing a material into pores of the porous layer, resulting in the material forming an interconnection between the metal surface and the carrier. | 01-03-2013 |
20130021766 | Electronic Component - An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap. | 01-24-2013 |
20130105977 | Electronic Device and Method for Fabricating an Electronic Device | 05-02-2013 |
20130113114 | Device Including Two Power Semiconductor Chips and Manufacturing Thereof - A device includes a first power semiconductor chip having a first face and a second face opposite to the first face with a first contact pad arranged on the first face. The first contact pad is an external contact pad. The device further includes a first contact clip attached to the second face of the first power semiconductor chip. A second power semiconductor chip is attached to the first contact clip, and a second contact clip is attached to the second power semiconductor chip. | 05-09-2013 |
20130127031 | CHIP-CARRIER, A METHOD FOR FORMING A CHIP-CARRIER AND A METHOD FOR FORMING A CHIP PACKAGE - Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity. | 05-23-2013 |
20130134589 | CHIP-PACKAGE AND A METHOD FOR FORMING A CHIP-PACKAGE - A chip-package includes a chip-carrier configured to carry a chip, the chip arranged over a chip-carrier side, wherein the chip-carrier side is configured in electrical connection with a chip back side; an insulation material including: a first insulation portion formed over a first chip lateral side; a second insulation portion formed over a second chip lateral side, wherein the first chip lateral side and the second chip lateral side each abuts opposite edges of the chip back side; and a third insulation portion formed over at least part of a chip front side, the chip front side including one or more electrical contacts formed within the chip front side; wherein at least part of the first insulation portion is arranged over the chip-carrier side and wherein the first insulation portion is configured to extend in a direction perpendicular to the first chip lateral side further than the chip-carrier. | 05-30-2013 |
20130152696 | MICROMECHANICAL SEMICONDUCTOR SENSING DEVICE - Micromechanical semiconductor sensing device comprises a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, said piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal. | 06-20-2013 |
20130249069 | CIRCUIT PACKAGE, AN ELECTRONIC CIRCUIT PACKAGE, AND METHODS FOR ENCAPSULATING AN ELECTRONIC CIRCUIT - A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures. | 09-26-2013 |
20130264721 | Electronic Module - The electronic module includes a first carrier and a first semiconductor chip arranged on the first carrier. A second semiconductor chip is arranged above the first semiconductor chip. A material layer adheres the second semiconductor chip to the first carrier and encapsulates the first semiconductor chip. | 10-10-2013 |
20130277824 | Manufacturing Method for Semiconductor Device and Semiconductor Device - In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer. | 10-24-2013 |
20130299848 | Semiconductor Packages and Methods of Formation Thereof - In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed. | 11-14-2013 |
20130328197 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 12-12-2013 |
20130329365 | Electric Device Package and Method of Making an Electric Device Package - A system and method for manufacturing an electric device package are disclosed. An embodiment comprises a carrier, a component disposed on the carrier, the component having a first component contact pad, and a first electrical connection between the first component contact pad and a first carrier contact pad, wherein the first electrical connection comprises a first hollow space, the first hollow space comprising a first liquid. | 12-12-2013 |
20130341778 | Device Contact, Electric Device Package and Method of Manufacturing an Electric Device Package - An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer. | 12-26-2013 |
20140021638 | EMBEDDED INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING AN EMBEDDED INTEGRATED CIRCUIT PACKAGE - A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. | 01-23-2014 |
20140027892 | Electric Device Package Comprising a Laminate and Method of Making an Electric Device Package Comprising a Laminate - A system and method for manufacturing an electric device package are disclosed. An embodiment comprises comprising a first carrier contact, a first electric component, the first electric component having a first top surface and a first bottom surface, the first electric component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier and an connection element comprising a second electric component and an interconnect element, the connection element having a connection element top surface and a connection element bottom surface, wherein the connection element bottom surface comprises a first connection element contact and a second connection element contact, and wherein the first connection element contact is connected to the first component contact and the second connection element contact is connected to the first carrier contact. The packaged device further comprises an encapsulant encapsulating the first electric component. | 01-30-2014 |
20140042603 | Electronic Device and Method of Fabricating an Electronic Device - A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip. | 02-13-2014 |
20140061878 | INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material. | 03-06-2014 |
20140076613 | Method of Electrophoretic Depositing (EPD) a Film on a System and System Thereof - A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements. | 03-20-2014 |
20140084302 | INTEGRATED CIRCUIT, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area disposed on a first side of the carrier, wherein the at least one electronic component is electrically connected to the at least one contact area; an inorganic material layer wafer bonded to the first side of the carrier, wherein the carrier has a first coefficient of thermal expansion, and wherein the inorganic material layer has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion has a difference of less than 100% compared with the first coefficient of thermal expansion; and at least one contact via formed through the inorganic material layer, wherein the at least one contact via contacts the at least one contact area. | 03-27-2014 |
20140084433 | Semiconductor Device Having a Clip Contact - A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device. | 03-27-2014 |
20140117531 | SEMICONDUCTOR DEVICE WITH ENCAPSULANT - Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles. | 05-01-2014 |
20140126165 | Packaged Nano-Structured Component and Method of Making a Packaged Nano-Structured Component - An assembled component and a method for assembling a component are disclosed. In one embodiment the assembled component includes a component carrier, an attachment layer disposed on the component carrier and a component disposed on the attachment layer, the component having a nano-structured first main surface facing the component carrier. | 05-08-2014 |
20140138833 | Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced. | 05-22-2014 |
20140138841 | INTEGRATED CIRCUIT, A SEMICONDUCTOR DIE ARRANGEMENT AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side. | 05-22-2014 |
20140138843 | Method for Fabricating an Electronic Component - A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier. | 05-22-2014 |
20140151862 | EMBEDDED INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING AN EMBEDDED INTEGRATED CIRCUIT PACKAGE - A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. | 06-05-2014 |
20140197527 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%. | 07-17-2014 |
20140197552 | CHIP ARRANGEMENT, A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material. | 07-17-2014 |
20140218885 | Device Including a Semiconductor Chip and Wires - A device includes a carrier, a first semiconductor chip arranged over the carrier and a first electrically conductive element arranged over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and to the first semiconductor chip. The first electrically conductive element is configured to forward an electrical signal between the first wire and the second wire. | 08-07-2014 |
20140239466 | Electronic Device - An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member. | 08-28-2014 |
20140240945 | Multi-Die Package with Separate Inter-Die Interconnects - A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a second semiconductor die is connected to a second conductive region of the substrate. Each die has a second electrode at an opposing second side of the respective die. A first metal layer extends from a periphery region of the substrate to over the first die. The first metal layer has a generally rectangular cross-sectional area and connects one of the conductive regions in the periphery region of the substrate to the second electrode of the first die. A second metal layer separate from the first metal layer extends over the first and second dies. The second metal layer has a generally rectangular cross-sectional area and connects the second electrodes of the first and second dies. | 08-28-2014 |
20140246766 | Semiconductor Chip Package - The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements. | 09-04-2014 |
20140264919 | CHIP ARRANGEMENT, WAFER ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure. | 09-18-2014 |
20140264950 | CHIP ARRANGEMENT AND A METHOD OF MANUFACTURING A CHIP ARRANGEMENT - In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier. | 09-18-2014 |
20140301039 | PACKAGE AND A METHOD OF MANUFACTURING THE SAME - In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant. | 10-09-2014 |
20140312394 | Semiconductor Device Including a Material to Absorb Thermal Energy - A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules. | 10-23-2014 |
20140353808 | Packaged Semiconductor Device - Disclosed is a packaged device, comprising a carrier comprising a first carrier contact, a first electrical component having a first top surface and a first bottom surface, the first electrical component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier, an embedded system comprising a second electrical component having a second top surface, an interconnect element, and a first connecting element, the embedded system having a system bottom surface, wherein the system bottom surface comprises a first system contact, wherein the second top surface comprises a first component contact, and wherein the first system contact is connected to the first component contact by the interconnect element and the first component contact of the second electrical component is connected to the first carrier contact by means of the first connecting element. | 12-04-2014 |
20150028448 | Chip Package with Embedded Passive Component - A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure. | 01-29-2015 |
20150028487 | Chip Package with Passives - A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure. | 01-29-2015 |
20150035170 | MULTICHIP DEVICE INCLUDING A SUBSTRATE - A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the substrate, and a second electrically conductive material arranged over a second main surface of the substrate opposite to the first main surface. The device further includes an electrically conductive connection extending from the first main surface to the second main surface and electrically coupling the first electrically conductive material and the second electrically conductive material, a first semiconductor chip arranged over the first main surface and electrically coupled to the first electrically conductive material, and a second semiconductor chip arranged over the second main surface and electrically coupled to the second electrically conductive material. | 02-05-2015 |
20150060872 | Encapsulated Semiconductor Device - A semiconductor device includes a carrier and a semiconductor chip disposed over the carrier. The semiconductor chip has a first surface and a second surface opposite to the first surface, wherein the second surface faces the carrier. Further, the semiconductor device includes a pre-encapsulant covering at least partially the second surface of the semiconductor chip and at least partially a side wall surface of the semiconductor chip. The pre-encapsulant has a thermal conductivity of equal to or greater than 10 W/(m·K) and a specific heat capacity of equal to or greater than 0.2 J/(g·K). | 03-05-2015 |
20150076672 | METHOD OF MANUFACTURING A CHIP PACKAGE, CHIP PACKAGE, METHOD OF MANUFACTURING A CHIP ASSEMBLY AND CHIP ASSEMBLY - A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip. | 03-19-2015 |
20150077941 | Electronic Power Device and Method of Fabricating an Electronic Power Device - An electronic device comprises a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least a portion of the first main surface is configured as a heat dissipating surface without electrical power terminal functionality. The electronic device comprises a porous metal layer arranged on the portion of the first main surface. | 03-19-2015 |
20150111343 | Electronic Component - An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap. | 04-23-2015 |
20150162287 | Electronic Device - An electronic device includes multiple semiconductor chips in a single housing. Such semiconductor chips may comprise different semiconductor materials, for example they may comprise GaN. Using bonding clips instead of bonding wires is an efficient way of connecting such semiconductor chips to a substrate. | 06-11-2015 |
20150217994 | Micromechanical Semiconductor Sensing Device - Micromechanical semiconductor sensing device comprises a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, said piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal. | 08-06-2015 |
Khalil Hosseini, Weihmichi DE
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20130241077 | Semiconductor Package and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant. | 09-19-2013 |
Khosro Molla Hosseini, Scottsdale, AZ US
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20110299972 | IMPELLER BACKFACE SHROUD FOR USE WITH A GAS TURBINE ENGINE - An impeller or axial stage compressor disk backface shroud for use with a gas turbine engine is disclosed. The backface shroud includes, but is not limited to, a substantially funnel shaped body having a surface. The substantially funnel shaped body is configured to be statically mounted to the gas turbine engine substantially coaxially with the impeller or axial stage compressor disk. The surface and a backface of the impeller or axial stage compressor disk form a cavity that guides an airflow portion to a turbine when the substantially funnel shaped body is mounted coaxially with the impeller or axial stage compressor disk and axially spaced apart therefrom. The airflow portion has a tangential velocity and a recessed groove in the surface of the backface shroud is oriented generally transversely to the tangential velocity to at least partially interfere with the airflow portion, thus affecting static pressure in the cavity. | 12-08-2011 |
Khosro Molla Hosseini, Phoenix, AZ US
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20090317244 | GAS TURBINE ENGINE WITH IMPROVED THERMAL ISOLATION - A gas turbine engine includes a housing with a duct wall that defines a generally annular and axially elongated hot gas flow path for passage of combustion gas. The engine further includes a contoured shroud mounted within the internal engine cavity and defining a hot gas recirculation pocket for receiving hot gas ingested from the hot gas flow path through the annular space and for recirculating the ingested hot gas back through the annular space to the hot gas flow path. The contoured shroud includes a base wall extending radially inwardly from the duct wall, an inboard wall extending from the base wall in an axial direction toward the rotor, and an end wall extending from the inboard wall in a radially outward direction. The end wall terminates in a circumferentially extending free edge disposed in proximity to the annular space. The end wall defines an opening. | 12-24-2009 |
Mahdi Hosseini, Ginalary AU
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20090082216 | Metallic nanostructures self-assembly, and testing methods - The invention provides method for metallic nanonstructures self-assembly methods and materials testing. Preferred embodiment methods permit for the formation of individual nanonstructures and arrays of nanostructrues. The nanostructures formed can have a metal alloy crystal structure. Example structures include slender wires, rectangular bars, or plate-like structures. Tips can be shaped, single layer and multiple layer coatings can be formed, tips can be functionalized, molecules can be adhered, and many testing methods are enabled. | 03-26-2009 |
Majid Hosseini, Cuyahoga Falls, OH US
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20150037852 | METHOD AND SYSTEM FOR REDUCING FREE FATTY ACID CONTENT OF A FEEDSTOCK - A method for reducing the free fatty acid content of a feedstock includes the steps of providing a free-fatty-acid-containing feedstock, treating the free-fatty-acid-containing feedstock to reduce the free fatty acid content thereof, where the step of treating includes combining at least one of an algae and a coagulant to the free-fatty-acid-containing feedstock, and producing a product from the treated feedstock. | 02-05-2015 |
Mohammad Javad Hosseini, Shiraz IR
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20150370996 | System for determining the need for Angiography in patients with symptoms of Coronary Artery disease - The present invention relates to a system for determining the need for angiography in patients with symptoms of Coronary Artery Disease (CAD), and comprises a data mining algorithm that processes a dataset with a set of predetermined features, preferably 50 features. The system comprises a pre-processing phase and a main phase. | 12-24-2015 |
Moji Hosseini, Iowa City, IA US
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20140223203 | SYSTEM AND METHOD FOR CREATING HIGH POWERED EMC COMPLIANT POWER SUPPLY FOR INDUSTRIAL AND MILITARY APPLICATIONS - The present invention is an apparatus and method for provisioning a compact power filter connection to a well-grounded connector in such a way as to include a capacitive and inductive circuit connection, extremely near the connector and filter, such that EMC compatibility is created in a space roughly 30% of traditional mechanisms and design approach to satisfy the aforementioned needs, provide the previously stated objects, include the above-listed features, and achieve the already articulated advantages. The present invention is carried out in a “post-internal ferrite bead re-radiation noise-less” manner, in a sense that ability to have noise introduced back onto a post-ferrite bead line has been greatly reduced. | 08-07-2014 |
Mojtaba Hosseini, Ottawa CA
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20100067571 | Low latency high resolution video encoding - Video data that is associated with a videoconference or a telepresence session is captured and a video signal relating thereto is provided. The video signal is divided into segments, which are identical from one video frame to another subsequent video frame within the video signal. Each segment is encoded independently, to result in encoded segment data such that both I-frames and P-frames are generated for a given segment, so as to support independent reconstruction of segments at a distant end. The encoded segment data is transmitted subsequently to the distant end. | 03-18-2010 |
20100118114 | Video rate adaptation for congestion control - Exchanging of videoconference data between a first endpoint and a second endpoint via a network includes receiving, at the first endpoint, statistical data relating to transmission of first videoconference data. In particular, the first videoconference data is data that is transmitted previously from the first endpoint to the second endpoint via the network, and the statistical data relates to network performance characteristics during transmission of the first videoconference data. An approximately optimized data transmission rate for the network performance characteristics is determined, based on the statistical data. The output bit rate of a video encoder associated with the first endpoint is adjusted, such that second videoconference data, relating to the same videoconference at a time that is later than the first videoconference data, is encoded to provide output data at an adjusted output bit rate for being transmitted via the network at approximately the optimized data transmission rate. | 05-13-2010 |
20100321468 | Method Of Managing The Flow Of Time-Sensitive Data Over Packet Networks - A method is disclosed for managing multiple data streams transported over a common communications resource in a packet network, wherein data flowing through the resource travels in both directions, and wherein each stream is subject to data peaks. The round trip delay is determined for each data stream, and the transmission of data peaks in one or more of the data streams is delayed to at least reduce the degree of coincidence in the data peaks of different streams without increasing the maximum round trip delay for the data streams. | 12-23-2010 |
20110063408 | METHOD AND APPARATUS FOR COMMUNICATING AN IMAGE OVER A NETWORK WITH SPATIAL SCALEABILITY - Visual information over a network by filtering a full resolution image signal to produce a series of sub-bands, wherein at least one of the sub-bands constitutes a base sub-band representing an image of reduced resolution and wherein additional sub-bands carry higher resolution information. At least the base sub-band is transmitted to a far end endpoint to permit image reconstruction at the far end endpoint at a degree of resolution dependent on the number of sub-bands used to reconstruct the image. | 03-17-2011 |
20160007047 | METHOD OF CONTROLLING BANDWIDTH IN AN ALWAYS ON VIDEO CONFERENCING SYSTEM - Disclosed is a video conferencing endpoint comprising a camera interface for receiving local video from a local camera, a video encoder for encoding the local video from the camera interface for transmission to a remote endpoint over a communications channel, a feature detector for determining whether a feature is present in the local video received from the local camera, and a transmit parameter controller operative to control the video encoder to change at least one transmit parameter in response to at least one of: the presence or absence of the feature in the received local video, and a signal received from a remote endpoint indicating the presence or absence of a feature in the video acquired at the remote endpoint. | 01-07-2016 |
Morris Hosseini, Braunschweig DE
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20090269318 | PROGENITOR CELLS FROM WHARTON'S JELLY OF HUMAN UMBILICAL CORD - Human progenitor cells are extracted from perivascular tissue of human umbilical cord. The progenitor cell population proliferates rapidly, and harbours osteogenic progenitor cells and MHC−/− progenitor cells, and is useful to grow and repair human tissues including bone. | 10-29-2009 |
20130259840 | PROGENITOR CELLS FROM WHARTON'S JELLY OF HUMAN UMBILICAL CORD - Human progenitor cells are extracted from perivascular tissue of human umbilical cord. The progenitor cell population proliferates rapidly, and harbours osteogenic progenitor cells and MHC−/− progenitor cells, and is useful to grow and repair human tissues including bone. | 10-03-2013 |
Reshad Hosseini, Tubingen DE
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20110069755 | Method and device for image compression - A method for compressing a digital image includes selecting an image patch of the digital image; assigning the selected image patch to a specific class (z); transforming the image patch, with a pre-determined class-specific transformation function; and quantizing the transformed image patch, wherein parameters of the classifier have been learned from a set of training image patches. | 03-24-2011 |
S. Abbas Hosseini, Richmond Hill CA
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20130126573 | METHOD OF MATERIAL PROCESSING BY LASER FILAMENTATION - A method is provided for the internal processing of a transparent substrate in preparation for a cleaving step. The substrate is irradiated with a focused laser beam that is comprised of pulses having an energy and pulse duration selected to produce a filament within the substrate. The substrate is translated relative to the laser beam to irradiate the substrate and produce an additional filament at one or more additional locations. The resulting filaments form an array defining an internally scribed path for cleaving said substrate. Laser beam parameters may be varied to adjust the filament length and position, and to optionally introduce V-channels or grooves, rendering bevels to the laser-cleaved edges. Preferably, the laser pulses are delivered in a burst train for lowering the energy threshold for filament formation, increasing the filament length, thermally annealing of the filament modification zone to minimize collateral damage, improving process reproducibility, and increasing the processing speed compared with the use of low repetition rate lasers. | 05-23-2013 |
20150034612 | METHOD AND APPARATUS FOR NON-ABALTIVE, PHOTOACCOUSTIC COMPRESSION MACHINING IN TRANSPARENT MATERIALS USING FILAMENTATION BY BURST ULTRAFAST LASER PULSES - An apparatus, system and method for the processing of orifices in materials by laser filamentation that utilizes an optical configuration that focuses the incident laser light beam in a distributed manner along the longitudinal beam axis. This distributed focusing method enables the formation of filaments over distances, and the laser and focusing parameters are adjusted to determine the filament propagation and termination points so as to develop a single/double end stopped orifice, or a through orifice. Selected transparent substrates from a stacked or nested configuration may have orifices formed therein/therethrough without affecting the adjacent substrate. These distributed focusing methods support the formation filaments with lengths well beyond ten millimeters in borosilicate glass and similar brittle materials and semiconductors. | 02-05-2015 |
S. Abbas Hosseini, Orlando, FL US
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20150034613 | SYSTEM FOR PERFORMING LASER FILAMENTATION WITHIN TRANSPARENT MATERIALS - Systems and methods are described for forming continuous laser filaments in transparent materials. A burst of ultrafast laser pulses is focused such that a beam waist is formed external to the material being processed without forming an external plasma channel, while a sufficient energy density is formed within an extended region within the material to support the formation of a continuous filament, without causing optical breakdown within the material. Filaments formed according to this method may exhibit lengths exceeding up to 10 mm. In some embodiments, an aberrated optical focusing element is employed to produce an external beam waist while producing distributed focusing of the incident beam within the material. Various systems are described that facilitate the formation of filament arrays within transparent substrates for cleaving/singulation and/or marking. Optical monitoring of the filaments may be employed to provide feedback to facilitate active control of the process. | 02-05-2015 |
20150038313 | METHOD AND APPARATUS FOR PERFORMING LASER FILAMENTATION WITHIN TRANSPARENT MATERIALS - Systems and methods are described for forming continuous laser filaments in transparent materials. A burst of ultrafast laser pulses is focused such that a beam waist is formed external to the material being processed without forming an external plasma channel, while a sufficient energy density is formed within an extended region within the material to support the formation of a continuous filament, without causing optical breakdown within the material. Filaments formed according to this method may exhibit lengths exceeding 10 mm. In some embodiments, an aberrated optical focusing element is employed to produce an external beam waist while producing distributed focusing of the incident beam within the material. Various systems are described that facilitate the formation of filament arrays within transparent substrates for cleaving/singulation and/or marking. Optical monitoring of the filaments may be employed to provide feedback to facilitate active control of the process. | 02-05-2015 |
20150044416 | METHOD AND APPARATUS FOR HYBRID PHOTOACOUSTIC COMPRESSION MACHINING IN TRANSPARENT MATERIALS USING FILAMENTATION BY BURST ULTRAFAST LASER PULSES - An apparatus, system and method for the processing of orifices in materials by laser filamentation that utilizes an optical configuration that focuses the incident laser light beam in a distributed manner along the longitudinal beam axis. This distributed focusing method enables the formation of filaments over distances, and the laser and focusing parameters are adjusted to determine the filament propagation and termination points so as to develop a single/double end stopped orifice, or a through orifice. Selected transparent substrates from a stacked or nested configuration may have orifices formed therein/therethrough without affecting the adjacent substrate. These distributed focusing methods support the formation filaments with lengths well beyond ten millimeters in borosilicate glass and similar brittle materials and semiconductors. | 02-12-2015 |
20150118522 | METHOD OF FABRICATING A GLASS MAGNETIC HARD DRIVE DISK PLATTER USING FILAMENTATION BY BURST ULTRAFAST LASER PULSES - A non-ablative method and apparatus for making an economical glass hard disk (platter) for a computer hard disk drive (HDD) using a material machining technique involving filamentation by burst ultrafast laser pulses. Two related methods disclosed, differing only in whether the glass substrate the HDD platter is to be cut from has been coated with all the necessary material layers to function as a magnetic media in a computer's hard drive. Platter blanks are precisely cut using filamentation by burst ultrafast laser pulses such that the blank's edges need not be ground, the platter's geometric circularity need not be corrected and there is no need for further surface polishing. Thus the platters can be cut from raw glass or coated glass. As a result, this method reduces the product contamination, speeds up production, and realizes great reductions in the quantity of waste materials and lower production costs. | 04-30-2015 |
20150121960 | METHOD AND APPARATUS FOR MACHINING DIAMONDS AND GEMSTONES USING FILAMENTATION BY BURST ULTRAFAST LASER PULSES - A non-ablative laser machining method and apparatus for cutting facets of a diamond, using a material machining technique involving filamentation by burst ultrafast laser pulses well suited to mass production. Coupled with 3D modeling and the computerized laser machining system, complex geometric surfaces can be created on the diamond. The facets of the diamond need not be planar in configuration, and may incorporate acute as well as oblique angles. This method minimizes the need for diamond polishing, speeds up production, and realizes great reductions in the quantity of lost material from the cutting process. | 05-07-2015 |
20150122656 | MASS BASED FILTRATION DEVICES AND METHOD OF FABRICATION USING BURSTS OF ULTRAFAST LASER PULSES - A mass separation device includes a transparent substrate and a plurality of small diameter cylindrically shaped orifices in the transparent substrate. The small diameter cylindrically shaped orifices include smooth wall surfaces and are not tapered. The small diameter cylindrically shaped orifices are drilled by photoacoustic compression and are clean and sharp and do not have ejecta mounds surrounding the orifice on the surface of the transparent substrate. The small diameter cylindrically shaped orifices in said transparent substrate are less than or equal to 1 μm in diameter. The transparent substrate is glass and preferably is borosilicate glass. | 05-07-2015 |
20150136743 | METHOD OF CLOSED FORM RELEASE FOR BRITTLE MATERIALS USING BURST ULTRAFAST LASER PULSES - A method for machining and releasing closed forms from a transparent, brittle substrate includes using a burst of ultrafast laser pulses to drill patterns of orifices in the substrate. Orifices are formed by photoacoustic compression and they extend completely or partially in the transparent substrate. A scribed line of spaced apart orifices in the transparent substrate comprise a closed form pattern in the substrate. A heat source is applied in a region about said scribed line of spaced apart orifices until the closed form pattern releases from the transparent substrate. | 05-21-2015 |
20150140229 | METHOD AND APPARATUS FOR FORWARD DEPOSITION OF MATERIAL ONTO A SUBSTRATE USING BURST ULTRAFAST LASER PULSE ENERGY - A process of forward deposition of a material onto a target substrate is accomplished by passing a burst of ultrafast laser pulses of a laser beam through a carrier substrate that is transparent to a laser beam. The carrier substrate is coated with a material to be transferred on the bottom side thereof. Electrons on the back side of said transparent carrier coated with the material are excited by the first few sub-pulses of the laser beam which lifts the material from the carrier substrate and subsequent sub-pulse of the laser beam send the material into space at hypersonic speed by a shock wave that drives the material with forward momentum across a narrow gap between the carrier substrate and the target substrate, and onto the target substrate. | 05-21-2015 |
20150140241 | METHOD AND APPARATUS FOR SPIRAL CUTTING A GLASS TUBE USING FILAMENTATION BY BURST ULTRAFAST LASER PULSES - A method of producing a spiral cut transparent tube using laser machining includes using an ultrafast laser beam comprising a burst of laser pulses and focusing the laser beam on the transparent tube to enable relative movement between the laser beam and the transparent tube by moving the laser beam, the glass tube or both the laser beam and the glass tube. A beam waist is formed external to the surface of the transparent tube wherein the laser pulses and sufficient energy density is maintained within the transparent tube to form a continuous laser filament therethrough without causing optical breakdown. The method and delivery system makes a spiral cut in the transparent tube. | 05-21-2015 |
20150140735 | ELECTRO/MECHANICAL MICROCHIPS AND METHOD OF MAKING WITH BURST ULTRAFAST LASER PULSES - A method for making an electromechanical chip using a plurality of transparent substrates, comprising the steps of: machining, using photoacoustic compression, full or partial voids in at least one of the plurality of substrates. The plurality of transparent substrates are stacked and arranged in a specific order. The transparent substrates are affixed and sealed together. The chip may be sealed by laser welding or adhesive. | 05-21-2015 |
20150151380 | METHOD AND APPARATUS FOR LASER PROCESSING OF SILICON BY FILAMENTATION OF BURST ULTRAFAST LASER PULSES - A method for laser processing of Silicon includes placing a Kerr material into engagement with the Silicon forming an interface therebetween. A laser beam is applied having at least one subpulse in a burst envelope operating at a first wavelength. The laser beam passes through a distributive lens focusing assembly and to the Kerr material. The first wavelength is modified to a plurality of second wavelengths, some of which are effective for processing Silicon. Photoacoustic compression processing is produced by the laser pulse energy by a portion of second wavelengths delivered through the interface and to the Silcon which initiates Kerr Effect self focusing which is propagated in the Silicon by additional energy input to the Silicon thus producing a filament within the Silicon. | 06-04-2015 |
20150246415 | METHOD AND APPARATUS FOR MATERIAL PROCESSING USING MULTIPLE FILAMENTATION OF BURST ULTRAFAST LASER PULSES - A method of drilling multiple orifices in and texturing a substrate is disclosed and includes the following steps. Ultrafast laser pulses are passed through a beam splitting diffractive optical element and then multiple beams are passed through a distributive-focus lens focusing assembly. The relative distance and/or angle of said distributive-focus lens focusing assembly in relation to the laser source is adjusted focusing the pulses in a distributed focus configuration creating a principal focal waist and at least one secondary focal waist. The fluence level of the at least one secondary focal waists is adjusted such that it is or they are of sufficient intensity and number to ensure propagation of multiple filaments in the substrate. Photoacoustic compressive machining is performed and forms multiple volume(s) within the substrate. | 09-03-2015 |
Seyed Hamid Reza Hosseini, Seattle, WA US
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20110125086 | FLUID INJECTION DEVICE - A fluid injection device includes: a pulse generation section that includes a fluid chamber whose volume is changeable, and an inlet flow passage and an outlet flow passage that are connected to the fluid chamber; a first connection flow passage connected to the outlet flow passage, having an end portion; a second connection flow passage connected to the inlet flow passage; a fluid injection opening formed at the end portion of the first connection flow passage, having a diameter smaller than the diameter of the outlet flow passage; a connection flow passage tube including the first connection flow passage and having rigidity adequate to transmit pulses of fluid flowing from the fluid chamber to the fluid injection opening; and a pressure generation section that supplies fluid to the inlet flow passage. | 05-26-2011 |
20130079707 | FLUID INJECTION DEVICE - A fluid injection device includes: a pulse generation section that includes a fluid chamber whose volume is changeable, and an inlet flow passage and an outlet flow passage that are connected to the fluid chamber; a first connection flow passage connected to the outlet flow passage, having an end portion; a second connection flow passage connected to the inlet flow passage; a fluid injection opening formed at the end portion of the first connection flow passage, having a diameter smaller than the diameter of the outlet flow passage; a connection flow passage tube including the first connection flow passage and having rigidity adequate to transmit pulses of fluid flowing from the fluid chamber to the fluid injection opening; and a pressure generation section that supplies fluid to the inlet flow passage. | 03-28-2013 |
20140163417 | FLUID INJECTION DEVICE - A fluid injection device includes: a pulse generation section that includes a fluid chamber whose volume is changeable, and an inlet flow passage and an outlet flow passage that are connected to the fluid chamber; a first connection flow passage connected to the outlet flow passage, having an end portion; a second connection flow passage connected to the inlet flow passage; a fluid injection opening formed at the end portion of the first connection flow passage, having a diameter smaller than the diameter of the outlet flow passage; a connection flow passage tube including the first connection flow passage and having rigidity adequate to transmit pulses of fluid flowing from the fluid chamber to the fluid injection opening; and a pressure generation section that supplies fluid to the inlet flow passage. | 06-12-2014 |
20150266035 | FLUID INJECTION DEVICE - A fluid injection device includes: a pulse generation section that includes a fluid chamber whose volume is changeable, and an inlet flow passage and an outlet flow passage that are connected to the fluid chamber; a first connection flow passage connected to the outlet flow passage, having an end portion; a second connection flow passage connected to the inlet flow passage; a fluid injection opening formed at the end portion of the first connection flow passage, having a diameter smaller than the diameter of the outlet flow passage; a connection flow passage tube including the first connection flow passage and having rigidity adequate to transmit pulses of fluid flowing from the fluid chamber to the fluid injection opening; and a pressure generation section that supplies fluid to the inlet flow passage. | 09-24-2015 |
Seyed Naser Hosseini, Enschede NL
Patent application number | Description | Published |
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20160003730 | FLOW CYTOMETRY SYSTEM AND METHOD - A flow cytometry system having a flow channel defined through the thickness of a substrate is disclosed. Fluid flowing through the flow channel is illuminated by a first plurality of surface waveguides that are arranged around the flow channel in a first plane, while a second plurality of surface waveguides arranged around the flow channel in a second plane receive light after it has interacted with the fluid. The illumination pattern provided to the fluid is controlled by controlling the phase of the light in the first plurality of surface waveguides. As a result, the fluid is illuminated with light that is uniform and has a low coefficient of variation, improving the ability to distinguish and quantify characteristics of the fluid, such as cell count, DNA content, and the like. | 01-07-2016 |
Seyed Saeid Hosseini, Singapore SG
Patent application number | Description | Published |
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20110192281 | POLYMER BLENDS AND CARBONIZED POLYMER BLENDS - A composition includes a first polymer having monomers each containing an imidazole group, and a second polymer, the first and second polymers being a polymer blend. The first polymer, the second polymer, or both may be cross-linked. The carbonized composition, polymeric and carbon membranes (either in the form of a flat sheet or a hollow fiber) made from the composition are also described. The polymeric and carbon membranes can be used to separate and purify gases or liquids | 08-11-2011 |
20130042670 | DETERMINATION OF PORE SIZE IN POROUS MATERIALS BY EVAPORATIVE MASS LOSS - A method for determination of pore-size distribution in a porous material called evapo porometry (EP) is capable of determining pore sizes from approximately the nanometer scale up to the micron scale. EP determines the pore size based on the evaporative mass loss at constant temperature from porous materials that have been pre-saturated with either a wetting or non-wetting volatile liquid. The saturated porous material is placed in an appropriate test cell on a conventional microbalance to measure liquid mass loss at a constant temperature as a function of time. The mass-loss rate is then related to the pore-size distribution. The microbalance permits measuring the mass as a function of time. The slope of the mass versus time curve is the evaporation rate. The evaporation rate is related to the vapor pressure at the interface between the liquid in the porous material and the ambient gas phase. The vapor pressure in turn is related to the pore diameter. | 02-21-2013 |
S. Farid Hosseini, Redmond, WA US
Patent application number | Description | Published |
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20100235235 | ENDORSABLE ENTITY PRESENTATION BASED UPON PARSED INSTANT MESSAGES - During an instant message conversation, instant message users may be presented with advertisements, news headlines, hyperlinks to web pages, and other additional information. It may be advantageous to provide targeted information that may be relevant to the current conversation between the instant message users. As provided herein, an endorsable entity may be presented to an instant message user based upon parsing an instant message from an instant message conversation. An instant message may be parsed for a proper noun (e.g., a word or grouping of words within the instant message text). The proper noun (e.g., a retail product) may be compared to an index to determine a topic of interest (e.g., a manufacturer of the particular retail product). The topic of interest may be used to determined an endorsable entity (e.g., an advertisement of the manufacturer), which may be presented to instant message users engaged in the instant message conversation. | 09-16-2010 |