Patent application number | Description | Published |
20130054881 | ELECTRONIC SYSTEM WITH STORAGE MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of an electronic system includes: forming a superblock by organizing an erase block according to a wear attribute; detecting a trigger count of the wear attribute of the superblock; updating a metadata table with the trigger count; and triggering a recycling event of the superblock based on the metadata table. | 02-28-2013 |
20130060994 | NON-VOLATILE MEMORY MANAGEMENT SYSTEM WITH TIME MEASURE MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory management system includes: selecting a specific time period by a unit controller; establishing a first time pool having super blocks written during the specific time period; and promoting to a second time pool, the super blocks from the first time pool, at the lapse of the specific time period. | 03-07-2013 |
20130061019 | STORAGE CONTROL SYSTEM WITH WRITE AMPLIFICATION CONTROL MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system includes: partitioning logical addresses into a number of subdrives, the logical addresses associated with a memory device; and monitoring a data write measure of one of the subdrives. | 03-07-2013 |
20130061101 | NON-VOLATILE MEMORY MANAGEMENT SYSTEM WITH LOAD LEVELING AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system includes: generating a test stimulus for a page in a memory array; measuring a test response from the page in the memory array based on the test stimulus; calculating a measured effective life of the page from the test response; and determining a use plan according to the measured effective life for accessing the page. | 03-07-2013 |
20130282962 | STORAGE CONTROL SYSTEM WITH FLASH CONFIGURATION AND METHOD OF OPERATION THEREOF - A storage control system and method of operation thereof includes: a memory circuit for accessing a configuration category; a configuration module, coupled to the memory circuit, for configuring the memory circuit with the configuration category; and an operation module, coupled to the configuration module, for controlling a performance characteristic of a memory device based on the configuration category. | 10-24-2013 |
20140208174 | STORAGE CONTROL SYSTEM WITH DATA MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system includes: determining a bit error rate of a page; calculating a slope based on the bit error rate; and adjusting a threshold voltage for the page based on the slope for reading a memory device. | 07-24-2014 |
20140237315 | METHOD AND SYSTEM FOR IMPROVING DATA INTEGRITY IN NON-VOLATILE STORAGE - A method for improving data integrity in a non-volatile memory system includes: accessing a non-volatile memory cell for retrieving hard data bits; generating soft information by capturing a reliability of the hard data bits; calculating syndrome bits by applying a lossy compression to the soft information; and generating a host data by executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits. | 08-21-2014 |
20140237318 | BANDWIDTH OPTIMIZATION IN A NON-VOLATILE MEMORY SYSTEM - A method of bandwidth optimization in a non-volatile memory system includes: retrieving hard data bits; generating soft information from the hard data bits; applying a lossless compression to the soft information for calculating syndrome bits; and executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits. | 08-21-2014 |
20140304455 | DATA MANAGEMENT IN A STORAGE SYSTEM - A storage system, and a method of data management in the storage system, with non-volatile memory device characteristics determined during an inspection of non-volatile memory devices before a runtime operation of a storage device in the storage system including: a controller in the storage system: a drive-level control unit configured for an update of operational capabilities based on the non-volatile memory device characteristics during the runtime operation of the storage device and for a group of the non-volatile memory devices based on the operational capabilities; and a memory control unit, coupled to the drive-level control unit, the memory control unit configured to receive the operational capabilities for control of the non-volatile memory devices. | 10-09-2014 |
20140310445 | STORAGE CONTROL SYSTEM WITH POWER-OFF TIME ESTIMATION MECHANISM AND METHOD OF OPERATION THEREOF - A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate. | 10-16-2014 |
20150039842 | DATA STORAGE SYSTEM WITH DYNAMIC READ THRESHOLD MECHANISM AND METHOD OF OPERATION THEREOF - A system and method of operation of a data storage system includes: a memory die for determining a middle read threshold; a control unit, coupled to the memory die, for calculating a lower read threshold and an upper read threshold based on the middle read threshold and a memory element age; and a memory interface, coupled to the memory die, for reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation. | 02-05-2015 |
20150043277 | Data Storage System with Dynamic Erase Block Grouping Mechanism and Method of Operation Thereof - Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block. | 02-12-2015 |
20150046635 | Electronic System with Storage Drive Life Estimation Mechanism and Method of Operation Thereof - Systems, methods and/or devices are used to enable storage drive life estimation. In one aspect, the method includes (1) determining two or more age criteria of a storage drive, and (2) determining a drive age of the storage drive in accordance with the two or more age criteria of the storage drive. | 02-12-2015 |
20150046664 | Storage Control System with Settings Adjustment Mechanism and Method of Operation Thereof - Systems, methods and/or devices are used to enable a settings adjustment mechanism. In one aspect, the method includes (1) accessing characterization information corresponding to how a group of non-volatile memory devices of a storage control system operates as the group wears, (2) determining an estimated age of a non-volatile memory device, of the group of non-volatile memory devices, in accordance with a wear indicator for the non-volatile memory device, and (3) determining one or more settings for the non-volatile memory device in accordance with the estimated age and the characterization information. | 02-12-2015 |
Patent application number | Description | Published |
20090313531 | Methods and Apparatus for Processing a Received Signal Using a Multiple-Step Trellis and Selection Signals for Multiple Trellis Paths - Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle). | 12-17-2009 |
20090319874 | Reliability Unit For Determining A Reliability Value For At Least One Bit Decision - A reliability unit is disclosed for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis. | 12-24-2009 |
20090319875 | Path Metric Difference Computation Unit For Computing Path Differences Through A Multiple-Step Trellis - A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. The disclosed path metric difference computation unit computes differences between paths through a multiple-step trellis, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of the plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of the plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle. The disclosed path metric difference computation unit comprises one or more path metric difference generators for generating a path metric difference Δ | 12-24-2009 |
20100050060 | Path Comparison Unit For Determining Paths In A Trellis That Compete With A Survivor Path - A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path. | 02-25-2010 |
Patent application number | Description | Published |
20130117582 | OFFLINE COMMUNICATION IN A VOLTAGE SCALING SYSTEM - The subject matter of this application is embodied in an apparatus that includes a data processor, and a hardware monitor. The hardware monitor can be configured to emulate a critical path of the data processor, measure a parameter associated with the emulated critical path, process the measurement value, and generate an interrupt signal if the processing result meets a criterion. The apparatus also includes a power supply to provide power to the data processor and the hardware monitor, and a controller to control the power supply to adjust an output voltage level of the power supply. The controller upon receiving an interrupt signal from the hardware monitor queries the hardware monitor to obtain a measurement of the parameter and controls the power supply to adjust the output voltage level according to the measurement value. | 05-09-2013 |
20130117589 | STABILITY CONTROL IN A VOLTAGE SCALING SYSTEM - The subject matter of this application is embodied in an apparatus that includes a data processor, and a hardware monitor to emulate a critical path of the data processor and measure a parameter associated with the emulated critical path, process the measurement value, and generate an interrupt signal if the processing result meets a criterion. The apparatus also includes a power supply to provide power to the data processor and the hardware monitor, and a controller to receive the interrupt signal from the hardware monitor and in response to the interrupt signal, controls the power supply to adjust an output voltage level of the power supply. | 05-09-2013 |
20130311792 | VOLTAGE SCALING ARCHITECTURE ON SYSTEM-ON-CHIP PLATFORM - The subject matter of this application is embodied in an apparatus that includes a data processor, and at least one hardware monitor to measure circuit delays associated with the data processor and a power supply to provide power to the data processor. The apparatus also includes a voltage regulator to regulate a voltage level provided by the power supply, and a look-up table having target voltage values and target circuit delay values each corresponding to one or more conditions. The apparatus further includes a controller to control the voltage regulator. The controller at various time points controls the voltage regulator based on target voltage values obtained from the look-up table. In between the time points, the controller controls the voltage regulator based on differences between target circuit delay values and measured circuit delay values. | 11-21-2013 |
20130311799 | WEIGHTED CONTROL IN A VOLTAGE SCALING SYSTEM - The subject matter of this application is embodied in an apparatus that includes a data processor, and two or more hardware monitors to measure parameters associated with the data processor. The apparatus also features a power supply to provide power to the data processor and the hardware monitors, and a controller to control the power supply to adjust an output voltage level of the power supply according to measurements from the hardware monitors. Different weight values are applied to the hardware monitors under different conditions, and the power supply output voltage level is controlled according to weighted measurements or values derived from the weighted measurements. | 11-21-2013 |