Patent application number | Description | Published |
20140036208 | DISPLAY SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - A display substrate for a display device includes: a substrate which includes a light blocking region defining a plurality of pixel areas disposed in a matrix, each pixel area having a length extending in a first direction, and a width extending in a second direction; a color filter overlapping a portion of the each pixel area of the plurality of pixel areas; and an alignment layer disposed on the color filter. The color filter includes a first edge parallel to the first direction and a second edge forming a predetermined angle with the first edge. The second edge is substantially parallel to an alignment direction of the alignment layer. | 02-06-2014 |
20140306216 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes an insulation substrate; a gate line and a data line on the insulation substrate; a first passivation layer on the gate line and the data line; an organic layer on the first passivation layer; a first electrode on the organic layer; a second passivation layer on the first electrode; and a second electrode on the second passivation layer. An edge of the organic layer is exposed by the first electrode. | 10-16-2014 |
20150199929 | DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME - A display panel includes a plurality of display signal lines positioned in a display area. A plurality of test pads are positioned in a peripheral area around the display area and are respectively connected to the plurality of display signal lines. The plurality of test pads include a first test pad positioned at an edge of the peripheral area and a second test pad positioned at the middle of the peripheral area. A shorting bar is connected to the plurality of test pads through a contact assistant. The first test pad is connected to the second test pad through a connection line. | 07-16-2015 |
20150268528 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a first insulation substrate, a gate line disposed on the first insulation substrate, a semiconductor layer disposed on the gate line, a data line insulated from and crossing the gate line and including a source electrode and a drain electrode facing the source electrode, a first insulating layer disposed on the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a second insulating layer disposed on the pixel electrode, a common electrode disposed on the second insulating layer, and a shielding pattern part disposed on a same layer as the pixel electrode and overlapping the data line. | 09-24-2015 |
Patent application number | Description | Published |
20100177210 | METHOD FOR ADJUSTING WHITE BALANCE - A white balance adjustment method is disclosed, in which a plurality of input pixels are transformed into a digital component color space, a hue region of each of the color-space transformed input pixels is determined, and a transformation matrix is determined according to the determined hue region. | 07-15-2010 |
20100214434 | APPARATUS AND METHOD FOR ADJUSTING WHITE BALANCE OF DIGITAL IMAGE - A method and an apparatus are provided for adjusting white balance of a digital image. An input image is converted into a YCbCr color space. White pixels of the converted input image are detected by determining whether each pixel of the converted input image is included in a preset region of the YCbCr color space. A gain of each channel is calculated from averages of R, G and B values of the detected white pixels. White balance adjustment is performed by applying the calculated gain of each channel to each pixel of the input image. | 08-26-2010 |
20100238316 | APPARATUS AND METHOD FOR CLASSIFYING IMAGES - An image classification apparatus and method for Automatic White Balance (AWB) are provided. An input image is divided into blocks including pluralities of pixels. A hue value and a chroma value are calculated for each of the blocks. A color-changed block is detected by calculating, for each one of the blocks, differences between the hue and chroma values calculated for all blocks adjacent to the one of the blocks and the hue and chroma values calculated for the one of the blocks. A hue variance and a chroma variance are calculated for the entire input image if a number of the detected color-changed blocks is greater than or equal to a first threshold. The input image is determined as a non-monochromatic image, if the hue variance is greater than or equal to a second threshold or the chroma variance is greater than or equal to a third threshold. | 09-23-2010 |
Patent application number | Description | Published |
20100124757 | GOLD NANOPARTICLE BASED PROTEASE IMAGING PROBES AND USE THEREOF - Disclosed are a metal nanoparticle onto which a peptide substrate specifically degraded by protease and fluorophore are chemically modified for selectively imaging protease expressed in cell and in tissue in a human body, and the use thereof. Also, a quantitative analysis method of protease using the metal nanoparticle, a cell imaging method and a drug screening method of inhibiting a protease overexpression are provided. In detail, the present invention is directed to a metal nanoparticle having a peptide substrate and fluorophore coupled thereto, the peptide substrate and the fluorophore being specifically degraded by due to a protease activated in various ways in cell and in a human body to exhibit fluorescence. Hence, the metal nanoparticle can be used to rapidly screen activation and inhibition of the protease in the imaging manner. Also, the metal nanoparticle is capable of being selectively absorbed into a cell and a tissue so as to be possibly used as a sensor for real-time cell imaging and early diagnosis of non-invasive diseases. | 05-20-2010 |
20100233085 | IONIC COMPLEX NANOPARTICLES FOR DETECTING HEPARANASE ACTIVITIES AND METHOD FOR PREPARING THE SAME - Disclosed are Ionic complex nanoparticles for detecting heparanase activities and a method for preparing the same. More specifically, disclosed are Ionic complex nanoparticles for detecting heparanase activities, wherein negative-ion substrate polymers specifically degraded by heparanase and positive-ion biocompatible polymers ionically bind to each other, and fluorophores or quenchers bind to each of the polymers. The ionic complex nanoparticles for detecting heparanase activities may be applied to a method for screening novel drugs such as inhibitors that prevent over-expression of heparanase. Various cells and tissues where over-expression of heparanase occurs may be non-invasively imaged in cancer cells, cancer tissues, and tissues of various inflammatory diseases. Accordingly, the ionic complex nanoparticles for detecting heparanase activities may be effectively used to early diagnose various diseases and incurable diseases including autoimmune diseases such as cancers, osteoarthritis, rheumatoid arthritis, and dementia. | 09-16-2010 |
20110213121 | NANOPARTICLE SENSOR FOR MEASURING PROTEASE ACTIVITY AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a nanoparticle sensor for measuring protease activity, for protease imaging, and a method for preparing the same. More specifically, the present invention relates to a nanoparticle sensor for measuring protease activity in which a fluorophore- and a quencher-conjugated peptide substrate is conjugated to a biocompatible polymer nanoparticle. The peptide substrate is specifically lysed by a protease. The sensor according to the present invention is capable of inhibiting emission of fluorescence with high extinctive activity of the quencher on a fluorescent material. But strong fluorescence is specifically emitted only if the peptide substrate is lysed by a specific protease. Therefore, the sensor is especially useful as a method for screening a novel drug such as a protease overexpression inhibitor, and early diagnosis of incurable diseases and various diseases such as autoimmune diseases including cancer, osteoarthritis, rheumatoid arthritis and dementia. | 09-01-2011 |
Patent application number | Description | Published |
20130215684 | NONVOLATILE MEMORY DEVICE, METHOD FOR OPERATING THE SAME, AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string. | 08-22-2013 |
20140169105 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device includes a semiconductor substrate including a plurality of active regions and a pair of first pillars protruding from each active region. A pair of drain selection lines surround each pillar of the pair of first pillars. A pair of second pillars, wherein each second pillar is disposed over a corresponding first pillar, of the pair of the first pillars, and is formed of a semiconductor material. A plurality of word lines and a source selection line form a stack that surrounds the pair of second pillars. A source line is formed over and connected with the pair of second pillars. Drain contacts are formed at both sides of each active region except between pairs of the drain selection lines. A bit line is formed over and connected with the drain contacts. | 06-19-2014 |
20150270283 | NONVOLATILE MEMORY DEVICE, METHOD FOR OPERATING THE SAME, AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string. | 09-24-2015 |