Schloeffel
Juergen Schloeffel, Buchholz/sproetze DE
Patent application number | Description | Published |
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20100229061 | Cell-Aware Fault Model Creation And Pattern Generation - Cell-aware fault models directly address layout-based intra-cell defects. They are created by performing analog simulations on the transistor-level netlist of a library cell and then by library view synthesis. The cell-aware fault models may be used to generate cell-aware test patterns, which usually have higher defect coverage than those generated by conventional ATPG techniques. The cell-aware fault models may also be used to improve defect coverage of a set of test patterns generated by conventional ATPG techniques. | 09-09-2010 |
20110047425 | On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis - On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature. | 02-24-2011 |
Juergen Schloeffel, Buchholz DE
Patent application number | Description | Published |
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20100117658 | TESTABLE INTEGRATED CIRCUIT AND TEST DATA GENERATION METHOD - An integrated circuit (IC) is disclosed that comprises a circuit portion ( | 05-13-2010 |
Juergen Schloeffel US
Patent application number | Description | Published |
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20130054161 | Cell-Aware Fault Model Generation For Delay Faults - Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns. | 02-28-2013 |