Patent application number | Description | Published |
20100183143 | CRYPTOGRAPHIC PROCESSING APPARATUS AND CRYPTOGRAPHIC PROCESSING METHOD - A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL | 07-22-2010 |
20100183144 | Cipher processing apparatus - A cipher processing apparatus for arithmetic operations of an FO function and an FL function comprising: an FL function operating unit for generating a 2N-bit output based on a first extension key; a partial function operating unit for generating an N-bit output based on second and third extension keys; an N-bit intermediate register for storing an output of the partial operating unit; a 2N-bit first data register for storing data based on the output of the FL function operating unit; and a controller for making the partial function operating unit perform six cycles, inputting an output of the intermediate register to the FL function operating unit, and storing the data based on the output of the FL function operating unit in the first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function. | 07-22-2010 |
20100232601 | ELLIPTIC CURVE ARITHMETIC PROCESSING UNIT AND ELLIPTIC CURVE ARITHMETIC PROCESSING PROGRAM AND METHOD - An apparatus for executing cryptographic calculation on the basis of an elliptic point on an elliptic curve includes: a memory for storing a first value including a plurality of digits; and a processor for executing a process including: obtaining a second value representing a point on the elliptic curve; calculating output values by using a predetermined equation, each digit of the first value, and the second value; determining whether at least one of the second value and the output values indicates a point of infinity; terminating the calculation when at least one of the second value and the output values indicates the point at infinity; and completing calculation when both the second value and the output values do not indicate the point at infinity, so as to obtain a result of the cryptographic calculation. | 09-16-2010 |
20100278332 | DATA CONVERSION FUNCTION PROCESSOR | 11-04-2010 |
20100278340 | ENCRYPTION DEVICE, ENCRYPTION METHOD AND STORAGE MEDIUM STORING ITS PROGRAM - When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t | 11-04-2010 |
20110075836 | METHOD AND APPARATUS FOR ELLIPTIC CURVE CRYPTOGRAPHIC PROCESSING - An apparatus includes a data storage to store a window table storing a table value with an index value mapped to the table value, the index value having same number of bits as a window width, the table value being a sum of a basic table value and a non-zero table correction value, the basic table value being obtained by multiplying a point G on an elliptic curve. An arithmetic processor generates the index value by reading from a scalar value at a bit position assigned to each bit of the window with the window being shifted, reads the table value from the window table according to the index value, and performs a doubling operation and an addition operation using the read table value. A corrector performs a correction on arithmetic results with a specific correction value responsive to the table correction value. | 03-31-2011 |
20110176673 | Encrypting apparatus - An encrypting apparatus includes a digest part using a SHA-2 algorithm of which a basic unit of operation is 32*Y (Y=1 or 2) bits. The digest part includes a shift register including a series of registers, and a predetermined number of adders performing an addition operation based on data stored in the shift register. The shift register includes a (32*Y)/X-bit register, where X=2 | 07-21-2011 |
20130022197 | RANDOM NUMBER GENERATOR, ENCRYPTION DEVICE, AND AUTHENTICATION DEVICE - A random number generator includes an exclusive-OR circuit, a random number determiner, and a random number generation instruction inhibitor. The exclusive-OR circuit obtains an exclusive-OR of outputs from a number of digital circuits. The random number determiner determines whether or not an output generated according to an instruction to generate random numbers is a random number for each of the digital circuits. The random number generation instruction inhibitor inhibits an instruction to generate random numbers to be provided to the digital circuits whose output generated according to the instruction is determined to be not a random number by the random number determiner. | 01-24-2013 |
20130039486 | CRYPTOGRAPHIC PROCESSING DEVICE AND CRYPTOGRAPHIC PROCESSING METHOD - A cryptographic processing device includes a private key storage unit which stores a private key d for elliptic curve cryptography, a random number generation unit which generates a b-bit random value s, and a processing unit. A bit string D is the private key d or a bit string obtained by modifying the private key d in such a way that a value of a most significant bit is 0, and a relation u=mk+b holds true for a length u of the bit string D, a window size k, and a positive integer m. The processing unit determines a signed k-bit window value w[i] corresponding to each i where 0≦i≦(m−1), a signed b-bit random value s[i] corresponding to each i, and a correction value g. The processing unit determines the above values under a certain constraint condition, while determining each random value s[i] to be +s or −s. | 02-14-2013 |
20130138710 | INDIVIDUAL-SPECIFIC INFORMATION GENERATION APPARATUS AND INDIVIDUAL-SPECIFIC INFORMATION GENERATION METHOD - The generation of individual-specific information having a good reliability and uniqueness is made possible with a little circuit scale. For this purpose, in an individual-specific information generation apparatus, a plurality of digital circuits are in the same circuit configuration. Each of the digital circuits outputs a fixed or a random number output value individually without their output with respect to a certain input being determined unambiguously among the digital circuits. In each of the digital circuit, an order is defined in advance. A random number judgment unit judges whether the output value is a random value or fixed, for each of the plurality of digital circuits. An individual-specific information generation unit generates the individual-specific information based on information of the order defined in the digital circuit judged by the random number judgment unit as having a fixed output value among the plurality of digital circuits and the output value. | 05-30-2013 |
20130287209 | ENCRYPTION PROCESSING DEVICE AND METHOD - A constant multiplier inputs a base and a modulo n, performs modular exponentiation modulo n with a prescribed constant as the exponent and with base a, and outputs the result of this calculation as base b. A personal key converter inputs a personal key d and calculates a personal key d′ as the quotient when d is divided by the prescribed constant. A correction key generator generates a correction key d″ as the remainder of the aforementioned division. A first modular exponentiation unit performs modular exponentiation base b with d′ as the exponent. A second modular exponentiation unit performs modular exponentiation base a with d″ as the exponent, and outputs a correction value. A correction calculation unit multiplies the outputs of the first and second modular exponentiation units and outputs the result as the encryption processing result. | 10-31-2013 |
20140016772 | ENCRYPTING DEVICE, ENCRYPTING METHOD, AND RECORDING MEDIUM - k bits from the least significant bit of the current secret key are retrieved, obtaining a binary window sequence. A binary bit string of concatenation of the random number to the more significant bits of the window sequence is obtained if the most significant bit of the window sequence is 0, subtracting a bit string from the current secret key to obtain a new secret key, or the bit string of a complement of the base number for the window sequence in binary system is calculated if the most significant bit of the window sequence is 1, obtaining a bit string by adding a minus sign to a bit string obtained by concatenating the random number to the more significant bits of the bit string, subtracting the bit string from the current secret key to obtain a new secret key. | 01-16-2014 |
20140164785 | ENCRYPTION PROCESSING DEVICE AND AUTHENTICATION METHOD - An encryption processing device includes a memory configured to store a common key, and a processor configured to generate a random number which is an integer, to perform a bit transposition on the common key, the bit transposition being determined at least by the random number, to transmit the random number to another encryption processing device and to receive a response from the other encryption processing device, the response obtained by encryption using a common key stored in the other encryption processing device and a second randomized key generated by performing the bit transposition determined by the random number; and to authenticate the other encryption processing device either by comparing the response with the random number by decrypting the response with the common key, or by comparing the random number with the response by encrypting the random number with the common key. | 06-12-2014 |
Patent application number | Description | Published |
20100046533 | ROUTER AND PACKET DISCARDING METHOD - A router controlling a route of packets. The router includes a counter counting an amount of received control packets on a user-identifier-by-user-identifier basis, the control packets being used for managing a network, a discard determining unit comparing a counter value of the counter with a threshold value, and a control packet discarding unit discarding a control packet including a user identifier for which the discard determining unit determines that the counter value exceeds the threshold value. | 02-25-2010 |
20100091775 | PACKET SWITCHING SYSTEM - A packet switching system includes a forwarding processing unit determining a destination of an input packet by analyzing the input packet and outputting it as an output packet, the forwarding processing unit comprises an ingress interface card checking if the input packet has a sequential cyclic number and an egress interface card creating a sequential cyclic number and assigning it to the output packet. | 04-15-2010 |
20100100672 | RELAY APPARATUS AND DATA CONTROL METHOD - When a data word is designated through a network search engine, a FIFO unit, and the like, a relay apparatus according to the invention searches for an associative memory address corresponding to the data word. Even when the associative memory address is internally converted to a contents memory address, the relay apparatus stores the contents memory address by causing it to correspond to a search result corresponding to the contents memory address as well as outputs the associative memory address together with the search result. | 04-22-2010 |
20100158030 | Routing Apparatus - A routing apparatus couples to another routing apparatus using a trunk formed by a plurality of channels, and has a plurality of input and output cards to input and output frames. Each input and output card includes a management table registering a transmitting source address, destination information, and a trunk attribute indicating whether a channel used for a transmission has a trunk structure, a learning request part searching the management table using a transmitting source address within a frame that is transmitted via the channel, and generating and supplying learning request information having information that is obtained by searching the management table to another input and output card, if the channel used for the transmission has the trunk structure, and a registering part registering learning request information supplied thereto in the management table. | 06-24-2010 |
20100246425 | PACKET PROCESSING APPARATUS, INTERFACE UNIT AND METHOD THEREOF - A packet processing apparatus includes a plurality of communication connecting unit each connected with a communication partner apparatus using one of a work path and a protection path, connecting unit for connecting, using a data bus, the plurality of communication connecting unit with one another; determination unit for, when a packet sent from the communication partner apparatus is received by one of the communication connecting unit, determining whether the packet is a maintenance packet that is used for monitoring a connection state with the communication partner apparatus; and transmitting unit for, when it is determined that the packet is a maintenance packet by the determination unit, transmitting the maintenance packet to the plurality of communication connecting unit using the data bus via the connecting unit. | 09-30-2010 |
20120079310 | COMMUNICATION SYSTEM, COMMUNICATION INTERFACE, AND SYNCHRONIZATION METHOD - An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator. | 03-29-2012 |
20120209941 | COMMUNICATION APPARATUS, AND APPARATUS AND METHOD FOR CONTROLLING COLLECTION OF STATISTICAL DATA - In a communication apparatus, a collector collects a plurality of statistical data values describing communication activities, based on given user data frames, and produces statistics transmission data including the collected statistical data values and management data tags added thereto. A controller transfers, by using a direct memory access technique, the statistics transmission data produced by the collector. A memory stores the statistics transmission data transferred by the controller. | 08-16-2012 |
Patent application number | Description | Published |
20090009822 | Solid-State Image Pickup Device and Image Pickup Method - A solid-state image pickup device and image pickup method eliminate a dark-current component by adjusting the black level appropriately even if the dark-current component varies among horizontal lines. A pixel array includes light-receiving pixel elements and light-blocking pixel elements disposed such that horizontal lines include the light-blocking pixel elements individually. A readout circuit block reads pixel signals of each of the horizontal lines from the pixel array, inputs the pixel signals to ADC circuits (column ADC circuit block), and outputs the pixel signals of the light-blocking pixel elements. A ramp signal generation circuit obtains the pixel signals of the light-blocking pixel elements output from the readout circuit block, generates a ramp signal by using a reference level of AD conversion adjusted for each of the horizontal lines in accordance with the obtained pixel signals of the light-blocking pixel elements, and inputs the ramp signal to the ADC circuits. | 01-08-2009 |
20100283879 | Solid-State Image Pickup Apparatus Including A Global Shutter Function and Control Method Therefor - A solid-state image pickup apparatus includes a pixel unit consisting of a plurality of pixels; a pixel control unit for controlling the plurality of pixels; a readout unit for reading a signal of each pixel output from the pixel unit; a shutter unit for establishing a state of a light incident to the pixel unit and that of shielding the pixel unit from the light; and a control unit. The control unit includes an exposure mode changeover unit for changing over an exposure mode to either a first exposure mode performing a simultaneous exposure for all pixels or a second exposure mode performing an exposure for each of a predetermined unit of pixels. The control unit controls the pixel control unit, readout unit and shutter unit according to an exposure mode changed over by the exposure mode changeover unit. | 11-11-2010 |
20110210383 | IMAGING DEVICE - First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects tend to occur by a process of forming an isolation region and a gate electrode, so that dark current noise tends to occur. The second diffusion region functioning as a protection layer prevents crystal defects in a manufacturing process. The second diffusion region isn't formed on a center of the surface of the first diffusion region where crystal defects don't tend to occur. In the first diffusion region where the second diffusion region isn't formed, the thickness of a depletion layer increases, which improves light detection sensitivity. This improves detection sensitivity of the photodiode without increasing the dark current noise. | 09-01-2011 |
Patent application number | Description | Published |
20090059431 | SUSPENSION, HEAD GIMBALS ASSEMBLY, METHOD FOR MANUFACTURING HEAD GIMBALS ASSEMBLY, STORAGE APPARATUS, AND APPARATUS FOR MANUFACTURING HEAD GIMBALS ASSEMBLY - This head gimbals assembly has a head slider, a flexure, and a load beam. The head slider has a head element and slider-side connection terminals. The flexure has a free end, a fixed end, a slider mounting portion and suspension-side connection terminals connected to the slider-side connection terminals. The load beam fixes a fixed end of the flexure on the side opposite to a flexure surface on which the head slider is mounted a connecting portion for interconnecting the suspension-side connection terminals and the slider mounting portion has higher resiliency than other portion of the connecting portion. According to a suspension in the present embodiment, a head gimbals assembly can be easily manufactured without wastefully discarding the suspension even when the desired evaluation result is not obtained because of problems in the head characteristics and the floating surface of the head slider. | 03-05-2009 |
20090103213 | Magnetic head slider for absorbing vibrations - A magnetic head slider disposed opposite to a surface of a magnetic disk, includes a slider main body, a magnetic head element that reads and reproduces data from the magnetic disk, and a vibration absorbing unit that absorbs vibrations generated due to contact between any portion of the slider main body and the surface of the magnetic disk, and that is provided on the slider main body at a predetermined position. | 04-23-2009 |
20090195933 | HEAD ASSEMBLY - A head assembly for writing or reading information to or from a recording medium. The head assembly includes a suspension having an electrode pad; a mounting member placed on the suspension; a head mounted on the mounting member and having an electrode, for writing or reading information; and a first bonding member made of a hot-melt adhesive and fixing the electrode to the electrode pad. | 08-06-2009 |
20100053791 | STORAGE DEVICE, RECORDING MEDIUM EVALUATION DEVICE, AND RECORDING MEDIUM EVALUATION METHOD - According to one embodiment, a storage device that reads data from and writes data to a recording medium, which is rotationally driven by a motor, by a head, includes a ground disconnector, a motor voltage application module, and a Coulomb force detector. The ground disconnector disconnects a connection between the motor and ground. The motor voltage application module applies voltage to be supplied to the motor. The Coulomb force detector detects read output while the motor voltage application module applies voltage to the motor. The Coulomb force detector then calculates, based on the read output, an amount of change in floating height of the head to read data from or write data to the recording medium to detect the magnitude of Coulomb force generated by electrical charging of the recording medium based on the applied voltage and the amount of change in floating height of the head. | 03-04-2010 |
Patent application number | Description | Published |
20090128210 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC CIRCUIT - An electric circuit has a first differential circuit for transmitting input data to a first node, a second differential circuit for holding the first node data, a first clock transmission circuit for flowing a first current in accordance with a clock signal, and a first transformer circuit for transformer-coupling the first differential circuit with the first clock transmission circuit, and the second differential circuit with the first clock transmission circuit. | 05-21-2009 |
20100253436 | AMPLIFIER - An amplifier is realized by a distributed-constant-type amplifier including an input-side transmission line and an output-side transmission line, and a plurality of unit circuits coupled between the input-side transmission line and the output-side transmission line, in which each of the plurality of unit circuits is formed by including an amplification circuit having a gain equal to or greater than one. | 10-07-2010 |
20110085621 | RECEIVER - A receiver includes: a first amplifier for amplifying an input signal and outputting an output signal; a clock generator for generating a clock signal corresponding to a period of the output signal; a judger for outputting a first logical value or a second logical value in accordance with a phase lead or phase lag which has been occurred at a crossing point of the positive-phase signal and the negative-phase signal of the output signal upon rising or falling the clock signal; a detector for outputting a difference value between a time for which the judgment signal has the first logical value and a time for which the judgment signal has the second logical value; and an adjustor for adjusting reference voltages of a positive-phase signal and a negative-phase signal of the input signal in accordance with the difference value output from the detector. | 04-14-2011 |
20110221491 | RECEIVING CIRCUIT AND SAMPLING CLOCK CONTROL METHOD - A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value. | 09-15-2011 |
Patent application number | Description | Published |
20140358967 | SERVICE SEARCH METHOD AND SERVER DEVICE IN DISTRIBUTED PROCESSING - A service search method, judges when receiving a service search request from a service search requester whether or not a local server matches a service search condition stored in the service search request by referring to the attribute about the local server; selects according to the route information a server having no search record in the search history information which is added to the service search request when it is judged that the local server does not match the service search condition, and transfers to the selected server the service search request to which the information about the local server is added as the search history information; and notifies the service search requester of a search request reply according to the route information generated by the local server when it is judged that the local server matches the service search condition. | 12-04-2014 |
20140379777 | DEVICE AND METHOD FOR PERFORMING DISTRIBUTED PROCESSING - A computer-readable recording medium has stored therein a program for causing a computer to execute a process including storing, as a variable set, a database of a variable that associates a key, a value and a synchronization destination corresponding to the key, executing a process of requesting that the variable in the variable set of the computer be referred to or updated in a state and evaluating a condition so as to make the state transition to a different state, and communicating the key specified by the request with the synchronization destination for the variable corresponding to the key specified by the request and synchronizing the value of the variable corresponding to the key in the computer and the value of the variable corresponding to the key in the variable set of the synchronization destination when the process of requesting is executed. | 12-25-2014 |
20150023213 | NODE APPARATUS AND COMMUNICATION METHOD - A node apparatus includes a TTL memory configured to store a TTL value for a first node apparatus in the cluster; a receiving unit configured to receive a first Hello packet including a first sequence number and a second Hello packet including a second sequence number that is incremented when the node apparatus transmits a Hello packet; a sequence number judging unit configured to judge whether a first sequence number and a second sequence number match each other; a TTL decrementing unit configured to perform a process to decrement the TTL value stored in the TTL memory, when the first sequence number and the second sequence number are identical according to a judgment; and a cluster information updating unit configured to separate the first node apparatus from the cluster, when the TTL value for the first node apparatus becomes equal to or smaller than a prescribed value. | 01-22-2015 |
20150023214 | NODE APPARATUS AND COMMUNICATION METHOD - A node apparatus in a network including a plurality of node apparatuses includes: a cluster information memory configured to store apparatus identification information of node apparatus included in a first cluster including the node apparatus; a merge cluster node number determination unit configured to obtain the number of node apparatuses included in the second cluster based on information included in the hello packet upon receipt of a hello packet from one of adjacent node apparatuses included in a second cluster, and to determine whether a sum of the number of node apparatuses included in the first cluster and that of node apparatuses included in the second cluster is equal to or smaller than a maximum number of cluster nodes; and a cluster merge processing unit configured to merge the second cluster with the first cluster based on a result of the determination. | 01-22-2015 |
Patent application number | Description | Published |
20080241972 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, PATTERN CORRECTION APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device includes measuring a first width of a first mask pattern formed in a photomask and a second width of a second mask pattern formed in the photomask, and deciding a temperature of heat treatment of a thickening material over a resist film based on measured results. | 10-02-2008 |
20090130603 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: forming a resist film above a semiconductor wafer having a layer to be processed, the resist film not being formed on a circumferential portion of the semiconductor wafer; exposing the resist film; after exposing the resist film, forming a resist pattern by developing the resist film; after forming the resist pattern by developing the resist film, cleaning the semiconductor wafer by supplying a thinner to the circumferential portion of the semiconductor wafer; and after cleaning the semiconductor wafer, processing the layer to be processed of the semiconductor wafer using the resist pattern. | 05-21-2009 |
20110043783 | ILLUMINATION OPTICAL SYSTEM, EXPOSURE METHOD AND DESIGNING METHOD - Exposure for performing patterning in which micropatterns differing in pitch exist in close vicinity to one another is handled, and micropatterns are formed with high accuracy with sufficient manufacture process margins without using a photomask complicated in manufacturing process at high manufacture cost like an alternating phase shift mask. A light intensity distribution of irradiation light constituted of double pole illuminations is formed to correspond to L&S patterns. The double pole illumination is constituted of a pair of illumination modes, and the double pole illumination is constituted of a pair of illumination modes. | 02-24-2011 |
Patent application number | Description | Published |
20100124007 | MEDIUM DRIVE UNIT AND ELECTRONIC EQUIPMENT - A medium drive unit includes a frame having an operating section, on a rear surface of which facing the main body side of the frame is provided a projection projecting toward the button, and which, upon receiving a depression operation from an outer surface side facing the outside, is biased toward the main body side and pushes the button with the leading end of the projection, a frame main body which surrounds the operating section so as to be separated from the operating section by an opening which extends surrounding the operating section, and passes through the front and rear surfaces of the frame, and an elastic support piece which extends through the opening along an edge of the operating section adjacent to the opening, of which one end is connected to the frame main body and the other end to the operating section. | 05-20-2010 |
20130021728 | DISPLAY DEVICE AND ELECTRONIC APPARATUS - A display device includes: a display panel; a first housing attached to the display panel, the first housing having an opening to expose a display surface of the display panel; and a second housing attached to the first housing to cover a back surface of the display panel, wherein an end portion of one of the first housing and the second housing includes a folded portion and an end portion of the other of the first housing and the second housing includes an insertion portion to be inserted into the end portion. | 01-24-2013 |
20130215561 | ELECTRONIC DEVICE - There is provided an electronic device which includes a housing, an opening formed in the housing, a light receiving unit which is disposed inside the housing and is configured to receive an optical signal which enters through the opening, and an optical path changing unit which changes, to guide to the light receiving unit, a travelling direction of at least one of a first optical signal arriving from a first direction in respect to the housing and a second optical signal arriving from a second direction in respect to the housing, the first and second directions being opposite each other. | 08-22-2013 |
20140168937 | LIGHTING DEVICE AND ELECTRONIC DEVICE - A lighting device includes a light source which is disposed in a vicinity of a part to be lighted and provided for a function other than lighting the part to be lighted, and a light projecting part which is movable between a lighting position and a non-lighting position and configured to emit the light from the light source to the part to be lighted when the light projecting part is moved to the lighting position. | 06-19-2014 |
20150061479 | EXTERIOR CASE AND ELECTRONIC DEVICE - An exterior case includes a first member to which a hinge bracket is attached, a fastener portion being a portion of the first member surrounding a hole in the first member, and being thickened in a thickness direction of the first member, a second member that is fixed to the first member and surrounds the fastener portion of the first member, and at least one fastener screw screwed into the hole to fasten the first member and the second member together and to fasten the hinge bracket to the first member. | 03-05-2015 |
20150062808 | INFORMATION PROCESSING DEVICE - An information processing device includes a first case, a second case over which the first case is placeable, and a connector including a first rotation part and a second rotation part and configured to couple the first case on the second case, the first rotation part allowing the first case to be rotated about a first axis, the second rotation part allowing the first case to be rotated about a second axis, the second axis being displaced from a central position of the first case in an axial direction of the first axis, wherein when front and back surfaces of the first case are reversed and the first case is placed over the second case, at least part of the first case projects from the second case toward an outer side. | 03-05-2015 |
Patent application number | Description | Published |
20090027988 | Memory device, memory controller and memory system - An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals. | 01-29-2009 |
20100146201 | MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM - Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks. | 06-10-2010 |
20100172200 | MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM - Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks. | 07-08-2010 |