Patent application number | Description | Published |
20110312041 | DNA POLYMERASES WITH INCREASED 3'-MISMATCH DISCRIMINATION - Disclosed are mutant DNA polymerases having increased 3′-mismatch discrimination relative to a corresponding, unmodified polymerase. The mutant polymerases are useful in a variety of disclosed primer extension methods. Also disclosed are related compositions, including recombinant nucleic acids, vectors, and host cells, which are useful, e.g., for production of the mutant DNA polymerases. | 12-22-2011 |
20120258501 | DNA POLYMERASES WITH IMPROVED ACTIVITY - Disclosed are DNA polymerases having increased reverse transcriptase efficiency, mismatch tolerance, extension rate and/or tolerance of RT and polymerase inhibitors relative to a corresponding, unmodified polymerase. The polymerases are useful in a variety of disclosed primer extension methods. Also disclosed are related compositions, including recombinant nucleic acids, vectors, and host cells, which are useful, e.g., for production of the DNA polymerases. | 10-11-2012 |
20130280697 | HEV Assay - A method of simultaneously amplifying genotypes 1, 2, 3 and/or 4 of HEV is disclosed comprising amplifying the genotypes 1, 2, 3 and/or 4 of HEV with one single none-degenerate forward primer partially overlapping the 5′UTR region of HEV and at least one reverse primer. Also disclosed are related methods comprising a probe, and kits for the detection of genotypes 1, 2, 3 and/or 4 of HEV. | 10-24-2013 |
20150176059 | OLIGONUCLEOTIDE INHIBITOR OF DNA POLYMERASES - The invention comprises a reversible oligonucleotide inhibitor of nucleic acid polymerases. Methods of designing said inhibitors and using said inhibitors in amplification and detection of nucleic acid, particularly detection of RNA by RT-PCR are also disclosed. | 06-25-2015 |
20150191708 | DNA POLYMERASES WITH IMPROVED ACTIVITY - Disclosed are DNA polymerases having increased reverse transcriptase efficiency, mismatch tolerance, extension rate and/or tolerance of RT and polymerase inhibitors relative to a corresponding, unmodified polymerase. The polymerases are useful in a variety of disclosed primer extension methods. Also disclosed are related compositions, including recombinant nucleic acids, vectors, and host cells, which are useful, e.g., for production of the DNA polymerases. | 07-09-2015 |
Patent application number | Description | Published |
20130042032 | Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices - Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device. Thus, the initiator device may not transmit the transaction request again until it has received the credit grant, whereupon it may transmit it along with a credit grant indicator such that it is sure that it will be accepted. | 02-14-2013 |
20130042034 | SYNCHRONISATION OF DATA PROCESSING SYSTEMS - A centralised synchronising device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system in response to receipt of a system synchronising request, the data processing system having a plurality of devices including a plurality of transaction request generating devices for generating the transaction requests and a plurality of recipient devices for receiving the transaction requests, the synchronising device and at least one interconnect for interconnecting at least some of the devices; wherein the system synchronising request comprising a request generated by one of the plurality of transaction generating devices and querying progress of the at least a subset of the transaction requests;
| 02-14-2013 |
20130042070 | Shared cache memory control - A data processing system | 02-14-2013 |
20130042077 | Data hazard handling for copending data access requests - A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. The data processing system process write requests in a two part form, such that a first part is transmitted and when the coherency controller has space to accept data it responds to the first part and the data and state of the data prior to the write are sent as a second part of the write request. When there are copending reads and writes to the same address the writes are stalled by the coherency controller by not responding to the first part of the write and the initiator device proceeds to process any snoop requests received to the address of the write regardless of the fact that the write is pending. When the pending read has completed the coherency controller will respond to the first part of the write and the initiator device will complete the write by sending the data and an indicator of the state of the data following the snoop. The coherency controller can then avoid any potential data hazard using this information to update memory as required. | 02-14-2013 |
20130042078 | Snoop filter and non-inclusive shared cache memory - A data processing apparatus | 02-14-2013 |
20130042249 | Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels - An integrated circuit | 02-14-2013 |
20130042252 | Processing resource allocation within an integrated circuit - An integrated circuit | 02-14-2013 |
20150248138 | STORAGE CIRCUITRY AND METHOD FOR PROPAGATING DATA VALUES ACROSS A CLOCK BOUNDARY - A storage circuit and method are provided for propagating data values across a clock boundary between a first clock domain and a second clock domain. A storage structure is provided with at least one entry, and write circuitry performs write operations in the first clock domain, where each write operation writes a data value into an entry of the storage structure identified by a write pointer. The write circuitry alters the write pointer between each write operation. Write pointer synchronisation circuitry then receives the write pointer and synchronises the write pointer indication to the second clock domain over a predetermined number of clock cycles of the second clock domain. Read circuitry performs read operations in the second clock domain, with each read operation reading a data value from an entry of the storage structure identified by a read pointer. However, for a read operation to be performed, it is necessary that the synchronised write pointer indication indicates that there is a data value written into the storage structure that is available to be read. Early update circuitry is configured, for a write operation, to alter the write pointer indication provided to the write pointer synchronisation circuitry a number of clock cycles of the first clock domain before the write operation is performed. That number of clock cycles is chosen dependent on the difference in clock speed between the first clock domain and the second clock domain, and the predetermined number of clock cycles of the second clock domain taken by the write pointer synchronisation circuitry to synchronise the write pointer indication to the second clock domain. Such an approach enables at least a part of the latency of the write pointer synchronisation circuitry to be hidden, thereby improving performance of the storage circuitry. | 09-03-2015 |
20160034403 | ACCESS SUPPRESSION IN A MEMORY DEVICE - A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced. | 02-04-2016 |
Patent application number | Description | Published |
20100094897 | UNIFIED FORMAT FOR DIGITAL CONTENT METADATA - A method and system to provide a unified format for digital content metadata are described. The system may include a module to obtain source data associated with media content; a module to identify, based on the source data, the media content; an extractor to obtain metadata associated the identified content; and a converter to format the obtained metadata according to the popular music format. The popular music format is a tree field format, where the fields are to store the title of the album, the title of the track, and the name of the artist. | 04-15-2010 |
20140278071 | ESTIMATING TIMES TO LEAVE AND TO TRAVEL - In an embodiment, a data processing method comprises obtaining a present location value indicating a present location of a computing device and event data indicating an event location and an event time; determining a route of travel between the present location and the event location for a mode of transportation from the present location to the event location; determining one or more route segments in the route of travel; determining one or more estimated journey times respectively for each of the route segments; adding one or more padding time values to each of the route segments; determining a total travel time based upon the journey times and the padding time values for all of the route segments; determining a recommended time to leave based upon a current time and a difference between the event time and the total travel time; wherein the method is performed by one or more computing devices. | 09-18-2014 |
20140278086 | USING HISTORICAL LOCATION DATA TO IMPROVE ESTIMATES OF LOCATION - In an embodiment, a data processing method comprises obtaining, from a calendar database associated with a particular mobile computing device, an event record specifying an event, and a date value and a time value indicating a date and time of the event; obtaining, from a user location history table accessible to a server computer, historical location data specifying a plurality of past geographical locations of the particular mobile computing device; using the server computer, determining, based upon the plurality of past geographical locations of the particular mobile computing device, a predicted location of the event; based upon the predicted location of the event, a current location of the particular mobile computing device, and mode data specifying a particular mode of transportation, calculating a route of travel between the current location and the predicted location and an estimated duration of travel; determining, based upon the date value, time value, route of travel and estimated duration of travel, a recommended time to leave to arrive at the predicted location of the event approximately on time. | 09-18-2014 |