Komirenko
Sergiy Komirenko US
Patent application number | Description | Published |
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20130080982 | Simulation And Correction Of Mask Shadowing Effect - Disclosed are techniques for simulating and correcting the mask shadowing effect using the domain decomposition method (DDM). According to various implementations of the invention, DDM signals for an extreme ultraviolet (EUV) lithography mask are determined for a plurality of azimuthal angles of illumination. Base on the DDM signals, one or more layout designs for making the mask may be analyzed and/or modified. | 03-28-2013 |
20130104091 | Tolerable Flare Difference Determination - Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions. | 04-25-2013 |
Sergiy M. Komirenko, Cupertino, CA US
Patent application number | Description | Published |
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20120047473 | Layout Decomposition Based on Partial Intensity Distribution - Layout design data are decomposed for double dipole lithography based on partial intensity distribution information. The partial intensity distribution information is generated by performing optical simulations on the layout design data. The layout decomposition may further be adjusted during an optical proximity correction process. The adjustment may utilize the partial intensity distribution information. | 02-23-2012 |
Sergly M. Komirenko, Cupertino, CA US
Patent application number | Description | Published |
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20100223590 | Mask Decomposition for Double Dipole Lithography - Method and apparatus for generating a pair of layouts suitable for forming exposure mask to use in a double dipole lithographic process are disclosed. With some implementations, a y-dipole layout and an x-dipole layout are generated by decomposing a target layout. Subsequently, an optical proximity correction process is implemented on the y-dipole layout and the x-dipole layout. The decomposition may designate ones of the edge segments in the target layout at major edge segments and other ones of the edge segments as minor edge segments. A higher feedback value may then be assigned to the minor edges than the major edges. Subsequently, a few iterations of an optical proximity correction process that utilizes a smaller than intended mask rule constraint value and the assigned feedback values is implemented on the target layout. The minor edges separated by a distance of less than the intended mask rule constraint distance are then collapsed. After which, a few iterations of the optical proximity correction process are allowed to iterate. In further implementations, once the y-dipole and x-dipole layouts have been generated. An additional optical proximity correction process is implemented on the layouts. During this optical proximity correction process, a higher feedback values is again assigned to the minor edge segments. At a point during the optical proximity correction process, minor edges within portions of the layouts that have a bias value larger than a predetermined value are expanded back from their collapsed position. | 09-02-2010 |