Wu, Palo Alto
Alan Wu, Palo Alto, CA US
Patent application number | Description | Published |
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20080311606 | Platelet Activation Markers and Predictors of Desease and of Response to Therapy and for Monitoring Therapeutic Progress - Methods for assessing patient risk for platelet-affected disease states are disclosed. Also disclosed are methods for predicting the appropriateness of platelet antagonist therapy, and for monitoring patients during therapeutic intervention or during a combined regimen of therapy and angioplasty. | 12-18-2008 |
20090233299 | Physiogenomic Method for Predicting Statin Injury to Muscle and Muscle Side Effects - The present invention relates to the use of genetic variants of associated marker genes to predict an individual's susceptibility to muscular injury and muscular side effects in response to statin therapy. The present invention further relates to analytical assays and computational methods using the novel marker gene set. The present invention has utility for personalized medical treatment, drug safety, statin compliance, and prophylaxis of muscle side effect. | 09-17-2009 |
20100173339 | PLATELET ACTIVATION MARKERS AS INDICATORS FOR ANTI-PLATELET THERAPY - Methods for determining the appropriateness of anti-platelet therapy in a patient with a platelet-affected disease. The Mean Platelet Component value in a patient blood sample is determined corresponding to the patient's platelet activation status. A high platelet activation status indicates the appropriateness of anti-platelet therapy. | 07-08-2010 |
20110111524 | Highly Sensitive System and Method for Analysis of Troponin - The invention provides methods, compositions, kits, and systems for the sensitive detection of cardiac troponin. Such methods, compositions, kits, and systems are useful in diagnosis, prognosis, and determination of methods of treatment in conditions that involve release of cardiac troponin. | 05-12-2011 |
20130237438 | PHYSIOGENOMIC METHOD FOR PREDICTING STATIN INJURY TO MUSCLE AND MUSCLE SIDE EFFECTS - The present invention relates to the use of genetic variants of associated marker genes to predict an individual's susceptibility to muscular injury and muscular side effects in response to statin therapy. The present invention further relates to analytical assays and computational methods using the novel marker gene set. The present invention has utility for personalized medical treatment, drug safety, statin compliance, and prophylaxis of muscle side effect. | 09-12-2013 |
Alan H.b. Wu, Palo Alto, CA US
Patent application number | Description | Published |
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20080261242 | Highly Sensitive System and Methods for Analysis of Troponin - The invention provides methods, compositions, kits, and systems for the sensitive detection of cardiac troponin. Such methods, compositions, kits, and systems are useful in diagnosis, prognosis, and determination of methods of treatment in conditions that involve release of cardiac troponin. | 10-23-2008 |
20100297672 | HIGHLY SENSITIVE SYSTEM AND METHODS FOR ANALYSIS OF TROPONIN - The invention provides methods, compositions, kits, and systems for the sensitive detection of cardiac troponin. Such methods, compositions, kits, and systems are useful in diagnosis, prognosis, and determination of methods of treatment in conditions that involve release of cardiac troponin. | 11-25-2010 |
Albert Wu, Palo Alto, CA US
Patent application number | Description | Published |
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20080246015 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 10-09-2008 |
20080258291 | Semiconductor Packaging With Internal Wiring Bus - A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies. | 10-23-2008 |
20090017593 | METHOD FOR SHALLOW TRENCH ISOLATION - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 01-15-2009 |
20090212410 | STACK DIE PACKAGES - An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact. A first wire connects the first contact to the second contact. A flip-chip integrated circuit comprises a third contact connected to the trace by a conductive bump. A second integrated circuit mechanically coupled to the flip-chip integrated circuit. The second integrated circuit comprises a fourth contact. A second wire connects the fourth contact to at least the second contact or the first contact. | 08-27-2009 |
20100140760 | ALPHA SHIELDING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed. | 06-10-2010 |
20100173452 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 07-08-2010 |
20100301467 | WIREBOND STRUCTURES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor die, a bond pad formed on the semiconductor die, the bond pad comprising aluminum (Al), a bonding material comprising gold (Au) coupled to the bond pad, the bonding material covering at least a portion of the bond pad, and a wire coupled to the bonding material, the wire comprising copper (Cu). Other embodiments may be described and/or claimed. | 12-02-2010 |
20110121444 | EMBEDDED CHIP PACKAGES - Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed. | 05-26-2011 |
20110148312 | INTEGRATED BUCK POWER SUPPLY ARCHITECTURES FOR LED-BASED DISPLAYS - A system includes a plurality of light emitting diodes (LEDs) and a control module configured to generate pulse width modulated (PWM) pulses to drive the LEDs. The LEDs and the control module are integrated in an integrated circuit (IC) package. | 06-23-2011 |
20110169163 | ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. | 07-14-2011 |
20110175218 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 07-21-2011 |
20110180913 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed. | 07-28-2011 |
20110186960 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110186992 | RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110186998 | RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110227223 | EMBEDDED DIE WITH PROTECTIVE INTERPOSER - Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed. | 09-22-2011 |
20120098127 | POWER/GROUND LAYOUT FOR CHIPS - Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip. | 04-26-2012 |
20120319231 | Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 12-20-2012 |
20130026609 | PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE WITH STRESS RELIEF STRUCTURE - An apparatus configured to be coupled onto a substrate, wherein the apparatus comprises a semiconductor substrate and the semiconductor substrate includes a plurality of trenches defined within a side of the semiconductor substrate. The apparatus further comprises an interconnect layer over portions of the side of the semiconductor substrate, wherein the portions of the side of the semiconductor substrate include the plurality of trenches defined within the side of the semiconductor substrate. Each trench is configured to respectively receive a solder ball to provide an interface between i) the interconnect layer and ii) the substrate to which the apparatus is to be coupled. | 01-31-2013 |
20130143366 | ALPHA SHIELDING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed. | 06-06-2013 |
20130147025 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - A first chip is mounted on a substrate and includes a plurality of bump pads located on an active surface of the first chip. A wire bonds a first bump pad to the substrate. An intermediate layer is disposed on a portion of the active surface of the first chip, and a via within the intermediate layer extends to a second bump pad. A second chip is disposed on the intermediate layer, and wherein the second chip includes a third bump pad located on an active surface of the second chip and aligned with the via formed in the intermediate layer. A corresponding bump is disposed on one or more of the second bump pad and the third bump pad, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. | 06-13-2013 |
20140041916 | METHODS OF MAKING PACKAGES USING THIN CU FOIL SUPPORTED BY CARRIER CU FOIL - In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer. | 02-13-2014 |
20140080285 | METHOD AND APPARATUS FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES HAVING ROUNDED CORNERS - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 03-20-2014 |
20140104924 | APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS - A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch. | 04-17-2014 |
20140104926 | SYSTEMS AND METHODS FOR READING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS - A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell. | 04-17-2014 |
20140104927 | CONFIGURING RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY FOR WRITE OPERATIONS - A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction. | 04-17-2014 |
20140104928 | METHOD AND APPARATUS FOR FORMING A CONTACT IN A CELL OF A RESISTIVE RANDOM ACCESS MEMORY TO REDUCE A VOLTAGE REQUIRED TO PROGRAM THE CELL - A cell of a resistive random access memory including a resistive element and an access device. The resistive element includes (i) a first electrode and (ii) a second electrode. The access device is configured to select and deselect the cell. The access device includes (i) a first terminal connected to a first contact and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact includes (i) a first surface in contact with the second contact and (ii) a second surface in contact with the second electrode. The first surface defines a first surface area, and the second surface defines a second surface area. The first surface area is greater than the second surface area. | 04-17-2014 |
20140106508 | STRUCTURES EMBEDDED WITHIN CORE MATERIAL AND METHODS OF MANUFACTURING THEREOF - Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die. | 04-17-2014 |
20140112057 | APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS - A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell. | 04-24-2014 |
20140124961 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 05-08-2014 |
20140170832 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR CONTROLLING MANUFACTURING OF CORRESPONDING SUB-RESOLUTION FEATURES OF CONDUCTIVE AND RESISTIVE ELEMENTS - A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory. | 06-19-2014 |
20140284635 | INTEGRATED POWER SUPPLY ARCHITECTURE FOR LIGHT EMITTING DIODE-BASED DISPLAYS - An integrated circuit including a die of the integrated circuit, the die including an insulating layer, light emitting diodes, a semiconductor layer, and a control module. The insulating layer includes a first side and a second side. The second side is opposite to the first side. The light emitting diodes are arranged on the first side of the insulating layer. The semiconductor layer is arranged adjacent to the second side of the insulating layer. The light emitting diodes are connected to the semiconductor layer using connections from the first side of the insulating layer to the second side of the insulating layer. The control module is arranged on the semiconductor layer. The control module is configured to output pulse width modulated pulses to the light emitting diodes via the connections. | 09-25-2014 |
20150028422 | ANALOG CIRCUIT WITH IMPROVED LAYOUT FOR MISMATCH OPTIMIZATION - Embodiments include a semiconductor device comprising: a substrate; a first transistor formed on the substrate; and a second transistor formed on the substrate, wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor. | 01-29-2015 |
20150063004 | METHOD AND APPARATUS FOR REFORMING A MEMORY CELL OF A MEMORY - A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle. | 03-05-2015 |
20150124520 | RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE WITH REDUCED PROGRAMMING VOLTAGE - A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface. | 05-07-2015 |
20150155202 | POWER/GROUND LAYOUT FOR CHIPS - Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip. | 06-04-2015 |
20150200114 | ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. | 07-16-2015 |
20150221577 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 08-06-2015 |
20150228569 | METHOD AND APPARATUS FOR IMPROVING THE RELIABILITY OF A CONNECTION TO A VIA IN A SUBSTRATE - Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs. | 08-13-2015 |
20150244410 | METHOD AND APPARATUS FOR INCORPORATING PASSIVE DEVICES IN AN INTEGRATED PASSIVE DEVICE SEPARATE FROM A DIE - A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack. | 08-27-2015 |
20150279806 | RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed. | 10-01-2015 |
20150311147 | SEMICONDUCTOR PACKAGE WITH A SEMICONDUCTOR DIE EMBEDDED WITHIN SUBSTRATES - Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed. | 10-29-2015 |
20150318232 | METHOD AND APPARATUS FOR MOUNTING SOLDER BALLS TO AN EXPOSED PAD OR TERMINAL OF A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a package comprising a die attach pad, a die disposed on the die attach pad and a leadframe. The leadframe includes an opening defined therein that exposes a bottom surface of the die attach pad. The leadframe comprises a plurality of bond pads that are exposed at a bottom surface of the leadframe and a plurality of traces that are exposed at the bottom surface of the leadframe. Each trace of the plurality of traces is coupled to a corresponding bond pad of the plurality of bond pads. At least some of the traces are coupled to the die at top surfaces of the at least some of the traces. The leadframe also comprises a plurality of first insulated barriers. Each first insulated barrier is located between (i) a corresponding trace and (ii) a corresponding bond pad coupled to the corresponding trace. | 11-05-2015 |
20160087201 | RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE - A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell. | 03-24-2016 |
Allan H.b. Wu, Palo Alto, CA US
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20130130403 | Highly Sensitive System and Method for Analysis of Troponin - The invention provides methods, compositions, kits, and systems for the sensitive detection of cardiac troponin. Such methods, compositions, kits, and systems are useful in diagnosis, prognosis, and determination of methods of treatment in conditions that involve release of cardiac troponin. | 05-23-2013 |
20130252346 | Highly Sensitive System and Method for Analysis of Troponin - The invention provides methods, compositions, kits, and systems for the sensitive detection of cardiac troponin, Such methods, compositions, kits, and systems are useful in diagnosis, prognosis, and determination of methods of treatment in conditions that involve release of cardiac troponin. | 09-26-2013 |
20130288383 | Highly Sensitive System and Method for Analysis of Troponin - The invention provides methods, compositions, kits, and systems for the sensitive detection of cardiac troponin. Such methods, compositions, kits, and systems are useful in diagnosis, prognosis, and determination of methods of treatment in conditions that involve release of cardiac troponin. | 10-31-2013 |
Bicheng Wu, Palo Alto, CA US
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20140160884 | APPARATUS AND SYSTEM FOR ADAPTIVELY SCHEDULING ULTRASOUND SYSTEM ACTIONS - Apparatus for adaptively scheduling ultrasound device actions includes a probe interface, a beamer, a receiver, a processor, and a memory. The probe interface may interface with probe units to transmit signals generated by the beamer to the probe units and to receive data signals from the probe units. The processor may be coupled to the probe interface, the beamer, and the receiver. The memory may store instructions, which when executed by the processor, causes the processor to generate a task list that includes a timed beam firing sequence and to signal to the beamer to generate signals to the probe units associated with the plurality of task actions. The task list may include a plurality of task actions associated with probe units, and the processor may signal to the beamer in accordance with the timed beam firing sequence. Other embodiments are also described. | 06-12-2014 |
20140160894 | METHOD FOR ADAPTIVELY SCHEDULING ULTRASOUND SYSTEM ACTIONS - A method of adaptively scheduling ultrasound device actions starts with an electronic circuit included in an adaptive scheduler selecting a next task in a task list. The task list may include tasks scheduled to be performed by an ultrasound system. Each of the tasks may include a plurality of task actions. The electronic circuit may then determine if a task action included in the next task can start. This determination may include determining if the task action can be completed without interfering with a start of a higher priority task in the task list. When the electronic circuit determines that the next task action can start, the electronic circuit may signal to a beam associated with the task action to start and perform the task action. Other embodiments are also disclosed. | 06-12-2014 |
20140160895 | APPARATUS AND SYSTEM FOR REAL-TIME EXECUTION OF ULTRASOUND SYSTEM ACTIONS - Apparatus for real-time execution of ultrasound system actions includes processor and memory to store instructions. Execution of the instructions causes processor to receive a task list including task actions that include next task action in task list. Next task action includes task instructions. Processor determines whether next task instruction in next task action is a timed instruction that includes a timestamp field having a time value indicating a time at which next task action is to be executed, and a hardware-enable field indicating hardware elements required to be available before execution of timed instruction. If next task instruction is not a timed instruction, processor may execute next task instruction. If next task instruction is timed instruction, processor determines whether time value has expired. If time value has expired, processor signals an error has occurred, and if time value has not expired, processor waits for time value. Other embodiments are described. | 06-12-2014 |
20140163370 | SYSTEM AND METHOD FOR AUTOMATICALLY ADJUSTING BEAMS TO SCAN AN OBJECT IN A BODY - A method of scanning for an object using an adaptive scheduler starts with an electronic circuit (EC) receiving information associated with the object. A task list is then generated by the EC that includes at least one task action based on the information associated with the object. The at least one task action includes a beam firing required for the object to be scanned. The EC may signal based on the task list to a beamer to generate and send a signal to a probe unit to perform the beam firing. A receiver may receive and process a data signal from the probe unit and send the processed data signals to the EC. The EC may then analyze the processed data signal to determine if the object is identified using the processed data signal. Other embodiments are also described. | 06-12-2014 |
20140165069 | SYSTEM AND APPARATUS HAVING AN APPLICATION PROGRAMMING INTERFACE FOR FLEXIBLE CONTROL OF EXECUTION ULTRASOUND ACTIONS - Apparatus to control and execute ultrasound system actions includes API that includes API procedure, processor coupled to API, adaptive scheduler, and memory. Adaptive scheduler includes beamer to generate signals, probe interface to transmit the signals to at least one probe unit and to receive signals from the at least one probe unit, and receiver to receive and process the signals received from the probe interface. Memory stores instructions, which when executed, causes processor to receive task list including task actions. Processor may execute API procedure to generate scan specification that is a data structure that includes task list. Processor may execute API procedure to identify at least one of: a probe required to perform the task actions, a beam required to perform the task actions and requirements and parameters associated with the beam, or a format of a beam firing result. Other embodiments are described. | 06-12-2014 |
20140171798 | SYSTEM AND METHOD FOR SCANNING FOR A SECOND OBJECT WITHIN A FIRST OBJECT USING AN ADAPTIVE SCHEDULER - Method for scanning for second object on or within first object starts by receiving information on first object and second object. Task lists are generated that include at least one task action based on information on first object and second object. Based on task lists, beamer is then signaled to generate and send first signal to first probe unit to perform first beam firing. Receiver processes first data signal from first probe unit that is then analyzed to determine if first object is identified using processed first data signal. Upon determination that first object is identified, based on task list, beamer is signaled to generate and send second signal to second probe unit to perform second beam firing. Receiver processes second data signal from second probe unit that is then analyzed to determine if second object is identified using processed second data signal. Other embodiments are described. | 06-19-2014 |
Carol C. Wu, Palo Alto, CA US
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20120117492 | METHOD, SYSTEM AND APPARATUS FOR PROCESSING CONTEXT DATA AT A COMMUNICATION DEVICE - A method and apparatus for processing context data at a communication device is provided. Icon data associated with an application is rendered at a display device, thereby providing rendered icon data at the display device, the icon data and the application stored at a memory. Context data associated with the application is determined by retrieving at least a first portion of the context data from a calendar database, the context data for rendering within the application when the application is executed by a processor and rendered at the display device. A portion of the rendered icon data is updated such that the rendered icon data comprises at least a subset of the context data. When the rendered icon data is actuated, the application is responsively executed at the processor such that the context data is rendered at the display device within a rendering of the application. | 05-10-2012 |
20120117499 | METHODS AND APPARATUS TO DISPLAY MOBILE DEVICE CONTEXTS - Example methods and apparatus to display mobile device contexts are disclosed. An example method includes displaying a first context in a user interface of a mobile device based on first device platform information, the first context including a first arrangement of information, graphics, and application icons that are associated with the first device platform information, determining that second device platform information received after the first device platform information corresponds to a second context, the second context being different from the first context and including a second arrangement of information, graphics, and applications that are associated with the second device platform information, and displaying the second context in the user interface replacing the first context without prompting a user of the mobile device. | 05-10-2012 |
20120278080 | COMMUNICATION DEVICE FOR DETERMINING CONTEXTUAL INFORMATION - A method and communication device for determining contextual information is provided. Textual information is received from at least one of an input device and a communication interface at the communication device. The textual information is processed to automatically extract contextual data embedded in the textual information in response to the receiving. Supplementary contextual data is automatically retrieved based on the contextual data from a remote data source via the communication interface in response to the processing. The supplementary contextual data is automatically rendered at the display device in association with the contextual data in response to receiving the supplementary contextual data. | 11-01-2012 |
Charles Qingle Wu, Palo Alto, CA US
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20090086857 | Reduced voltage subLVDS receiver - A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals. | 04-02-2009 |
20090153219 | Replica bias circuit for high speed low voltage common mode driver - A transmitter provides fast settling times, slew rate control, and power efficiency while reducing the need for large external capacitors. The transmitter typically includes a pre-driver, driver, and replica circuit. The pre-driver can shift the voltage level of an input signal to produce a shifted signal. The pre-driver can shift the voltage level in response to a selectable load resistance circuit and a voltage regulation feedback signal. The driver receives the shifted signal and generates a driver output signal in response to the received shifted signal. The replica circuit can be a scaled replica of the pre-driver and the driver using scaled components from the pre-driver and driver circuits. The scaled components can be used to generate the voltage regulation feedback signal. The generated voltage regulation feedback signal represents, for example, whether the output voltage of the driver output is above a reference voltage. | 06-18-2009 |
20090180570 | HYBRID ON-CHIP REGULATOR FOR LIMITED OUTPUT HIGH VOLTAGE - A driver circuit provides fast settling times, slew rate control, and power efficiency, while reducing the need for large external capacitors. A voltage reference circuit generates a voltage reference signal. A comparator compares the voltage reference signal and a driver output signal and generates an output high voltage control signal. An output driver includes a first and a second switch that are coupled together. The first and second switches are further coupled to generate the driver output signal in response to coupling the output high voltage control signal to the control terminal of the first switch and coupling an input signal to the control terminal of the second switch. | 07-16-2009 |
20100315053 | HYBRID ON-CHIP REGULATOR FOR LIMITED OUTPUT HIGH VOLTAGE - A driver circuit includes a pre-driver and an output driver. The pre-driver is coupled to receive an input signal and to generate first and second pre-driver output signals in response to the input signal. The output driver generates a driver output signal and includes first and second switches, a native mode transistor, and a driver output. The first switch has a first control terminal coupled to receive the first pre-driver output signal. The second switch has a second control terminal coupled to receive the second pre-driver output signal. The native mode transistor is coupled in series between the first switch and the second switch and has a third control terminal coupled to receive the voltage reference signal. The driver output is coupled between the native mode transistor and the second switch to output the driver output signal. | 12-16-2010 |
20120307122 | LOW COMMON MODE DRIVER - Techniques to provide a replica bias circuit for a high speed and low voltage common mode driver. In an embodiment, a pre-driver is coupled to provide driver input voltages to the driver, which driver includes a set of circuit elements coupled to provide, based on the driver input voltages, an output signal of a differential output. In another embodiment, a regulator circuit is coupled to provide regulated power to the pre-driver and driver, where the regulator circuit includes a scale replica circuit having a replica of the first set of circuit elements. | 12-06-2012 |
20140132592 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING PRE-EMPHASIS IN A SIGNAL - A transmitter for generating a differential signal pair including a pre-emphasis component. In an embodiment, the transmitter comprises pre-driver circuitry including an input to receive a single-ended data signal. The differential transmitter further comprises a load circuit coupled between the input and a node coupled to an output of the pre-driver circuitry which corresponds to a constituent signal of the differential signal pair. In another embodiment, the load circuit is configurable to provide a signal path between the input and the node. A configuration of the load circuit allows for a type of pre-emphasis to be included in the constituent signal. | 05-15-2014 |
20150192949 | Digital Calibration-Based Skew Cancellation for Long-Reach MIPI D-PHY Serial Links - A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode. | 07-09-2015 |
Chia Y. Wu, Palo Alto, CA US
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20100036948 | ZONING SCHEME FOR ALLOCATING SAS STORAGE WITHIN A BLADE SERVER CHASSIS - In a method for partitioning SAS storage within a blade server chassis, where the blade server chassis may include one of a plurality (N) of server blades, the same plurality (N) of SAS storage blades or any combination thereof up to a total of N blades, in order for the plurality of SAS storage blades to be securely shared by the plurality of server blades, a pair-based zoning scheme may be implemented whereby if a server blade and a disk blade occupy neighboring slots in the blade server chassis, a pair of the server blade and the disk blade may be set to belong in the same zone. Partitioning of SAS expansion ports within the blade server chassis may be accomplished by providing exclusive access of a single SAS expansion port to a server blade located in an even slot. | 02-11-2010 |
Dennis Wu, Palo Alto, CA US
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20080275727 | SYSTEM AND METHOD FOR ECONOMICAL REPRESENTATION OF PRODUCTS USING INTELLIGENCE CLUSTERING - A system includes a recommendation engine, product database and interface. The recommendation engine determines one or more recommended product clusters from the product database based on a request for a healthcare product recommendation based on a symptom. The interface, which is communicatively coupled to the engine, displays the one or more recommended product clusters. The product clusters are organized based on at least one common attribute, such as active ingredient. | 11-06-2008 |
Diane Wu, Palo Alto, CA US
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20160055501 | SYSTEM AND METHOD FOR DETERMINING A COHORT - A system and method is provided for determining a cohort. In one implementation a method is provided that can include acquiring user inputs and identifying, based on the user inputs, a plurality of entities sharing one or more attributes with a first entity. The method can also include acquiring information including one or more interactions associated with the first entity and the plurality of entities and creating a cohort by processing the one or more interactions to select other entities associated with the first entity. Selecting the other entities can be based on a similarity between attributes of consuming entities that are associated with the first entity and the other entities; a similarity between location information associated with the first entity and the other entities; a market share of the first entity and the other entities; and a wallet share of the first entity and the other entities. | 02-25-2016 |
Dongxiang Wu, Palo Alto, CA US
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20120036488 | Method and Apparatus for Automatic Relative Placement Rule Generation - Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level. | 02-09-2012 |
Fang Wu, Palo Alto, CA US
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20100223578 | POPULATING VARIABLE CONTENT SLOTS ON WEB PAGES - A respective novelty value is ascertained for each of multiple user-selectable contents. Each of the novelty values represents a level of newness of the respective user-selectable content in relation to the other user-selectable contents. A respective novelty decay value is calculated for each of the user-selectable contents as a decreasing function of the respective novelty value. A prioritization order of the user-selectable contents in respective prioritized positions on a web page is determined based on the novelty decay values. | 09-02-2010 |
20110197139 | Displaying Personalized Information in a Handheld Device - One embodiment is a handheld electronic device ( | 08-11-2011 |
20110319058 | Social Networking of Mobile Devices - A method for social networking of mobile devices based upon telephone numbers of the mobile devices includes receiving user profile information and telephone numbers of contacts from a plurality of users' mobile devices; at least one of creating and updating respective user profiles based upon the telephone numbers of the users' mobile devices and the received profile information; identifying relationships among the users based at least upon the contacts contained in the contacts information; and establishing a social network group including at least two of the users based upon the identified relationships among the users. | 12-29-2011 |
Ganlin Wu, Palo Alto, CA US
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20140185442 | SUPPORTING QUALITY OF SERVICE DIFFERENTIATION USING A SINGLE SHARED BUFFER - An example method, system, and switching element are provided and may provide for an egress port to be configured to receive a plurality of data packets, each of the plurality of data packets being a class of a plurality of classes. A buffer may communicate with the at least one data port interface. A memory management unit may be configured to enable and disable transmission of the plurality of classes of the plurality of data packets based on a metering policy; and place the plurality of data packets in the buffer. | 07-03-2014 |
Hailin Wu, Palo Alto, CA US
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20150379528 | SOCIAL NETWORK USAGE-BASED SALES INSIGHTS - In an example embodiment, information about one or more Customer Relationship Management (CRM) entities is received from a CRM system, the information including an identification of each of the one or more CRM entities and usage information about how a user interacted with each of the one or more CRM entities. Then, at a software tool distinct from the CRM system, one or more actionable insights related to the one or more CRM entities are identified. The relevance of the one or more actionable insights to the user is then determined based on the usage information. One or more of the one or more actionable insights are then presented to the user based on the determined relevance via the software tool. | 12-31-2015 |
20160092940 | DE-DUPLICATING COMBINED CONTENT - A system, method, and apparatus for de-duplicating and serving a combined content feed are provided. The combined content includes items of two or more classes, such as sponsored and unsponsored, wherein some or all unsponsored content items may be sponsored. A feed service obtains sponsored and unsponsored items suitable for a user to whom the combined content feed is to be served. The service determines whether an item is duplicated among the multiple classes. If so, a distance between the duplicates is calculated (within the feed). If the distance is less than a first threshold, one of them is discarded and may or may not be replaced. A decision regarding which to eject may depend upon which version (e.g., sponsored or unsponsored) is positioned earlier in the feed, whether the duplicates are also less than a second threshold apart (which is lower than the first threshold), and/or other factors. | 03-31-2016 |
Hsien-Hsun Wu, Palo Alto, CA US
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20160069699 | APPARATUS, SYSTEM AND METHOD FOR CLUSTERING POINTS OF INTEREST IN A NAVIGATION SYSTEM - A navigation system, apparatus and method utilizing a processor and a sensor, operatively coupled to the processor to determine a location of the navigation system. A navigation input module is configured to receive destination data specifying a destination and a plurality of point-of-interest (POI) data from a user, where the navigation input module is further configured to receive a POI search area value defining an area of search for the POI data from potential route segments. The processor may utilize the POI search area value to search a plurality of areas along the potential route segments to identify at least some of the plurality of POI data that are in closest proximity to the destination, and wherein the processor may be further configured to cluster the identified POI data for simultaneous presentation on a navigational map. | 03-10-2016 |
Joseph Wu, Palo Alto, CA US
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20110118333 | Use on Minicircle vectors for cardiac gene therapy - Compositions and methods are provided for the treatment of an ischemic cardiovascular condition by providing a patient with a novel non-viral minicircle DNA vector comprising polynucleotide sequences that potentiate HIF-1 activity, including RNAi or antisense agents selective for proteins involved in HIF1 inactivation. | 05-19-2011 |
20110244566 | Enhanced efficiency of induced pluripotent stem cell generation - Human somatic cells are reprogrammed to become induced pluripotent stem cells (iPS cells) by the introduction of a minicircle DNA vector. Cells of interest include adipose stem cells. | 10-06-2011 |
Joseph C. Wu, Palo Alto, CA US
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20120004283 | NOVEL SHRNA GENE THERAPY FOR TREATMENT OF ISCHEMIC HEART DISEASE - Short hairpin RNA (shRNA) interference therapy targeting hypoxia inducible factor—lot (HIF-1 α) prolyl-4-hydroxylase protein (HIF-PHD2) is used for treatment of myocardial ischemia. This treatment can be followed noninvasively by molecular imaging. Provided are compositions comprising novel vectors encoding shRNA targeting the HIF-1α and asparaginyl hydroxylase genes. The vectors encoding shRNA are also useful for the treatment of cardiac diseases, peripheral vascular diseases and decubitis ulcers. | 01-05-2012 |
Joseph Ching-Ming Wu, Palo Alto, CA US
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20090176260 | Double-fusion human embryonic stem cells, methods of making double-fusion human embryonic stem cells, triple-fusion human embryonic stem cells, methods of making triple-fusion human embryonic stem cells, and methods of monitoring double-fusion human embryonic stem cells and triple-fusion human embryonic stem cells - Embodiments of the present disclosure include double-fusion human embryonic stem cells, methods of imaging double-fusion human embryonic stem cells, double-fusion polynucleotides, double-fusion proteins, triple-fusion human embryonic stem cells, methods of imaging triple-fusion human embryonic stem cells, triple-fusion polynucleotides, triple-fusion proteins, methods of monitoring the progression of human embryonic stem cells, methods of making isolated double-fusion human embryonic stem cells, methods of making isolated triple-fusion human embryonic stem cells, and the like. | 07-09-2009 |
20120144506 | DOUBLE-FUSION HUMAN EMBRYONIC STEM CELLS, METHOD OF MAKING DOUBLE-FUSION HUMAN EMBRYONIC STEM CELLS, TRIPLE-FUSION HUMAN EMBRYONIC STEM CELLS, METHOD OF MAKING TRIPLE-FUSION HUMAN EMBRYONIC STEM CELLS, AND METHODS OF MONITORING DOUBLE-FUSION HUMAN EMBRYONIC STEM CELLS AND TRIPLE-FUSION HUMAN EMBRYONIC STEM CELLS - Embodiments of the present disclosure include double-fusion human embryonic stem cells, methods of imaging double-fusion human embryonic stem cells, double-fusion polynucleotides, double-fusion proteins, triple-fusion human embryonic stem cells, methods of imaging triple-fusion human embryonic stem cells, triple-fusion polynucleotides, triple-fusion proteins, methods of monitoring the progression of human embryonic stem cells, methods of making isolated double-fusion human embryonic stem cells, methods of making isolated triple-fusion human embryonic stem cells, and the like. | 06-07-2012 |
Juhao Wu, Palo Alto, CA US
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20160044771 | High-Gain Thompson-Scattering X-Ray Free-Electron Laser by Time-Synchronic Laterally Tilted Optical Wave - An improved optical undulator for use in connection with free electron radiation sources is provided. A tilt is introduced between phase fronts of an optical pulse and the pulse front. Two such pulses in a counter-propagating geometry overlap to create a standing wave pattern. A line focus is used to increase the intensity of this standing wave pattern. An electron beam is aligned with the line focus. The relative angle between pulse front and phase fronts is adjusted such that there is a velocity match between the electron beam and the overlapping optical pulses along the line focus. This allows one to provide a long interaction length using short and intense optical pulses, thereby greatly increasing the radiation output from the electron beam as it passes through this optical undulator. | 02-11-2016 |
Kenneth S. Wu, Palo Alto, CA US
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20110218518 | DEVICES AND METHODS FOR ACCESSING THE EPIDURAL SPACE - An apparatus for accessing the epidural space in a mammal has a cutting sheath with a distal end adapted to transition from a closed cutting configuration to an open configuration. A tissue engagement device is in a hollow portion of the sheath. The tissue engagement device has a blunt distal end and an engagement feature. A method of accessing an epidural space includes the step of forming an opening to a position at or near the ligamentum flavum using the cutting sheath. Another step of the method is positioning a tissue engagement device within the hollow portion of the cutting sheath. Another step of the method is transitioning the cutting sheath from the closed cutting configuration to the open configuration. Another step of the method is manipulating the tissue engagement device to controllably advance the tissue engagement device at least partially through the ligamentum flavum. | 09-08-2011 |
Lili Wu, Palo Alto, CA US
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20150112898 | SITE FLOW OPTIMIZATION - A method and system to present an optimum action in response to a flow of actions in a computer network from a user are provided. For each of a plurality of possible presented actions corresponding to a particular flow of actions in a computer network, and for each of one or more possible performed actions for each possible presented action, a likelihood that a user will perform the possible performed action is determined. Then each of the determined likelihoods is weighted by applying a weight assigned to a corresponding possible presented action. An optimum presented action is identified determining a presented action having a weighted maximum determined likelihood, based on the weighted determined likelihood. | 04-23-2015 |
20150339592 | SITE FLOW OPTIMIZATION - In an example embodiment, for each of a plurality of possible presented actions corresponding to a particular flow of actions in a computer network, and for each of one or more possible performed actions for each possible presented action, a likelihood that a user will perform the possible performed action is determined. Then, a first presented action is identified by determining a presented action having a maximum determined likelihood, based on the determined likelihood, wherein the identifying a first presented action includes utilizing a machine learning model having one or more user covariates and one or more performed action covariates, and interactions between the one or more user covariates and the one or more performed action covariates, the user covariates including information specific to the user, the one or more performed action covariates including information specific to one or more of the possible performed actions. | 11-26-2015 |
20150350354 | USER-ACTIVITY-BASED ROUTING WITHIN A WEBSITE - When a user of a social network accepts an invitation message to connect with another user of the social network, a system may use a history of user activity to determine where the user is subsequently directed within the social-network website. In particular, based on the history of user activity associated with an in-network page with recommendations for possible connections for the user within the network of users, the system may determine whether or not there have been too many impressions of the in-network page. If not, the system may present the in-network page with a recommendation for a possible in-network connection for the user within the network of users. Then, if the system receives a user selection of the possible in-network connection, the system may provide an invitation message inviting the possible in-network connection to connect with the user by activating a link in the invitation message. | 12-03-2015 |
20160034425 | PROVIDING RECOMMENDATIONS FOR ELECTRONIC PRESENTATIONS BASED ON CONTEXTUAL AND BEHAVIORAL DATA - Systems and methods are disclosed that recommend one or more electronic presentations to a user based on one or more factors. These factors may include contextual information, behavioral information, profile information, or combinations of the foregoing. Contextual information may include content and/or features extracted from a given electronic presentation. Behavioral information may include user behavioral data, such as the number of times a user has viewed a presentation, the amount of the presentation viewed by the user, presentations previously viewed by the user, and other such behavioral data. Profile information may include user professional profile information, such as skills the user has identified as possessing, employment history information, and other such user professional profile information. | 02-04-2016 |
Lingling Wu, Palo Alto, CA US
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20090214471 | USE OF PEGYLATED IL-10 TO TREAT CANCER - Provided are methods of treatment for tumors. In particular, methods are provided for use of a chemically modified IL-10 to treat tumors. | 08-27-2009 |
20110091419 | Use of Pegylated IL-10 to Treat Cancer - Provided are methods of treatment for tumors. In particular, methods are provided for use of a chemically modified IL-10 to treat tumors. | 04-21-2011 |
20150079031 | Use of Pegylated IL-10 to Treat Cancer - Provided are methods of treatment for tumors. In particular, methods are provided for use of a chemically modified IL-10 to treat tumors. | 03-19-2015 |
Lyndia Chun Wu, Palo Alto, CA US
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20140312834 | WEARABLE IMPACT MEASUREMENT DEVICE WITH WIRELESS POWER AND DATA COMMUNICATION - Described herein is a wearable device for impact measurement with wireless power and communication capability. The wearable device includes a base member configured for placement on a human body, an electronic board affixed to the base member, and a rechargeable battery affixed to the base member. The device also includes a dual-band antenna printed on the electronic board for wireless power and data communication. Also provided are methods for charging the wearable device with different power sources. | 10-23-2014 |
Michael Wu, Palo Alto, CA US
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20110216693 | Method and Apparatus for Ordered Partial Detection with MIMO Cooperation - In accordance with an example embodiment of the present invention, an apparatus comprising: at least one processor; and at least one memory including computer program code, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus to perform at least the following: receiving a MIMO (multiple-input multiple output) encoded symbol vector, the symbol vector encoding a plurality of streams of a source node; estimating channel matrix between the source node and the apparatus; re-ordering columns in said channel matrix; determining a plurality of feedback bits based at least in part on the re-ordered channel matrix, wherein each bit of the feedback bits indicates detection or no detection of the corresponding antenna streams of the source node; and transmitting the feedback bits. | 09-08-2011 |
20140096172 | SELECTIVE DISTRIBUTION OF CELL BASED VIDEO STREAMS OVER PACKET BASED NETWORKS - According to the present invention, methods and apparatus are provided to allow selective distribution of video information over packet based networks. Video information associated with a particular channel is received at an edge router from a cell based network. The edge router uses label switching to selectively distribute the video information to designated nodes in the packet based network. | 04-03-2014 |
Ren Wu, Palo Alto, CA US
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20110158527 | Color Constancy Method And System - A color constancy method and system include dividing an image into a plurality of sub-images and applying a plurality of color constancy algorithms to each of the sub-images. The outputs of each of the color constancy algorithms are analyzed for each of the sub-images to determine which of the color constancy algorithms give inconsistent results across the sub-images. The influence of the outputs of the algorithms providing inconsistent results is adjusted to decrease their influence (e.g. effect or weight) with respect to the outputs of algorithms providing consistent results. The outputs from the plurality of color constancy algorithms are combined based upon the adjustment of the outputs. | 06-30-2011 |
Shanchan Wu, Palo Alto, CA US
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20160124922 | Web Page Output Selection - Examples disclosed herein relate to web page output selection. A processor may determine the features of a section of a web page and assign a weight to each of the features respectively. The processor may determine a score for the section based on the weights of the features and determine to output the section based on the score. | 05-05-2016 |
Tzy-Chung Terry Wu, Palo Alto, CA US
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20100162954 | Integrated facility and process chamber for substrate processing - In accordance with some embodiments described herein, a process module facility is provided, comprising: at least one process chamber carried in frame, a subfloor adjacent the process module, a stationary pump and electrical box positioned atop the subfloor; and gas control lines and vacuum exhaust lines housed within the subfloor and coupled the process chamber. The process module facility may be integrated with a larger system for processing substrates which includes two or more process module facilities, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates. The transverse substrate handler further includes a rail for supporting the mobile transverse chambers, wherein the rail is positioned adjacent to entry of the process modules, and drive systems for moving the mobile transverse chambers on the rail. | 07-01-2010 |
20100162955 | Systems and methods for substrate processing - In accordance with some embodiments described herein, a system for processing substrates includes two or more process modules, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates. The transverse substrate handler further includes a rail for supporting the mobile transverse chambers, wherein the rail is positioned adjacent to entry of the process modules, and drive systems for moving the mobile transverse chambers on the rail. | 07-01-2010 |
20100167503 | Methods and systems of transferring, docking and processing substrates - In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more process modules, and wherein each mobile transverse chamber is configured to maintain a specified gas condition during conveyance of the substrate. One or more drive systems are actuated to propel at least one of the one or more mobile transverse chambers along the rail. The at least one mobile transfer chamber docks to at least one of the process modules, and the substrate is conveyed from the mobile transverse chamber to the at least one process modules. | 07-01-2010 |
20100173439 | Methods and systems of transferring a substrate to minimize heat loss - A method of transferring one or more substrates between process modules or load lock stations while minimizing heat loss is provided. In some embodiments the method comprising the steps of: identifying a destination location D1 for a substrate S1 present at an initial processing location P1; if the destination location D1 is occupied with a substrate S2, maintaining the substrate S1 at the initial processing location P1; and if the destination location D1 is available, transferring the substrate S1 to the destination location D1. In accordance with additional embodiments, the method is carried out on a system for processing substrates which includes two or more process modules, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates. The transverse substrate handler further includes a rail for supporting the mobile transverse chambers, wherein the rail is positioned adjacent to entry of the process modules, and drive systems for moving the mobile transverse chambers on the rail. | 07-08-2010 |
20110151119 | Methods and Systems of Transferring, Docking and Processing Substrates - In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more process modules, and wherein each mobile transverse chamber is configured to maintain a specified gas condition during conveyance of the substrate. One or more drive systems are actuated to propel at least one of the one or more mobile transverse chambers along the rail. The at least one mobile transfer chamber docks to at least one of the process modules, and the substrate is conveyed from the mobile transverse chamber to the at least one process modules. | 06-23-2011 |
20110217469 | Methods and Systems of Transferring, Docking and Processing Substrates - In accordance with some embodiments described herein, a method for transferring a substrate is provided. The method includes loading one or more substrates into a respective mobile chamber of one or more mobile chambers. The mobile chambers are movable on a first rail positioned adjacent to two or more process modules. Each mobile chamber is configured to maintain a specified gas condition. The respective mobile chamber is moved along the first rail. The respective mobile chamber is docked to a respective process module of the two or more process modules. At least one of the one or more substrates is conveyed from the respective mobile chamber to the respective process module. | 09-08-2011 |
Weiqing Wu, Palo Alto, CA US
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20160105392 | CENTRAL NAMESPACE CONTROLLER FOR MULTI-TENANT CLOUD ENVIRONMENTS - A centralized namespace controller allocates addresses in a distributed cloud infrastructure on-demand. Upon receiving a request to allocate addresses for a network to be provisioned by a cloud computing system included in the distributed cloud infrastructure, the centralized namespace controller allocates a network address that is unique within the distributed cloud infrastructure. Further, the centralized namespace controller allocates a range of virtual network interface cards (NIC) addresses that are unique within the network. The centralized namespace controller then allocates addresses from the range of virtual NIC addresses on an as-requested basis—when a virtual NIC is being created by the first cloud computing system on the network. Advantageously, by centralizing the allocation of addresses and dedicating independent NIC address ranges to different cloud computing systems, the centralized namespace controller enables stretched L2 networks between cloud computing systems while preventing duplicated addresses on the stretched networks. | 04-14-2016 |
20160105393 | CROSS-CLOUD NAMESPACE MANAGEMENT FOR MULTI-TENANT ENVIRONMENTS - Conditional address translation is performed in a multi-tenant cloud infrastructure to effectively support tenant-assigned addresses. For each tenant, the multi-tenant cloud infrastructure deploys both a private network used to communicate between the tenant and the cloud and a tenant-facing gateway to manage the private network. The multi-tenant cloud infrastructure also includes an externally-facing gateway used to communicate between the multi-tenant cloud and a public network. The tenant-facing gateways are configured to bypass address translation—providing consistent addressing across each private network irrespective of the physical location of resources linked by the private network. By contrast, the public-facing gateway is configured to translate source addresses in outgoing packets to addresses that are unique within the public network. Advantageously, discriminately mapping addresses enables multiple tenants to interact in a uniform fashion with both on-premises resources and cloud-hosted resources without incurring undesirable address collisions between tenants. | 04-14-2016 |
Yingpeng Wu, Palo Alto, CA US
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20150249261 | ULTRA-FAST RECHARGEABLE METAL-ION BATTERY - A metal-ion battery includes: (1) an anode including aluminum; (2) a cathode including a layered, active material; and (3) an electrolyte disposed between the anode and the cathode to support reversible deposition and dissolution of aluminum at the anode and reversible intercalation and de-intercalation of anions at the cathode. | 09-03-2015 |
Yingquan Wu, Palo Alto, CA US
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20130343131 | FAST TRACKING FOR FLASH CHANNELS - An SSD controller dynamically adjusts read thresholds in an NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller periodically performs offline tracking on a portion of the NVM. The controller reads a representative sub-portion with current read thresholds. If the read meets a condition, then the controller reads the sub-portion with sample read thresholds, estimates the device threshold voltage distributions, and adjusts the current read thresholds of the portion to calculated new operating read thresholds of the sub-portion. In a second aspect, the portion includes data with a known statistical average number of zero and/or one bits. | 12-26-2013 |
20140006896 | COMBINED KOETTER-VARDY AND CHASE DECODING OF CYCLIC CODES | 01-02-2014 |
20140013188 | ERROR RECOVERY FOR FLASH MEMORY - A set of data associated with a page in flash storage is received. Error correction decoding is performed on the set of data; if event error correction decoding fails, it is determined whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. If it is determined the page is a MSB page, one or more MSB read thresholds are adjusted and the is re-read page using the adjusted MSB read threshold(s). If it is determined the page is a LSB page, one or more LSB read thresholds are adjusted and the page is re-read using the adjusted LSB read threshold(s). | 01-09-2014 |
20140015697 | COMBINED WU AND CHASE DECODING OF CYCLIC CODES - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of symbols and (ii) a plurality of decision values both in response to detecting an encoded codeword. The second circuit may be configured to (i) generate a plurality of probabilities to flip one or more of the symbols based on the decision values, (ii) generate a modified probability by merging two or more of the probabilities of an unreliable position in the symbols and (iii) generate a decoded codeword by decoding the symbols using a list decode technique in response to the modified probability. | 01-16-2014 |
20140173380 | ERROR RECOVERY FOR FLASH MEMORY - An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. A third adjusted threshold associated with the page type is generated, including by: determining a first number of flipped bits using a first adjusted threshold associated with the page type, determining a second number of flipped bits using a second adjusted threshold associated with the page type, and generating the third adjusted threshold using the first number of flipped bits and the second number of flipped bits. | 06-19-2014 |
20140215285 | INTEGRATED-INTERLEAVED LOW DENSITY PARITY CHECK (LDPC) CODES - Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H | 07-31-2014 |
20140219033 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An indication to store a data value in Flash memory is received. An accurate coarse write is performed on the Flash memory, including by: storing a first voltage level in the Flash memory and setting a configuration setting of the Flash memory to a first setting. The first voltage level, when interpreted using the configuration setting at the first setting, corresponds to the data value. A fine write is performed on the Flash memory, including by: storing a second voltage level in the Flash memory and setting the configuration setting of the Flash memory to a second setting. The second voltage level, when interpreted using the configuration setting at the second setting, corresponds to the data value. | 08-07-2014 |
20140286102 | Method of Optimizing Solid State Drive Soft Retry Voltages - A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER. | 09-25-2014 |
20140298129 | Generating Partially Sparse Generator Matrix for a Quasi-Cyclic Low-Density Parity-Check Encoder - A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H′; and constructing the generator matrix G based on the rearranged parity check matrix H′. | 10-02-2014 |
20140376314 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction. | 12-25-2014 |
20150095735 | Integrated-Interleaved Low Density Parity Check (LDPC) Codes - Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H | 04-02-2015 |
20150154089 | ERROR RECOVERY FOR FLASH MEMORY - An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. A third adjusted threshold associated with the page type is generated, including by: determining a first number of flipped bits using a first adjusted threshold associated with the page type, determining a second number of flipped bits using a second adjusted threshold associated with the page type, and generating the third adjusted threshold using the first number of flipped bits and the second number of flipped bits. | 06-04-2015 |
20150235707 | FLASH MULTIPLE-PASS WRITE WITH ACCURATE FIRST-PASS WRITE - An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction. | 08-20-2015 |
20150287453 | OPTIMIZATION OF READ THRESHOLDS FOR NON-VOLATILE MEMORY - An SSD controller dynamically adjust read thresholds in a NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller periodically performs offline tracking on a portion of the NVM. The controller reads a representative sub-portion with current read thresholds. If the read meets a condition, then the controller reads the sub-portion with sample read thresholds, estimates the device threshold voltage distributions, and adjusts the current read thresholds of the portion to calculated new operating read thresholds of the sub-portion. In a second aspect, the portion includes data with a known statistical average number of zero and/or one bits. | 10-08-2015 |
20150326248 | DEFLATE COMPRESSION ALGORITHM - A compression algorithm replaces duplicative strings with a copy pair indicating a location and length of a preceding identical string that is within a window from the duplicative string. Rather than a replacing a longest matching string within a window from a given point with a copy pair, the longest matching string may be used provide it is at least two bytes larger than the next longest matching string or is at a distance that is less than some multiple of a distance to the next longest matching string. In another aspect, the length of the window in which a matching string may be found is dependent on a length of the matching string. In yet another aspect, rather than labeling each literal and copy pair to indicate what it is, strings of non-duplicative literals are represented by a label and a length of the string. | 11-12-2015 |
20150358031 | VLSI EFFICIENT HUFFMAN ENCODING APPARATUS AND METHOD - A compression algorithm based on Huffman coding is disclosed that is adapted to be readily implemented using VLSI design. A data file may be processed to replace duplicate data with a copy commands including an offset and length, such as according to the LV algorithm. A Huffman code may then be generated for parts of the file. The Huffman code may be generated according to a novel method that generates Huffman code lengths for literals in a data file without first sorting the literal statistics. The Huffman code lengths may be constrained to be no longer than a maximum length and the Huffman code may be modified to provide an acceptable overflow probability and be in canonical order. Literals, offsets, and lengths may be separately encoded. The different values for these data sets may be assigned to a limited number of bins for purpose of generating usage statistics used for generating Huffman codes. | 12-10-2015 |
20150365106 | DETERMINISTIC READ RETRY METHOD FOR SOFT LDPC DECODING IN FLASH MEMORIES - A method is disclosed for performing LDPC soft decoding of data stored in a flash storage device. Upon occurrence of a hard read failure, one or more retries with soft decoding after each retry are performed until soft decoding is successful or a maximum iteration count is reached. For each retry thresholds for sensing a level of a cell are adjusted according to a specific sequence. Likewise, the LLR table for each retry is selected from pre-determined LLR tables each corresponding to a retry attempt and the thresholds used for the retry attempt. The LLR table is not adjusted between retries or based on outcomes of any retries. A step size by which thresholds adjusted may be tuned to improve performance. | 12-17-2015 |
20160048531 | Adaptive Rate Compression Hash Processor - An input file is processed according to hash algorithm that references sets of literals to preceding sets of literals to facilitate copy-offset command generation. Preceding instances are identified by generating a hash of the literal set and looking up a corresponding entry in a hash table. The hash table may be accessed by placing look-up requests in a FIFO buffer. When the FIFO buffer is full, generation of the hash chain is suspended until it is no longer full. When repeated literals are found, generation of the hash chain is likewise suspended. The hash chain is used to generate a command file, such as according to the LZ algorithm. Runs of consecutive literals are replaced by a run-length command. The command file may then be encoded using Huffman encoding. | 02-18-2016 |
20160093396 | Read Retry For Non-Volatile Memories - An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns. | 03-31-2016 |
20160105199 | FAST MAPPING METHOD FOR LAYERED MIN-SUM DECODING OF LDPC CODES, - A method is disclosed for performing LDPC decoding, specifically layered min-sum decoding using a Tanner graph including check nodes (CN) and variable nodes (VN). Messages passed between nodes are quantized in a non-uniform manner. Values below a threshold are uniformly quantized whereas values above the threshold are non-uniformly quantized. A corresponding inverse-quantization is also defined. | 04-14-2016 |
Ying Quan Wu, Palo Alto, CA US
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20140269048 | RETENTION DETECTION AND/OR CHANNEL TRACKING POLICY IN A FLASH MEMORY BASED STORAGE SYSTEM - A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred. | 09-18-2014 |
Yongsheng Wu, Palo Alto, CA US
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20110246435 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR MAINTAINING DATA STORED IN A DATA STRUCTURE - There are provided mechanisms and methods for maintaining data stored in a data structure. These mechanisms and methods for maintaining data stored in a data structure can provide maintenance operations with improved efficiency, functionality, etc. | 10-06-2011 |
20110264434 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR COMPARING RESULTS OF PERFORMING A PLURALITY OF OPERATIONS WITH RESULTS OF SIMULATING THE PLURALITY OF OPERATIONS - In accordance with embodiments, there are provided mechanisms and methods for comparing results of performing a plurality of operations with results of simulating the plurality of operations. These mechanisms and methods for comparing results of performing a plurality of operations with results of simulating the plurality of operations can enable optimized performance of operations, reduced processing time, increased confidence in processing results, etc. | 10-27-2011 |